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82 Commits

Author SHA1 Message Date
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner
b2b32e9283 fix spello 
llvm-svn: 27053
 2006-03-24 07:15:07 +00:00
Chris Lattner
9fc969612c TargetData doesn't know the alignment of vectors :( 
llvm-svn: 26884
 2006-03-20 01:51:46 +00:00
Chris Lattner
da5f77e3cf Move some simple-sched-specific instance vars to the simple scheduler. 
llvm-svn: 26690
 2006-03-10 07:42:02 +00:00
Chris Lattner
ec2c5aa0bb prune #includes 
llvm-svn: 26689
 2006-03-10 07:37:35 +00:00
Chris Lattner
808cc02983 move some simple scheduler methods into the simple scheduler 
llvm-svn: 26688
 2006-03-10 07:35:21 +00:00
Chris Lattner
89a5a946f5 Make EmitNode take a SDNode instead of a NodeInfo* 
llvm-svn: 26687
 2006-03-10 07:28:36 +00:00
Chris Lattner
3f870d581e Move the VRBase field from NodeInfo to being a separate, explicit, map. 
llvm-svn: 26686
 2006-03-10 07:25:12 +00:00
Chris Lattner
ed528a5652 Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy 
llvm-svn: 26682
 2006-03-10 06:34:51 +00:00
Chris Lattner
3f23d22d3f Change the interface for getting a target HazardRecognizer to be more clean. 
llvm-svn: 26608
 2006-03-08 04:25:59 +00:00
Chris Lattner
5c28fdcae8 When a hazard recognizer needs noops to be inserted, do so. This represents 
noops as null pointers in the instruction sequence.

llvm-svn: 26564
 2006-03-05 23:51:47 +00:00
Evan Cheng
026fd6af96 Added an offset field to ConstantPoolSDNode. 
llvm-svn: 26371
 2006-02-25 09:54:52 +00:00
Chris Lattner
22356863a0 Pass all the flags to the asm printer, not just the # operands. 
llvm-svn: 26362
 2006-02-24 19:50:58 +00:00
Chris Lattner
f1e0c1f0a8 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. 
Add support for addressing modes.

llvm-svn: 26361
 2006-02-24 19:18:20 +00:00
Chris Lattner
e00cf77ecb Refactor operand adding out to a new AddOperand method 
llvm-svn: 26358
 2006-02-24 18:54:03 +00:00
Chris Lattner
b4951fbe82 Record all of the expanded registers in the DAG and machine instr, fixing 
several bugs in inline asm expanded operands.

llvm-svn: 26332
 2006-02-23 19:21:04 +00:00
Chris Lattner
86d5e100d2 Make MachineConstantPool entries alignments explicit 
llvm-svn: 26071
 2006-02-09 02:23:13 +00:00
Jeff Cohen
4f433dafa5 Fix VC++ warning. 
llvm-svn: 25975
 2006-02-04 16:20:31 +00:00
Evan Cheng
062ac6e46b Get rid of some memory leaks identified by Valgrind 
llvm-svn: 25960
 2006-02-04 06:49:00 +00:00
Chris Lattner
013f5fc2fa Add initial support for immediates. This allows us to compile this: 
int %rlwnm(int %A, int %B) {
  %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
  ret int %C
}

into:

_rlwnm:
        or r2, r3, r3
        or r3, r4, r4
        rlwnm r2, r2, r3, 4, 17    ;; note the immediates :)
        or r3, r2, r2
        blr

llvm-svn: 25955
 2006-02-04 02:26:14 +00:00
Evan Cheng
f115c17f23 Allow the specification of explicit alignments for constant pool entries. 
llvm-svn: 25855
 2006-01-31 22:23:14 +00:00
Chris Lattner
e113238f5c Handle physreg input/outputs. We now compile this: 
int %test_cpuid(int %op) {
        %B = alloca int
        %C = alloca int
        %D = alloca int
        %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
        %Bv = load int* %B
        %Cv = load int* %C
        %Dv = load int* %D
        %x = add int %A, %Bv
        %y = add int %x, %Cv
        %z = add int %y, %Dv
        ret int %z
}

to this:

_test_cpuid:
        sub %ESP, 16
        mov DWORD PTR [%ESP], %EBX
        mov %EAX, DWORD PTR [%ESP + 20]
        cpuid
        mov DWORD PTR [%ESP + 8], %ECX
        mov DWORD PTR [%ESP + 12], %EBX
        mov DWORD PTR [%ESP + 4], %EDX
        mov %ECX, DWORD PTR [%ESP + 12]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 8]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 4]
        add %EAX, %ECX
        mov %EBX, DWORD PTR [%ESP]
        add %ESP, 16
        ret

... note the proper register allocation.  :)

it is unclear to me why the loads aren't folded into the adds.

llvm-svn: 25827
 2006-01-31 02:03:41 +00:00
Chris Lattner
a1769576f0 Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an 
ISD::INLINEASM node.

llvm-svn: 25668
 2006-01-26 23:28:04 +00:00
Evan Cheng
168b8c5b29 No need to keep track of top and bottom nodes in a group since the vector is 
already in order. Thanks Jim for pointing it out.

llvm-svn: 25608
 2006-01-25 18:54:24 +00:00
Evan Cheng
d95c4530e7 Keep track of bottom / top element of a set of flagged nodes. 
llvm-svn: 25600
 2006-01-25 09:13:41 +00:00
Evan Cheng
37c62244a6 Factor out more instruction scheduler code to the base class. 
llvm-svn: 25532
 2006-01-23 07:01:07 +00:00
Evan Cheng
4a57a7551f Do some code refactoring on Jim's scheduler in preparation of the new list 
scheduler.

llvm-svn: 25493
 2006-01-21 02:32:06 +00:00
Duraid Madina
b9197e021f purity++ 
llvm-svn: 25041
 2005-12-29 05:59:19 +00:00
Jim Laskey
d82881490c Disengage DEBUG_LOC from non-PPC targets. 
llvm-svn: 24919
 2005-12-21 20:51:37 +00:00
Jim Laskey
2f4c62c51a Amend comment. 
llvm-svn: 24861
 2005-12-19 16:32:26 +00:00
Jim Laskey
57b66c8475 Create a strong dependency for loads following stores. This will leave a 
latency period between the two.

llvm-svn: 24860
 2005-12-19 16:30:13 +00:00
Jeff Cohen
d46f4d16d2 Keep VC++ happy. 
llvm-svn: 24835
 2005-12-18 22:20:05 +00:00
Jim Laskey
831eca00db Fix a bug Sabre was having where the DAG root was a group. The group dominator 
needed to be added to the ordering list, not the first member of the group.

llvm-svn: 24816
 2005-12-18 04:40:52 +00:00
Jim Laskey
a06085f024 Groups were not emitted if the dominator node and the node in the ordering list 
were not the same node.  Ultimately the test was bogus.

llvm-svn: 24815
 2005-12-18 03:59:21 +00:00
Chris Lattner
bb6af65f76 Simplify code 
llvm-svn: 24806
 2005-12-18 01:03:46 +00:00
Nate Begeman
811a41a87c Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Evan Cheng
025dab1137 Added an index field to GlobalAddressSDNode so it can represent X+12, etc. 
llvm-svn: 24523
 2005-11-30 02:04:11 +00:00
Chris Lattner
29585fd8c8 Switch the allnodes list from a vector of pointers to an ilist of nodes.This eliminates the vector, allows constant time removal of a node froma graph, and makes iteration over the all nodes list stable when adding 
nodes to the graph.

llvm-svn: 24263
 2005-11-09 23:47:37 +00:00
Chris Lattner
80717f007c Explicitly initialize some instance vars 
llvm-svn: 24247
 2005-11-08 21:54:57 +00:00
Jim Laskey
0c65e09865 Let's try ignoring resource utilization on the backward pass. 
llvm-svn: 24231
 2005-11-07 19:08:53 +00:00
Jim Laskey
5a3005b7d0 Fix logic bug in finding retry slot in tally. 
llvm-svn: 24188
 2005-11-05 00:01:25 +00:00
Jim Laskey
305647f84e Fix a warning 
llvm-svn: 24187
 2005-11-04 18:26:02 +00:00
Jim Laskey
670144ec9e Scheduling now uses itinerary data. 
llvm-svn: 24180
 2005-11-04 04:05:35 +00:00
Jim Laskey
8a0072ec92 1. Embed and not inherit vector for NodeGroup. 
2. Iterate operands and not uses (performance.)

3. Some long pending comment changes.

llvm-svn: 24119
 2005-10-31 12:49:09 +00:00
Chris Lattner
b0c50d1b7d Reduce the number of copies emitted as machine instructions by 
generating results in vregs that will need them.  In the case of something
like this:  CopyToReg((add X, Y), reg1024), we no longer emit code like
this:

   reg1025 = add X, Y
   reg1024 = reg 1025

Instead, we emit:

   reg1024 = add X, Y

Whoa! :)

llvm-svn: 24111
 2005-10-30 18:54:27 +00:00
Jim Laskey
2d23e75ac5 Inhibit instructions from being pushed before function calls. This will 
minimize unnecessary spilling.

llvm-svn: 23710
 2005-10-13 16:44:00 +00:00
Jim Laskey
2fe279f783 Finally committing to the new scheduler. Still -sched=none by default. 
llvm-svn: 23702
 2005-10-12 18:29:35 +00:00
Chris Lattner
d5ac294abd When emiting a CopyFromReg and the source is already a vreg, do not bother 
creating a new vreg and inserting a copy: just use the input vreg directly.

This speeds up the compile (e.g. about 5% on mesa with a debug build of llc)
by not adding a bunch of copies and vregs to be coallesced away.  On mesa,
for example, this reduces the number of intervals from 168601 to 129040
going into the coallescer.

llvm-svn: 23671
 2005-10-09 05:58:56 +00:00
Jim Laskey
9a2a3d4aab Reverting to version - until problem isolated. 
llvm-svn: 23622
 2005-10-04 16:41:51 +00:00
Jim Laskey
22633f7a41 Refactor gathering node info and emission. 
llvm-svn: 23610
 2005-10-03 12:30:32 +00:00