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Commit Graph

176112 Commits

Author SHA1 Message Date
Eugene Leviant
f0dc8144c5 [CGP] Fix UB when GEP is bound to trivial PHINode
Differential revision: https://reviews.llvm.org/D59140

llvm-svn: 355904
2019-03-12 10:10:29 +00:00
David Stuttard
bbae73ce2c [AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM

Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6

Reviewers: alexshap

Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59213

llvm-svn: 355902
2019-03-12 09:52:58 +00:00
Sjoerd Meijer
c1c71ee45e [TTI] Enable analysis of clib functions in getIntrinsicCosts. NFCI.
This is addressing the issue that we're not modeling the cost of clib functions
in TTI::getIntrinsicCosts and thus we're basically addressing this fixme:
    
// FIXME: This is wrong for libc intrinsics.

To enable analysis of clib functions, we not only need an intrinsic ID and
formal arguments, but also the actual user of that function so that we can e.g.
look at alignment and values of arguments. So, this is the initial plumbing to
pass the user of an intrinsinsic on to getCallCosts, which queries
getIntrinsicCosts.

Differential Revision: https://reviews.llvm.org/D59014

llvm-svn: 355901
2019-03-12 09:48:02 +00:00
Simon Tatham
f622a83e0d [TableGen] Allow 2^63-1 and 2^63-2 as int literals.
These two values correspond to the 'Empty' and 'Tombstone' special
keys defined by DenseMapInfo<int64_t>, which means that neither one
can be used as a key in DenseMap<int64_t, anything>. Hence, if you try
to use either of those values as an int literal, IntInit::get() fails
an assertion when it tries to insert them into its static cache of
int-literal objects.

Fixed by replacing the DenseMap with a std::map, which doesn't intrude
on the space of legal values of the key type.

Reviewers: nhaehnle, hfinkel, javedabsar, efriedma

Reviewed By: efriedma

Subscribers: fhahn, efriedma, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59016

llvm-svn: 355900
2019-03-12 09:28:19 +00:00
Alex Bradbury
f1498c6332 [RISCV] Add test cases for the lp64 ABI
These are closely modeled on similar tests for the ilp32 ABI. Like those
tests, we group together tests that should be common cross lp64, lp64+lp64f,
and lp64+lp64f+lp64d ABIs.

llvm-svn: 355899
2019-03-12 09:26:53 +00:00
Raphael Isemann
bfaa497048 Fix git-llvm crashing when trying to remove directory while cleaning
Summary:
I'm trying to push D59198 but it seems that `git-llvm push` can't handle the fact
that I add a new directory in the patch:

```
> git llvm push -n
Pushing 1 commit:
  e7c0a9bd136 Correctly look up declarations in inline namespaces
Traceback (most recent call last):
  File "llvm/utils/git-svn//git-llvm", line 431, in <module>
    args.func(args)
  File "llvm/utils/git-svn//git-llvm", line 385, in cmd_push
    clean_svn(svn_root)
  File "llvm/utils/git-svn//git-llvm", line 201, in clean_svn
    os.remove(os.path.join(svn_repo, filename))
IsADirectoryError: [Errno 21] Is a directory: '.git/llvm-upstream-svn/lldb/trunk/packages/Python/lldbsuite/test/expression_command/inline-namespace'
```

This patch just uses shutil to delete the directory instead of trying to use `os.remove`
which only works for files.

Reviewers: mehdi_amini, jlebar

Reviewed By: jlebar

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59236

llvm-svn: 355896
2019-03-12 07:40:54 +00:00
Kristina Brooks
2641089362 Very minor typo. NFC
Typo `we we're` => `we were` in the pass EarlyCSE

Patch by liangdzou (Liang ZOU)

Differential Revision: https://reviews.llvm.org/D59241

llvm-svn: 355895
2019-03-12 07:08:19 +00:00
Peter Collingbourne
ab72ac7186 llvm-objcopy: Remove unused field. NFCI.
Differential Revision: https://reviews.llvm.org/D59126

llvm-svn: 355892
2019-03-12 02:17:01 +00:00
Sanjoy Das
c6d3c3a4b5 Reland "Relax constraints for reduction vectorization"
Change from original commit: move test (that uses an X86 triple) into the X86
subdirectory.

Original description:
Gating vectorizing reductions on *all* fastmath flags seems unnecessary;
`reassoc` should be sufficient.

Reviewers: tvvikram, mkuper, kristof.beyls, sdesmalen, Ayal

Reviewed By: sdesmalen

Subscribers: dcaballe, huntergr, jmolloy, mcrosier, jlebar, bixia, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57728

llvm-svn: 355889
2019-03-12 01:31:44 +00:00
Nathan Lanza
0368dcdd6e Add Swift enumerator value for CodeView::SourceLanguage
Summary:
Swift now generates PDBs for debugging on Windows. llvm and lldb
need a language enumerator value too properly handle the output
emitted by swiftc.

Subscribers: jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59231

llvm-svn: 355882
2019-03-11 23:27:59 +00:00
David Blaikie
feb6347be0 Hexagon RDF: Replace function template (plus explicit specializations) with non-template overloads
For the design in question, overloads seem to be a much simpler and less subtle solution.

This removes ODR issues, and errors of the kind where code that uses the
specialization in question will accidentally and erroneously specialize
the primary template. This only "works" by accident; the program is
ill-formed NDR.

(Found with -Wundefined-func-template.)

Patch by Thomas Köppe!

Differential Revision: https://reviews.llvm.org/D58998

llvm-svn: 355880
2019-03-11 23:10:33 +00:00
Sanjoy Das
244bc57544 Revert "Relax constraints for reduction vectorization"
This reverts commit r355868.  Breaks hexagon.

llvm-svn: 355873
2019-03-11 22:37:31 +00:00
Craig Topper
365e5dc779 [X86] Remove ProcModel and ProcFeatures tablegen classes. Move all feature lists into a ProcessorFeatures class.
ProcFeatures was a class that just concatenated two feature lists together and gave it a name. We used it to inherit features between CPUs.

ProcModel took a two CPU feature lists and concatenated them before deferring to ProcessorModel. This was to allow inherited features and specific features to be passed to each CPU.

Both of these allowed for only very rigid CPU inheritance rules.

With this patch we now store all of the lists we were using for inheritance in one object and do any list oncatenation we want there. Then we just pass whatever list we want from this class into the ProcessorModel class for each CPU.

Hopefully this gives us more flexibility to build up feature lists in whatever ways we think make sense. Perhaps untangling ISA flags and tuning flags.

I've only touched the CPUs that were directly affected by the removal of the ProcModel and ProcFeatures classes. We should move more of the feature lists into ProcessorFeatures.

llvm-svn: 355872
2019-03-11 22:29:00 +00:00
Jessica Paquette
9202e8eb2a Recommit "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT"
After r355865, we should be able to safely select G_EXTRACT_VECTOR_ELT without
running into any problematic intrinsics.

Also add a fix for lane copies, which don't support index 0.

llvm-svn: 355871
2019-03-11 22:18:01 +00:00
Evgeniy Stepanov
5fdfe239d2 Remove ASan asm instrumentation.
Summary: It is incomplete and has no users AFAIK.

Reviewers: pcc, vitalybuka

Subscribers: srhines, kubamracek, mgorny, krytarowski, eraman, hiraditya, jdoerfert, #sanitizers, llvm-commits, thakis

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D59154

llvm-svn: 355870
2019-03-11 21:50:10 +00:00
Alex Bradbury
fb784a2c47 [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A
AtomicCmpSwapWithSuccess is legalised into an AtomicCmpSwap plus a comparison.
This requires an extension of the value which, by default, is a
zero-extension. When we later lower AtomicCmpSwap into a PseudoCmpXchg32 and then expanded in
RISCVExpandPseudoInsts.cpp, the lr.w instruction does a sign-extension.

This mismatch of extensions causes the comparison to fail when the compared
value is negative. This change overrides TargetLowering::getExtendForAtomicOps
for RISC-V so it does a sign-extension instead.

Differential Revision: https://reviews.llvm.org/D58829
Patch by Ferran Pallarès Roca.

llvm-svn: 355869
2019-03-11 21:41:22 +00:00
Sanjoy Das
367bdd4c9b Relax constraints for reduction vectorization
Summary:
Gating vectorizing reductions on *all* fastmath flags seems unnecessary;
`reassoc` should be sufficient.

Reviewers: tvvikram, mkuper, kristof.beyls, sdesmalen, Ayal

Reviewed By: sdesmalen

Subscribers: dcaballe, huntergr, jmolloy, mcrosier, jlebar, bixia, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57728

llvm-svn: 355868
2019-03-11 21:36:41 +00:00
Alex Bradbury
b9e1cd8de0 [RISCV] Allow fp as an alias of s0
The RISC-V Assembly Programmer's Manual defines fp as another alias of x8.
However, our tablegen rules only recognise s0. This patch adds fp as another
alias of x8. GCC also accepts fp.

Differential Revision: https://reviews.llvm.org/D59209
Patch by Ferran Pallarès Roca.

llvm-svn: 355867
2019-03-11 21:35:26 +00:00
Jessica Paquette
1d2b488ef7 [GlobalISel][AArch64] Always fall back on aarch64.neon.addp.*
Overloaded intrinsics aren't necessarily safe for instruction selection. One
such intrinsic is aarch64.neon.addp.*.

This is a temporary workaround to ensure that we always fall back on that
intrinsic. Eventually this will be replaced with a proper solution.

https://bugs.llvm.org/show_bug.cgi?id=40968

Differential Revision: https://reviews.llvm.org/D59062

llvm-svn: 355865
2019-03-11 20:51:17 +00:00
Alex Bradbury
dd6e68f13e [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()
llvm-svn: 355864
2019-03-11 20:43:29 +00:00
Nico Weber
2b90fade91 Remove esan.
It hasn't seen active development in years, and it hasn't reached a
state where it was useful.

Remove the code until someone is interested in working on it again.

Differential Revision: https://reviews.llvm.org/D59133

llvm-svn: 355862
2019-03-11 20:23:40 +00:00
Nikita Popov
b4de4b44fe [SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.

Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.

This also includes a few more changes to make this work somewhat
reasonably:

 * Add support for expanding VECREDUCE in SDAG. Usually
   experimental.vector.reduce is expanded prior to codegen, but if the
   target does have native vector reduce, it may of course still be
   necessary to expand due to legalization issues. This uses a shuffle
   reduction if possible, followed by a naive scalar reduction.
 * Allow the result type of integer VECREDUCE to be larger than the
   vector element type. For example we need to be able to reduce a v8i8
   into an (nominally) i32 result type on AArch64.
 * Use the vector operand type rather than the scalar result type to
   determine the action, so we can control exactly which vector types are
   supported. Also change the legalize vector op code to handle
   operations that only have vector operands, but no vector results, as
   is the case for VECREDUCE.
 * Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
   explicitly specify for which vector types the reductions are supported.

This does not handle anything related to VECREDUCE_STRICT_*.

Differential Revision: https://reviews.llvm.org/D58015

llvm-svn: 355860
2019-03-11 20:22:13 +00:00
Nico Weber
282bbd75f6 gn build: Merge r355777
llvm-svn: 355857
2019-03-11 19:30:13 +00:00
Nico Weber
fa20902c5a gn build: Merge r355835
llvm-svn: 355856
2019-03-11 19:14:22 +00:00
Nico Weber
bf84eebf59 gn build: Merge r355834
llvm-svn: 355855
2019-03-11 19:11:15 +00:00
Jonas Paulsson
132f812a12 [RegAlloc] Avoid compile time regression with multiple copy hints.
As a fix for https://bugs.llvm.org/show_bug.cgi?id=40986 ("excessive compile
time building opencollada"), this patch makes sure that no phys reg is hinted
more than once from getRegAllocationHints().

This handles the case were many virtual registers are assigned to the same
physreg. The previous compile time fix (r343686) in weightCalcHelper() only
made sure that physical/virtual registers are passed no more than once to
addRegAllocationHint().

Review: Dimitry Andric, Quentin Colombet
https://reviews.llvm.org/D59201

llvm-svn: 355854
2019-03-11 19:00:37 +00:00
Brian Gesiak
b996a21cd8 [coroutines][PR40979] Ignore unreachable uses across suspend points
Summary:
Depends on https://reviews.llvm.org/D59069.

https://bugs.llvm.org/show_bug.cgi?id=40979 describes a bug in which the
-coro-split pass would assert that a use was across a suspend point from
a definition. Normally this would mean that a value would "spill" across
a suspend point and thus need to be stored in the coroutine frame. However,
in this case the use was unreachable, and so it would not be necessary
to store the definition on the frame.

To prevent the assert, simply remove unreachable basic blocks from a
coroutine function before computing spills. This avoids the assert
reported in PR40979.

Reviewers: GorNishanov, tks2103

Reviewed By: GorNishanov

Subscribers: EricWF, jdoerfert, llvm-commits, lewissbaker

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59068

llvm-svn: 355852
2019-03-11 18:31:28 +00:00
Michael Trent
0a7d883761 Detect malformed LC_LINKER_COMMANDs in Mach-O binaries
Summary:
llvm-objdump can be tricked into reading beyond valid memory and
segfaulting if LC_LINKER_COMMAND strings are not null terminated. libObject
does have code to validate the integrity of the LC_LINKER_COMMAND struct,
but this validator improperly assumes linker command strings are null
terminated.

The solution is to report an error if a string extends beyond the end of
the LC_LINKER_COMMAND struct.

Reviewers: lhames, pete

Reviewed By: pete

Subscribers: rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59179

llvm-svn: 355851
2019-03-11 18:29:25 +00:00
Simon Pilgrim
ade83e4a31 [X86] Extend widening comparison test.
Ensure we test both v2i16 unary and binary comparisons.

llvm-svn: 355849
2019-03-11 18:08:20 +00:00
Jinsong Ji
1cca201a0c [NFC][PowerPC] Add comment for PPCAsmPrinter::printOperand
Patch by Yi-Hong Lyu

llvm-svn: 355848
2019-03-11 17:57:49 +00:00
Simon Pilgrim
d450878638 [DAG] FoldSetCC - reuse valuetype + ensure its simple.
llvm-svn: 355847
2019-03-11 17:56:18 +00:00
Brian Gesiak
0f1d71d29d [Utils] Extract EliminateUnreachableBlocks (NFC)
Summary:
Extract the functionality of eliminating unreachable basic blocks
within a function, previously encapsulated within the
-unreachableblockelim pass, and make it available as a function within
BlockUtils.h. No functional change intended other than making the logic
reusable.

Exposing this logic makes it easier to implement
https://reviews.llvm.org/D59068, which fixes coroutines bug
https://bugs.llvm.org/show_bug.cgi?id=40979.

Reviewers: mkazantsev, wmi, davidxl, silvas, davide

Reviewed By: davide

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59069

llvm-svn: 355846
2019-03-11 17:51:57 +00:00
Simon Pilgrim
da2ae38874 [DAG] Move SetCC NaN handling into FoldSetCC
llvm-svn: 355845
2019-03-11 17:43:10 +00:00
Stanislav Mekhanoshin
9260748488 Use bitset for assembler predicates
AMDGPU target run out of Subtarget feature flags hitting the limit of 64.
AssemblerPredicates uses at most uint64_t for their representation.
At the same time CodeGen has exhausted this a long time ago and switched
to a FeatureBitset with the current limit of 192 bits.

This patch completes transition to the bitset for feature bits extending
it to asm matcher and MC code emitter.

Differential Revision: https://reviews.llvm.org/D59002

llvm-svn: 355839
2019-03-11 17:04:35 +00:00
Craig Topper
b9b16d334d [TableGen] Replace a dyn_cast with isa to avoid an unused variable warning introduced in r355785. NFC
llvm-svn: 355837
2019-03-11 16:51:37 +00:00
Stanislav Mekhanoshin
c17ae456cc [AMDGPU] Mark enum types in SIDefines.h as unsigned
MSVC issues some warnings about signed/unsigned comparison.

Differential Revision: https://reviews.llvm.org/D59171

llvm-svn: 355836
2019-03-11 16:49:32 +00:00
Jeremy Morse
8f39e6c547 [SimplifyCFG] Retain debug info when threading jumps with critical edges
Fixes bug 38023: https://bugs.llvm.org/show_bug.cgi?id=38023

The SimplifyCFG pass will perform jump threading in some cases where
doing so is trivial and would simplify the CFG. When folding a series
of blocks with redundant conditional branches into an unconditional "critical
edge" block, it does not keep the debug location associated with the previous
conditional branch.

This patch fixes the bug described by copying the debug info from the
old conditional branch to the new unconditional branch instruction, and
adds a regression test for the SimplifyCFG pass that covers this case.

Patch by Stephen Tozer!

Differential Revision: https://reviews.llvm.org/D59206

llvm-svn: 355833
2019-03-11 16:23:59 +00:00
George Rimar
757b91db38 [yaml2obj] - Simplify. NFC.
llvm-svn: 355832
2019-03-11 16:10:02 +00:00
Simon Pilgrim
8e975721b4 [DAG] TargetLowering::SimplifySetCC - call FoldSetCC early to handle constant/commute folds.
Noticed while looking at PR40800 (and also D57921)

llvm-svn: 355828
2019-03-11 15:01:31 +00:00
Petar Jovanovic
36f3268eb1 [MIPS][microMIPS] Add a pattern to match TruncIntFP
A pattern needed to match TruncIntFP was missing. This was causing multiple
tests from llvm test suite to fail during compilation for micromips.

Patch by Mirko Brkusanin.

Differential Revision: https://reviews.llvm.org/D58722

llvm-svn: 355825
2019-03-11 14:13:31 +00:00
Sam Parker
f7c5332c4e [CGP] Limit distance between overflow math and cmp
Inserting an overflowing arithmetic intrinsic can increase register
pressure by producing two values at a point where only one is needed,
while the second use maybe several blocks away. This increase in
pressure is likely to be more detrimental on performance than
rematerialising one of the original instructions.
    
So, check that the arithmetic and compare instructions are no further
apart than their immediate successor/predecessor.

Differential Revision: https://reviews.llvm.org/D59024

llvm-svn: 355823
2019-03-11 13:19:46 +00:00
Jeremy Morse
99177e68e5 [JumpThreading] Retain debug info when replacing branch instructions
Fixes bug 37966: https://bugs.llvm.org/show_bug.cgi?id=37966

The Jump Threading pass will replace certain conditional branch
instructions with unconditional branches when it can prove that only one
branch can occur. Prior to this patch, it would not carry the debug
info from the old instruction to the new one.

This patch fixes the bug described by copying the debug info from the
conditional branch instruction to the new unconditional branch
instruction, and adds a regression test for the Jump Threading pass that
covers this case.

Patch by Stephen Tozer!

Differential Revision: https://reviews.llvm.org/D58963

llvm-svn: 355822
2019-03-11 11:48:57 +00:00
George Rimar
3e5b9fe4cd [llvm-objcopy] - Fix --compress-debug-sections when there are relocations.
When --compress-debug-sections is given,
llvm-objcopy removes the uncompressed sections and adds compressed to the section list.
This makes all the pointers to old sections to be outdated.

Currently, code already has logic for replacing the target sections of the relocation
sections. But we also have to update the relocations by themselves.

This fixes https://bugs.llvm.org/show_bug.cgi?id=40885.

Differential revision: https://reviews.llvm.org/D58960

llvm-svn: 355821
2019-03-11 11:01:24 +00:00
Benjamin Kramer
0d75a1cb6a [MIPS GlobalISel] Silence uninitialized variable warning
The control flow here cannot ever use the uninitialized value, but it's
too hard for the compiler to figure that out. Clang warns:

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2600:28: error: variable 'CarrySum' is used uninitialized whenever 'for' loop exits because its condition is false [-Werror,-Wsometimes-uninitialized]
      for (unsigned i = 2; i < Factors.size(); ++i)
                           ^~~~~~~~~~~~~~~~~~
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2604:26: note: uninitialized use occurs here
    CarrySumPrevDstIdx = CarrySum;
                         ^~~~~~~~
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2600:28: note: remove the condition if it is always true
      for (unsigned i = 2; i < Factors.size(); ++i)
                           ^~~~~~~~~~~~~~~~~~
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2583:22: note: initialize the variable 'CarrySum' to silence this warning
    unsigned CarrySum;
                     ^
                      = 0

llvm-svn: 355818
2019-03-11 10:39:15 +00:00
Petar Avramovic
fea74b4874 [MIPS GlobalISel] NarrowScalar G_UMULH
NarrowScalar G_UMULH in LegalizerHelper 
using multiplyRegisters helper function.
NarrowScalar G_UMULH for MIPS32.

Differential Revision: https://reviews.llvm.org/D58825

llvm-svn: 355815
2019-03-11 10:08:44 +00:00
Petar Avramovic
4df118146b [MIPS GlobalISel] NarrowScalar G_MUL
Narrow Scalar G_MUL for MIPS32.
Revisit NarrowScalar implementation in LegalizerHelper.
Introduce new helper function multiplyRegisters.
It performs generic multiplication of values held in multiple registers.
Generated instructions use only types NarrowTy and i1.
Destination can be same or two times size of the source.

Differential Revision: https://reviews.llvm.org/D58824

llvm-svn: 355814
2019-03-11 10:00:17 +00:00
Pavel Labath
c742abf450 Attempt to fix build errors caused by r355812
llvm-svn: 355813
2019-03-11 09:23:30 +00:00
Pavel Labath
aa70828a6f [Support/Endian] Add support for endian-specific enums
Summary:
Binary formats often include various enumerations or bitsets, but using
endian-specific types for accessing them is tricky because they
currently only support integral types. This is particularly true for
scoped enums (enum class), as these are not implicitly convertible to
integral types, and so one has to perform two casts just to read the
enum value.

This fixes that support by adding first-class support for enumeration
types to endian-specific types. The support for them was already almost
working -- all I needed to do was overload getSwappedBytes for
enumeration types (which casts the enum to its underlying type and performs the
conversion there). I also add some convenience template aliases to simplify
declaring endian-specific enums.

Reviewers: Bigcheese, zturner

Subscribers: kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59141

llvm-svn: 355812
2019-03-11 09:06:18 +00:00
Craig Topper
c4befaef73 [X86] Enable sse2_cvtsd2ss intrinsic to use an EVEX encoded instruction.
llvm-svn: 355810
2019-03-11 06:01:04 +00:00
Craig Topper
3317157532 [X86] Remove apparently unneeded patterns for storing a bitcasted extractelement.
I suspect if this pattern was seen, DAG combine would just change the type of the store to eliminate the bitcast.

llvm-svn: 355809
2019-03-11 06:01:02 +00:00