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7655 Commits

Author SHA1 Message Date
Rafael Espindola
daefe7aa54 Use movq to move 64 bits in and out of mmx registers. 
Fixes PR4669

llvm-svn: 77940
 2009-08-03 02:45:34 +00:00
Evan Cheng
27ee95d344 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. 
llvm-svn: 77939
 2009-08-03 02:38:06 +00:00
Andreas Bolka
d713824363 Expand LDA testcases. 
llvm-svn: 77926
 2009-08-02 23:28:14 +00:00
Richard Osborne
179bf3bdc2 Add extra SEXT pattern. 
llvm-svn: 77920
 2009-08-02 22:45:24 +00:00
Jakob Stoklund Olesen
0f9cf8a32b Remove unneeded intrinsics from Blackfin backend. 
__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.

__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.

We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.

llvm-svn: 77917
 2009-08-02 21:49:05 +00:00
Jakob Stoklund Olesen
9e71890531 Fix issue in regscavenger when scavenging a callee-saved register that has not been spilled. 
llvm-svn: 77912
 2009-08-02 20:29:41 +00:00
Jakob Stoklund Olesen
fe8f36d66b Never add a kill flag to a constrained physical register in a two-addr instruction. 
llvm-svn: 77906
 2009-08-02 19:13:03 +00:00
Jakob Stoklund Olesen
a726715be6 Scavenger asserts. 
Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier.
Allow redefinition of a sub-register of a live register.

llvm-svn: 77904
 2009-08-02 18:28:41 +00:00
Jakob Stoklund Olesen
23ad8d1848 Add some basic blackfin intrinsics. 
llvm-svn: 77903
 2009-08-02 18:28:11 +00:00
Jakob Stoklund Olesen
5c6e03f669 Inline assembly support for Blackfin. 
We use the same constraints as GCC, including those that are slightly insane for inline assembler.

llvm-svn: 77899
 2009-08-02 17:39:17 +00:00
Jakob Stoklund Olesen
e7eb74ef39 Analog Devices Blackfin back-end. 
Generate code for the Blackfin family of DSPs from Analog Devices:

  http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
  
We aim to be compatible with the exsisting GNU toolchain found at:

  http://blackfin.uclinux.org/gf/project/toolchain
  
The back-end is experimental.

llvm-svn: 77897
 2009-08-02 17:32:10 +00:00
Evan Cheng
3c2d9a0698 Test both darwin and linux. 
llvm-svn: 77852
 2009-08-02 02:54:34 +00:00
Chris Lattner
1e3d2247ba switch to filecheck format 
llvm-svn: 77841
 2009-08-02 00:32:26 +00:00
Chris Lattner
e1cc2c27b3 fix a problem Eli noticed where we would compile the attached ptrtoint 
to:

.quad X

even on a 32-bit system, where X is not 64-bits.  There isn't much that
we can do here, so we just print:

.quad	((X) & 4294967295)

instead.

llvm-svn: 77818
 2009-08-01 22:25:12 +00:00
Dan Gohman
512a0d9f42 Add nounwind to this test. 
llvm-svn: 77792
 2009-08-01 19:11:04 +00:00
Eli Friedman
cd4d9ff7fa Hack to make this test work on platforms which aren't Macs. Fixing this 
myself because I'm getting tired of seeing the red buildbots, which have 
been red since 5:30PM PDT last night.

Proposed supplement to developer policy: committers should make sure to 
be around to watch for buildbot failures after committing.

llvm-svn: 77785
 2009-08-01 16:37:18 +00:00
Evan Cheng
b9b4b9aa15 Workaround a couple of Darwin assembler bugs. 
llvm-svn: 77781
 2009-08-01 06:13:52 +00:00
Daniel Dunbar
c4efea5c56 Avoid a problem with ulimit on Solaris & friends, patch by Edward O'Callaghan! 
llvm-svn: 77767
 2009-08-01 03:37:54 +00:00
Evan Cheng
c165700a7f Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
llvm-svn: 77764
 2009-08-01 01:43:45 +00:00
Daniel Dunbar
7fd7e31119 llvm-mc: More quoted identifier support. 
llvm-svn: 77761
 2009-08-01 00:48:30 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
Daniel Dunbar
39929d9343 llvm-mc: Add -triple, and fix some typos 
llvm-svn: 77750
 2009-07-31 23:13:12 +00:00
Daniel Dunbar
a848745eb4 llvm-mc: Fix .s output to quote section & symbol names when necessary. 
llvm-svn: 77749
 2009-07-31 23:04:32 +00:00
Daniel Dunbar
99d279978e llvm-mc: A few more parsing / match tweaks. 
- Operands which are just a label should be parsed as immediates, not memory
   operands (from the assembler perspective).

 - Match a few more flavors of immediates.

 - Distinguish match functions for memory operands which don't take a segment
   register.

 - We match the .s for "hello world" now!

llvm-svn: 77745
 2009-07-31 22:22:54 +00:00
David Greene
543296ed84 Simplify operand padding by keying off tabs in the asm stream. If 
padding is disabled, tabs get replaced by spaces except in the case of
the first operand, where the tab is output to line up the operands after
the mnemonics.

Add some better comments and eliminate redundant code.

Fix some testcases to not assume tabs.

llvm-svn: 77740
 2009-07-31 21:57:10 +00:00
Daniel Dunbar
e150b07b71 llvm-mc: Support quoted identifiers. 
- Uses MCAsmToken::getIdentifier which returns the (sub)string representing the
   meaningfull contents a string or identifier token.

 - Directives aren't done yet.

llvm-svn: 77739
 2009-07-31 21:55:09 +00:00
Daniel Dunbar
3c72ed6449 llvm-mc/X86: Sketch match functions for immediates and memory operands. 
Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.

llvm-svn: 77728
 2009-07-31 20:53:16 +00:00
Eli Friedman
7bb0485237 PR4662: Fix a crash introduced by the recent LLVMContext changes. 
llvm-svn: 77716
 2009-07-31 19:36:47 +00:00
Chris Lattner
75b7692e66 switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.

llvm-svn: 77708
 2009-07-31 18:48:30 +00:00
Evan Cheng
0c9705feed Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.

llvm-svn: 77705
 2009-07-31 18:35:56 +00:00
Chris Lattner
85a3632c7a fix PR4650: we only track sizes for certain objects, so only put something 
into the mergable section if it is one of our special cases.  This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.

llvm-svn: 77679
 2009-07-31 16:17:13 +00:00
Daniel Dunbar
813b35a4b7 Add this test back, the check pattern was too strict. 
llvm-svn: 77662
 2009-07-31 03:11:49 +00:00
Daniel Dunbar
ed28c20ca7 Remove this test while I figure out why it is failing. 
llvm-svn: 77659
 2009-07-31 02:46:36 +00:00
Daniel Dunbar
41639473ed llvm-mc: Match a few X86 instructions. 
- This is "experimental" code, I am feeling my way around and working out the
   best way to do things (and learning tblgen in the process). Comments welcome,
   but keep in mind this stuff will change radically.

 - This is enough to match "subb" and friends, but not much else. The next step is to
   automatically generate the matchers for individual operands.

llvm-svn: 77657
 2009-07-31 02:32:59 +00:00
Evan Cheng
c9f31ae969 When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
llvm-svn: 77642
 2009-07-30 23:29:25 +00:00
Devang Patel
c3f4aa73cc Do not use abbrev while writing NamedMDNode name. 
llvm-svn: 77637
 2009-07-30 23:06:35 +00:00
David Goodwin
62efc71b9f Darwin assembler now recognizes "orn", so remove workaround. 
llvm-svn: 77627
 2009-07-30 21:51:41 +00:00
David Goodwin
d29f81da16 Darwin assembler now supports "rrx", so remove workaround. 
llvm-svn: 77625
 2009-07-30 21:38:40 +00:00
David Goodwin
2eaffa79af Cleanup and include code selection for some frame index cases. 
llvm-svn: 77622
 2009-07-30 18:56:48 +00:00
Evan Cheng
148032a1a2 Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582
 2009-07-30 08:33:02 +00:00
Dan Gohman
3c7e8160f6 Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565
 2009-07-30 01:56:29 +00:00
Evan Cheng
31ac181755 tbb / tbh instructions only branch forward, not backwards. 
llvm-svn: 77522
 2009-07-29 23:20:20 +00:00
Evan Cheng
fabbd6219a Add VFP3 D registers to the DPR register class. 
llvm-svn: 77521
 2009-07-29 23:03:41 +00:00
Devang Patel
d5b7c64109 Read and write NamedMDNode. 
llvm-svn: 77517
 2009-07-29 22:34:41 +00:00
Daniel Dunbar
89cb72a6bc Fix PR4645 which was fallout from the fix for PR4641. 
- Call RAUW to delete all instructions (this is a patch from Nick Lewycky).

llvm-svn: 77512
 2009-07-29 22:00:43 +00:00
Evan Cheng
9712360f80 xfail for now. 
llvm-svn: 77478
 2009-07-29 17:40:28 +00:00
Bob Wilson
355e0b70e0 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.

llvm-svn: 77468
 2009-07-29 16:39:22 +00:00
Nick Lewycky
1961298b63 Just discard the output, no need to turn it back into text. 
llvm-svn: 77439
 2009-07-29 06:14:52 +00:00
Chris Lattner
e5f1099d05 don't dump .bc file to stdout, and simplify this to a trivial testcase. 
llvm-svn: 77436
 2009-07-29 05:32:07 +00:00
Chris Lattner
f8a9c2f843 fix PR4584 with a trivial patch now that the pieces are in place. 
llvm-svn: 77434
 2009-07-29 05:20:33 +00:00
Nick Lewycky
e0524c1795 Bulk erasing instructions without RAUWing them is unsafe. Instead, break them 
into a new BB that has no predecessors.

llvm-svn: 77433
 2009-07-29 05:17:50 +00:00
Evan Cheng
fc846dd401 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
Eric Christopher
88c1b51020 Add a couple more tests for the ptest intrinsics to make sure we're 
grabbing them all correctly.

llvm-svn: 77413
 2009-07-29 00:51:15 +00:00
Eric Christopher
c7b97d1f03 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.

llvm-svn: 77407
 2009-07-29 00:28:05 +00:00
Andreas Bolka
7d6b4c24e6 Slightly reformat LDA tests to ease grepping. 
llvm-svn: 77398
 2009-07-28 23:40:40 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin
0c9e96bf09 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
David Goodwin
dbc23ece04 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
Chris Lattner
a8faf6b1b6 fix testcase for previous patch. 
llvm-svn: 77338
 2009-07-28 18:04:18 +00:00
Chris Lattner
986bd2bd0a Fix PR4639, a ELF-TLS regression from some of my refactoring. 
llvm-svn: 77336
 2009-07-28 17:57:51 +00:00
David Goodwin
e94d490b89 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng
05555a7d31 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
llvm-svn: 77305
 2009-07-28 07:38:35 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
Dan Gohman
0d0dd7b732 Teach instcombine to respect and preserve inbounds. Add inbounds 
to a few tests where it is required for the expected transformation.

llvm-svn: 77290
 2009-07-28 01:40:03 +00:00
David Goodwin
0bcb94eeff ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
Daniel Dunbar
3edfc4bb16 llvm-mc: Implement .abort fully in the front end 
llvm-svn: 77272
 2009-07-27 23:20:52 +00:00
Dan Gohman
490eb36e1d Add a new keyword 'inbounds' for use with getelementptr. See the 
LangRef.html changes for details.

llvm-svn: 77259
 2009-07-27 21:53:46 +00:00
David Goodwin
471e9f5b8d Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Sanjiv Gupta
f39c96217b Test case to check that separate section is created for a global variable specified with section attribute. 
llvm-svn: 77195
 2009-07-27 16:20:41 +00:00
Dan Gohman
39c0d3b10a Change the assembly syntax for nsw, nuw, and exact, putting them 
after their associated opcodes rather than before. This makes them
a little easier to read.

llvm-svn: 77194
 2009-07-27 16:11:46 +00:00
Chris Lattner
19c9914343 update testcase. 
llvm-svn: 77192
 2009-07-27 15:52:58 +00:00
Chris Lattner
5547fd80ad put normal data into .data instead of .data.rel on elf systems. 
llvm-svn: 77116
 2009-07-26 03:06:11 +00:00
Chris Lattner
9cd489c7f1 finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal 
for now.  Make the section switching directives more consistent
by not including \n and including \t for them all.

llvm-svn: 77107
 2009-07-26 01:24:18 +00:00
Chris Lattner
b95150b65a simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bit 
and make it more aggressive, we now put:

const int G2 __attribute__((weak)) = 42;

into the text (readonly) segment like gcc, previously we put
it into the data (readwrite) segment.

llvm-svn: 77104
 2009-07-26 00:51:36 +00:00
Bob Wilson
ec256c8938 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.

llvm-svn: 77101
 2009-07-26 00:39:34 +00:00
Chris Lattner
cf7cc0ed7d add the most expedient hack to fix PR4619, along with a testcase. 
Thanks to Rafael for the great example.

llvm-svn: 77083
 2009-07-25 17:57:37 +00:00
Dan Gohman
c126330ef1 When attempting to sign-extend an addrec by interpreting 
the step value as unsigned, the start value and the addrec
itself still need to be treated as signed.

llvm-svn: 77078
 2009-07-25 16:03:30 +00:00
Chris Lattner
06449afe92 remove this test. It is currently failing because we now emit the string 
on darwin with ".cstring" instead of ".section  __TEXT,__cstring".  They
are the same and the former is better.  Remove this because this is no longer
magic pixie dust in the frontend.

llvm-svn: 77055
 2009-07-25 07:31:51 +00:00
Dan Gohman
13aabe2ba4 Teach ScalarEvolution to make use of no-overflow flags when 
analyzing add recurrences.

llvm-svn: 77034
 2009-07-25 01:22:26 +00:00
Evan Cheng
12dd5c078f I've lost my mind. PR4572 has not been fixed. 
llvm-svn: 77031
 2009-07-25 01:11:46 +00:00
Evan Cheng
d615e606c4 Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00
Evan Cheng
bddff8fbe0 Remove a duplicated test. 
llvm-svn: 77020
 2009-07-25 00:24:40 +00:00
Evan Cheng
5faed6335e Forgot this test earlier. 
llvm-svn: 77007
 2009-07-24 22:42:45 +00:00
Evan Cheng
b8b61017e8 Fix these tests. 
llvm-svn: 77006
 2009-07-24 22:42:22 +00:00
Eli Friedman
11e86150c4 Fix assert assembling zero-argument constant GEP. 
There's still a strict-aliasing violation here, but I don't feel like 
dealing with that right now...

llvm-svn: 77005
 2009-07-24 21:56:17 +00:00
Eric Christopher
24a620ec3d Move insertps tests to sse41 combo test file, convert to filecheck 
format and add an extract/insert test.

llvm-svn: 76994
 2009-07-24 19:24:26 +00:00
Evan Cheng
bbac2397c5 Convert a test to FileCheck. 
llvm-svn: 76954
 2009-07-24 06:01:46 +00:00
Chris Lattner
09511ed243 Remove SectionKind::Small*. This was only used on mips, and is apparently 
a sad mistake that is regretted. :)

llvm-svn: 76935
 2009-07-24 03:11:51 +00:00
Richard Osborne
19591063fc Add tests for handling of globals and tls on the XCore. These currently fail 
but pass when run against r76652.

llvm-svn: 76923
 2009-07-24 00:38:20 +00:00
Dan Gohman
62c8b40b66 Remove the IA-64 backend. 
llvm-svn: 76920
 2009-07-24 00:30:09 +00:00
Evan Cheng
90f66e1c4e Thumb2 does not allow the use of "pc" register as part of the load / store address. 
llvm-svn: 76909
 2009-07-23 23:09:51 +00:00
Evan Cheng
f6b88eae82 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890
 2009-07-23 18:27:47 +00:00
Andreas Bolka
fa70ad653b FileCheck'ize and expand LDA testcases. 
llvm-svn: 76880
 2009-07-23 15:56:53 +00:00
Chris Lattner
4c55a88118 testcase for PR4590 
llvm-svn: 76868
 2009-07-23 06:07:59 +00:00
Chris Lattner
0426853d67 merge vector-casts-0.ll into vector-casts.ll 
llvm-svn: 76864
 2009-07-23 05:33:39 +00:00
Chris Lattner
c687344f0c Make some existing optimizations that would only trigger on scalars 
also apply to vectors.  This allows us to compile this:

#include <emmintrin.h>
__m128i a(__m128 a, __m128 b) { return a==a & b==b; }
__m128i b(__m128 a, __m128 b) { return a!=a | b!=b; }

to:

_a:
	cmpordps	%xmm1, %xmm0
	ret
_b:
	cmpunordps	%xmm1, %xmm0
	ret

with clang instead of to a ton of horrible code.

llvm-svn: 76863
 2009-07-23 05:32:17 +00:00
Chris Lattner
f4474da353 convert a test to filecheck format. This fixes an endemic problem 
with negative tests: this test wasn't checking what it thought it was
because it was grepping .bc, not .ll.

llvm-svn: 76861
 2009-07-23 05:27:48 +00:00
Chris Lattner
7061a4300d rename test 
llvm-svn: 76860
 2009-07-23 05:25:12 +00:00
Chris Lattner
7fd20e69f1 merge one more sse41 test into sse41.ll 
llvm-svn: 76853
 2009-07-23 04:49:39 +00:00
Chris Lattner
efe5b9aaf8 merge another sse41 test into sse41.ll 
llvm-svn: 76852
 2009-07-23 04:43:48 +00:00
Chris Lattner
c59ca858c8 merge sse41-pmovx.ll into sse41.ll 
llvm-svn: 76850
 2009-07-23 04:39:09 +00:00
Chris Lattner
313c95ea84 change a test to run in filecheck style. Rename it to be a general 
dumping ground of various SSE4.1 tests, since filecheck can reasonably
handle them all in one file.  Generalize it to check x86-64 stuff as
well since it has a different ABI (a convenient way to test both the 
reg and mem forms of these instructions).

llvm-svn: 76848
 2009-07-23 04:33:02 +00:00
Eric Christopher
c9299d5756 Support insertps via the intrinsic and add a couple of simple 
testcases to make sure it's being generated.

llvm-svn: 76843
 2009-07-23 02:22:41 +00:00
Eric Christopher
36eeebc1c4 Add test for pinsrd and pinsrb instructions. 
llvm-svn: 76840
 2009-07-23 01:58:04 +00:00
Devang Patel
6b2162686a Derive MDNode from MetadataBase instead of Constant. Emit MDNodes into METADATA_BLOCK in bitcode file. 
llvm-svn: 76834
 2009-07-23 01:07:34 +00:00
Dan Gohman
0a0d23a081 Revert r75663 (and r76805), as it is causing regressions on powerpc. 
llvm-svn: 76823
 2009-07-23 00:09:46 +00:00
Dan Gohman
840e7f252e x86 isel tweak: use lea (%reg,%reg) instead of lea (,%reg,2). 
llvm-svn: 76817
 2009-07-22 23:26:55 +00:00
Dan Gohman
001d777207 Rename the new unsigned and signed keywords to nuw and nsw, 
which stand for no-unsigned-wrap and no-signed-wrap.

llvm-svn: 76810
 2009-07-22 22:44:56 +00:00
Dan Gohman
f1103cf95b Add -march=ppc32 lines so that this test doesn't ever default to ppc64. 
llvm-svn: 76805
 2009-07-22 22:08:31 +00:00
Evan Cheng
4a77f28c47 Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
llvm-svn: 76803
 2009-07-22 22:03:29 +00:00
Dan Gohman
8b7a539e80 Make the grep line in this test more specific, to avoid 
unintended matches.

llvm-svn: 76802
 2009-07-22 22:02:42 +00:00
Evan Cheng
88dbc00ca7 Ignore undef uses. 
llvm-svn: 76799
 2009-07-22 21:51:42 +00:00
Devang Patel
b51f9d0246 Remove empty test. 
llvm-svn: 76763
 2009-07-22 18:09:11 +00:00
Devang Patel
5794cb80ad Introduce MetadataBase, a base class for MDString and MDNode. 
Derive MDString directly from MetadataBase. 
Introduce new bitcode block to hold metadata.

llvm-svn: 76759
 2009-07-22 17:43:22 +00:00
Duncan Sands
2a4535353f Revert commit 76707, it was breaking the llvm-gcc build 
on linux platforms.  The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html 

llvm-svn: 76733
 2009-07-22 10:35:05 +00:00
Chris Lattner
ced616dd50 set the ELF "small" flag on objects that end up in .rodata.cst4 consistently, 
updating a mips testcase to expect it.

llvm-svn: 76707
 2009-07-22 00:41:56 +00:00
Dan Gohman
190d29cb5c Replace the original ad-hoc code for determining whether (v pred w) implies 
(x pred y) with more thorough code that does more complete canonicalization
before resorting to range checks. This helps it find more cases where
the canonicalized expressions match.

llvm-svn: 76671
 2009-07-21 23:03:19 +00:00
Evan Cheng
e0f52b2bf3 Remove a big test case. 
llvm-svn: 76669
 2009-07-21 22:52:04 +00:00
Bob Wilson
2a2501eca4 Fix ocaml tests for 64-bit MacOS systems. LLVM is currently built 
as 32-bit code by default, and if gcc defaults to 64-bit code then ocamlc
requires a -cc "gcc -arch i386" option.  We were hardcoding -cc g++
and throwing away any other compiler options that were determined when
ocamlc was configured and built.

llvm-svn: 76658
 2009-07-21 21:56:46 +00:00
Evan Cheng
192fc19379 Do not select tSXTB / tSXTH in thumb2 mode. 
llvm-svn: 76600
 2009-07-21 18:15:26 +00:00
Chris Lattner
ed8c3ea053 convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin" 
llvm-svn: 76591
 2009-07-21 17:36:24 +00:00
Chris Lattner
788fa56eda add a testcase for the pic16 section handling stuff. 
llvm-svn: 76579
 2009-07-21 16:48:20 +00:00
Evan Cheng
c142755cec Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past. 
llvm-svn: 76558
 2009-07-21 09:15:00 +00:00
Chris Lattner
fab15a5571 remove a very large testcase for now. 
llvm-svn: 76537
 2009-07-21 06:28:36 +00:00
Evan Cheng
0cf19155ef Fix a dagga combiner bug: avoid creating illegal constant. 
Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or                                                                              
                              (srl (and x, (shl -1, c1)), (sub c1, c2))

llvm-svn: 76535
 2009-07-21 05:40:15 +00:00
Dan Gohman
f2c6e6a1bd Add a testcase for PR2831. 
llvm-svn: 76527
 2009-07-21 01:02:18 +00:00
Dan Gohman
7a836d6400 Add a testcase for PR4569, which is now fixed. 
llvm-svn: 76526
 2009-07-21 00:50:52 +00:00
Evan Cheng
949c2404a2 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
llvm-svn: 76520
 2009-07-21 00:31:12 +00:00
Evan Cheng
443ae1d494 Cross RC coalescing is now on by default. 
llvm-svn: 76519
 2009-07-21 00:22:59 +00:00
Dan Gohman
74a435e9f1 The upper argument of ConstantRange is exclusive, not inclusive. 
llvm-svn: 76492
 2009-07-20 22:34:18 +00:00
David Greene
1ac6d4ac0e Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes 
next.

llvm-svn: 76486
 2009-07-20 22:02:59 +00:00
Evan Cheng
919f5c5559 Forgot this test earlier. 
llvm-svn: 76485
 2009-07-20 21:46:42 +00:00
Dan Gohman
d2ad3e183b Assembly and Bitcode support for unsigned/signed overflow flags and 
exact sdiv flags.

llvm-svn: 76475
 2009-07-20 21:19:07 +00:00
Evan Cheng
2bac9b0d83 Use TII->findCommutedOpIndices to find the commute operands (rather than guessing). 
llvm-svn: 76472
 2009-07-20 21:16:08 +00:00
Kevin Enderby
f1c0daa6a7 Removed the DumpSymbolsandMacros and LoadSymbolsandMacros MCStreamer API as 
the parsing of the .dump and .load should be done in the assembly parser and
not have any need for an MCStreamer API.  Changed the code for now so these
just produce an error saying these specific directives are not yet implemented
since they are likely no longer used and may never need to be implemented.

llvm-svn: 76462
 2009-07-20 20:25:37 +00:00
Evan Cheng
0048e876c3 Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class. 
llvm-svn: 76458
 2009-07-20 19:47:55 +00:00
Dan Gohman
00b05492f1 Revert the addition of hasNoPointerOverflow to GEPOperator. 
Getelementptrs that are defined to wrap are virtually useless to
optimization, and getelementptrs that are undefined on any kind
of overflow are too restrictive -- it's difficult to ensure that
all intermediate addresses are within bounds. I'm going to take
a different approach.

Remove a few optimizations that depended on this flag.

llvm-svn: 76437
 2009-07-20 17:43:30 +00:00
Evan Cheng
e5d229f7ac xfail for now. 
llvm-svn: 76423
 2009-07-20 15:33:09 +00:00
Chris Lattner
eac40b1473 implement a new magic global "llvm.compiler.used" which is like llvm.used, but 
doesn't cause ".no_dead_strip" to be emitted on darwin.

llvm-svn: 76399
 2009-07-20 06:14:25 +00:00
Evan Cheng
7377d0cb7c Restore AsmWriterEmitter.cpp back to 74742. The recent changes broke Thumb. 
llvm-svn: 76398
 2009-07-20 06:10:07 +00:00
Daniel Dunbar
46389b3660 This test should be run with -m32. 
llvm-svn: 76382
 2009-07-19 22:44:03 +00:00
Jakob Stoklund Olesen
96f9a917c8 Fix http://llvm.org/bugs/show_bug.cgi?id=4583 
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.

llvm-svn: 76373
 2009-07-19 19:09:59 +00:00
Eli Friedman
e507c1afaa Canonicalize bitcasts between types like <1 x i64> and i64 to 
insertelement/extractelement.

I'm not entirely sure this is precisely what we want to do: should we 
prefer bitcast(insertelement) or insertelement(bitcast)?  Similarly. should we 
prefer extractelement(bitcast) or bitcast(extractelement)?

llvm-svn: 76345
 2009-07-18 23:06:53 +00:00
Eli Friedman
debc43cb11 Back out 76300; apparently the preference is to canonicalize the other 
way (bitcast -> insert/extractelement).

llvm-svn: 76325
 2009-07-18 19:04:16 +00:00
Eli Friedman
65a5fe312a Add combine: X sdiv (1 << Y) -> X udiv (1 << Y) when X doesn't have the 
sign bit set.

llvm-svn: 76304
 2009-07-18 09:53:21 +00:00
Eli Friedman
f1878fcda1 Canonicalize insert/extractelement from single-element vectors into 
bitcasts.

It would also be possible to canonicalize the other way; does anyone 
have a preference?

llvm-svn: 76300
 2009-07-18 09:07:47 +00:00
Eli Friedman
7b1597133d Fix simplifylibcalls memset recognition to work on 64-bit platforms 
where int is 32 bits.

llvm-svn: 76293
 2009-07-18 08:34:51 +00:00
Evan Cheng
a19ee1bb42 Catch more coalescing opportunities. 
llvm-svn: 76282
 2009-07-18 04:52:23 +00:00
Evan Cheng
84f06f0ee6 Enable cross register class coalescing. 
llvm-svn: 76281
 2009-07-18 02:10:10 +00:00
Evan Cheng
92fc255bb4 Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams. 
llvm-svn: 76258
 2009-07-17 22:42:51 +00:00
Daniel Dunbar
ab1316fbaf llvm-mc: Add -triple, and start fetching the target asm printer. 
llvm-svn: 76257
 2009-07-17 22:38:58 +00:00
Evan Cheng
67ccedff04 Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense. 
llvm-svn: 76248
 2009-07-17 22:13:25 +00:00
Chris Lattner
fb1ff2b993 rename test. 
llvm-svn: 76197
 2009-07-17 18:05:55 +00:00
Duncan Sands
c77e727d4f Testcase for PR4214. 
llvm-svn: 76174
 2009-07-17 11:44:20 +00:00
Eli Friedman
fde598545c Make promotion in operation legalization for SETCC work correctly. 
llvm-svn: 76153
 2009-07-17 05:16:04 +00:00
Anton Korobeynikov
dc39f4fff8 Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

llvm-svn: 76124
 2009-07-16 23:26:06 +00:00
Dale Johannesen
e08bda67c2 Assume an inline asm might be a call, so we get 
stack alignment right when it is.  This is not
ideal but conservatively correct.  Adjust a test
to compensate for changed stack offset value.
gcc.apple/asm-block-57.c

llvm-svn: 76120
 2009-07-16 22:34:45 +00:00
David Greene
a2c98dd402 Emit line numbers in asm comments when available. 
llvm-svn: 76117
 2009-07-16 22:24:20 +00:00
Jakob Stoklund Olesen
4a0d996780 Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands. 
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

llvm-svn: 76101
 2009-07-16 20:58:34 +00:00
Evan Cheng
981276bb16 Changed my mind. We now allow remat of instructions whose defs have subreg indices. 
llvm-svn: 76100
 2009-07-16 20:15:00 +00:00
Chris Lattner
aeeaf805c6 this should be xfailed on darwin. Darwin doesn't use the libstdc++ in the llvm-gcc distro, it uses the system version. 
llvm-svn: 76095
 2009-07-16 18:45:51 +00:00
Evan Cheng
39e5f6205a With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. 
llvm-svn: 76094
 2009-07-16 18:44:05 +00:00
Dan Gohman
50e65d8c93 Fill in some holes in ScalarEvolution's loop iteration condition 
analysis. This allows indvars to emit a simpler loop trip count
expression.

llvm-svn: 76085
 2009-07-16 17:34:36 +00:00
Anton Korobeynikov
0d58ad2528 Make xfail proper 
llvm-svn: 76065
 2009-07-16 14:53:47 +00:00
Anton Korobeynikov
3e8bb65ec8 Temporary disable 16 bit bswap 
llvm-svn: 76063
 2009-07-16 14:35:57 +00:00
Anton Korobeynikov
e11a89ba74 Add bswap patterns 
llvm-svn: 76061
 2009-07-16 14:34:52 +00:00
Anton Korobeynikov
94f250ff30 Fix logic inversion for RI-mode address selection 
llvm-svn: 76052
 2009-07-16 14:31:14 +00:00
Anton Korobeynikov
4bba61182a Unbreak the test 
llvm-svn: 76051
 2009-07-16 14:30:49 +00:00
Anton Korobeynikov
373515d99e Expand 32-bit bitconverts via memory 
llvm-svn: 76050
 2009-07-16 14:30:29 +00:00
Anton Korobeynikov
080bdae588 Fix incomin arg stack frame offset in case we need to generate stack frame 
llvm-svn: 76049
 2009-07-16 14:29:57 +00:00
Anton Korobeynikov
2e8f54d16d Revert the commit, it just hides the real bug 
llvm-svn: 76045
 2009-07-16 14:28:26 +00:00
Anton Korobeynikov
bbf0fe2a76 Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects 
llvm-svn: 76035
 2009-07-16 14:24:41 +00:00
Anton Korobeynikov
3e670f38f9 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems 
llvm-svn: 76011
 2009-07-16 14:18:17 +00:00
Anton Korobeynikov
b3af53a626 Implement 'large' PIC model 
llvm-svn: 76006
 2009-07-16 14:16:05 +00:00
Anton Korobeynikov
2889a28adb Implement shifts properly (hopefilly - finally!) 
llvm-svn: 76005
 2009-07-16 14:15:24 +00:00
Anton Korobeynikov
f48e88136e Properly handle divides. As a bonus - implement memory versions of them. 
llvm-svn: 76003
 2009-07-16 14:14:33 +00:00
Anton Korobeynikov
e6b7c15a63 32 bit shifts have only 12 bit displacements 
llvm-svn: 76000
 2009-07-16 14:13:24 +00:00
Anton Korobeynikov
6c1091e7f3 Consolidate reg-imm / reg-reg-imm address mode selection logic in one place. 
llvm-svn: 75990
 2009-07-16 14:10:17 +00:00
Anton Korobeynikov
9a1ad49207 Add support for 12 bit displacements 
llvm-svn: 75988
 2009-07-16 14:09:35 +00:00
Anton Korobeynikov
a809635fc8 Emit proper lowering of load from arg stack slot 
llvm-svn: 75986
 2009-07-16 14:08:42 +00:00
Anton Korobeynikov
9013a1ee39 Implement dynamic allocas 
llvm-svn: 75985
 2009-07-16 14:08:15 +00:00
Anton Korobeynikov
ee8ce5b760 Add jump tables 
llvm-svn: 75984
 2009-07-16 14:07:50 +00:00
Anton Korobeynikov
ab90a05ff3 Add rotates 
llvm-svn: 75981
 2009-07-16 14:06:49 +00:00
Anton Korobeynikov
ff5b07e994 Add patterns for integer negate 
llvm-svn: 75980
 2009-07-16 14:06:27 +00:00
Anton Korobeynikov
335aeecedc Provide proper patterns for and with imm instructions. Tune the tests accordingly. 
llvm-svn: 75979
 2009-07-16 14:06:00 +00:00
Anton Korobeynikov
49d065e9c9 Add 32 bit and reg-imm and disable invalid patterns for now 
llvm-svn: 75978
 2009-07-16 14:05:32 +00:00
Anton Korobeynikov
c9778b81c9 Add z9 and z10 target processors. Mark z10-only instructions as such. 
llvm-svn: 75977
 2009-07-16 14:05:00 +00:00
Anton Korobeynikov
1e1f1a789b Proper lower 'small' results 
llvm-svn: 75962
 2009-07-16 13:58:24 +00:00
Anton Korobeynikov
db9fb21b48 Completel forgot about unconditional branches 
llvm-svn: 75961
 2009-07-16 13:57:52 +00:00
Anton Korobeynikov
ce2b70586e Lower addresses of globals 
llvm-svn: 75960
 2009-07-16 13:57:27 +00:00
Anton Korobeynikov
9a57aa9c54 Test (incomplete) for easy muls 
llvm-svn: 75959
 2009-07-16 13:57:03 +00:00
Anton Korobeynikov
d984dc6c9d Provide "wide" muls and divs/rems 
llvm-svn: 75958
 2009-07-16 13:56:42 +00:00
Anton Korobeynikov
aad6f1c75a Tests for cmp / br_cc / select_cc 
llvm-svn: 75949
 2009-07-16 13:53:15 +00:00
Anton Korobeynikov
b4a6f3c467 Emit callee-saved regs spills / restores 
llvm-svn: 75943
 2009-07-16 13:51:12 +00:00
Anton Korobeynikov
4fcadd1a7d Some preliminary call lowering 
llvm-svn: 75941
 2009-07-16 13:50:21 +00:00
Anton Korobeynikov
f4257ba74e Prologue / epilogue emission 
llvm-svn: 75940
 2009-07-16 13:49:49 +00:00
Anton Korobeynikov
dd60515f11 Add simple frame index elimination 
llvm-svn: 75939
 2009-07-16 13:49:25 +00:00
Anton Korobeynikov
40a891deef Provide proper test :) 
llvm-svn: 75938
 2009-07-16 13:48:59 +00:00
Anton Korobeynikov
5e1fa67a23 Add address computation stuff 
llvm-svn: 75935
 2009-07-16 13:47:59 +00:00
Anton Korobeynikov
47c086cc6b Add mem-imm stores 
llvm-svn: 75933
 2009-07-16 13:47:14 +00:00