Jim Grosbach
0ae6bf8095
More ARM multiply instruction encoding information.
...
llvm-svn: 117108
2010-10-22 17:16:17 +00:00
Wesley Peck
488027efa3
Making the e_machine configurable by the target backend in ELFObjectWriter.
...
llvm-svn: 117099
2010-10-22 15:52:49 +00:00
Eric Christopher
58a6e62c08
Add some basic ret instruction support to arm fast-isel.
...
llvm-svn: 117085
2010-10-22 01:28:00 +00:00
Jim Grosbach
d86073aa9a
ARM binary encoding for some of the multiply instructions.
...
llvm-svn: 117080
2010-10-21 22:52:30 +00:00
Jim Grosbach
7c42142b71
ARM binary encodings for MVN variants.
...
llvm-svn: 117076
2010-10-21 22:19:32 +00:00
Jim Grosbach
cb41e97b5c
ARM Binary encoding information for BFC/BFI instructions.
...
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
Eric Christopher
59683c9d71
These don't need to be virtual.
...
llvm-svn: 117068
2010-10-21 21:47:51 +00:00
Owen Anderson
f84632744e
Move the encoding logic for Q registers into getMachineOpValue().
...
llvm-svn: 117060
2010-10-21 20:49:13 +00:00
Owen Anderson
ba2ac80921
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
llvm-svn: 117056
2010-10-21 20:21:49 +00:00
Eric Christopher
7ded7e88c8
Handle storing args to the stack for calls.
...
llvm-svn: 117055
2010-10-21 20:09:54 +00:00
Eric Christopher
b15029ea7e
More load/store refactoring, call reg+offset simplification from within
...
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
llvm-svn: 117051
2010-10-21 19:40:30 +00:00
Jim Grosbach
f35d3b2aa1
trailing whitespace
...
llvm-svn: 117050
2010-10-21 19:38:40 +00:00
Owen Anderson
51a6bc3b27
Add correct NEON encodings for vhadd and vrhadd.
...
llvm-svn: 117047
2010-10-21 18:55:04 +00:00
Owen Anderson
dce283c7db
Add correct encodings for NEON vaddw.s* and vaddw.u*.
...
llvm-svn: 117040
2010-10-21 18:20:25 +00:00
Owen Anderson
7d90c72edf
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
...
llvm-svn: 117039
2010-10-21 18:09:17 +00:00
Duncan Sands
b458f1dc85
The return value of this call is not used, so no point
...
in assigning it to a variable (gcc-4.6 warning).
llvm-svn: 117024
2010-10-21 16:06:28 +00:00
Andrew Trick
4a3b819c1f
putback r116983 and fix simple-fp-encoding.ll tests
...
llvm-svn: 116992
2010-10-21 03:40:16 +00:00
Owen Anderson
7da515c665
Revert r116983, which is breaking all the buildbots.
...
llvm-svn: 116987
2010-10-21 03:11:16 +00:00
Evan Cheng
0b9eaaf45d
Add missing scheduling itineraries for transfers between core registers and VFP registers.
...
llvm-svn: 116983
2010-10-21 01:12:00 +00:00
Owen Anderson
a685f8e90a
Implement correct encodings for NEON vadd, both integer and floating point.
...
llvm-svn: 116981
2010-10-21 00:48:00 +00:00
Eric Christopher
7989939d87
Custom lower f64 args passed in integer registers.
...
llvm-svn: 116977
2010-10-21 00:01:47 +00:00
Bill Wendling
c7ef66fcf2
Add encoding for moving a value between two ARM core registers and a doublework
...
extension register.
llvm-svn: 116970
2010-10-20 23:37:40 +00:00
Bill Wendling
0f96ff63b3
Add encodings for movement between ARM core registers and single-precision
...
registers.
llvm-svn: 116961
2010-10-20 22:44:54 +00:00
Dale Johannesen
a324c8c6bd
Fix crash introduced in 116852. 8573915.
...
llvm-svn: 116955
2010-10-20 22:03:37 +00:00
Chandler Carruth
55850cad48
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
...
#includes in the process.
llvm-svn: 116919
2010-10-20 08:27:02 +00:00
Eric Christopher
78c7e84ce5
Fix a TODO by removing some unnecesary copies.
...
llvm-svn: 116915
2010-10-20 08:02:24 +00:00
Jim Grosbach
ebb4bc2c05
Fix backwards conditional.
...
llvm-svn: 116897
2010-10-20 01:10:01 +00:00
Jim Grosbach
c77e19ac99
Add dynamic realignment when rematerializing the base register.
...
llvm-svn: 116886
2010-10-20 00:02:50 +00:00
Jim Grosbach
5f33ecfc98
Nuke a commented out bit that got missed a while back.
...
llvm-svn: 116883
2010-10-19 23:48:47 +00:00
Jim Grosbach
a8c0be5343
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
...
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
llvm-svn: 116879
2010-10-19 23:27:08 +00:00
Jim Grosbach
d7916d7468
Update comments to remove obsolete references.
...
llvm-svn: 116863
2010-10-19 21:34:47 +00:00
Dale Johannesen
ee87cbe4e9
Enable using vdup for vector constants which are splat of
...
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
llvm-svn: 116852
2010-10-19 20:00:17 +00:00
Evan Cheng
1c8dafd12a
Re-enable register pressure aware machine licm with fixes. Hoist() may have
...
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
llvm-svn: 116845
2010-10-19 18:58:51 +00:00
Daniel Dunbar
6ff550c84d
Revert r116781 "- Add a hook for target to determine whether an instruction def
...
is", which breaks some nightly tests.
llvm-svn: 116816
2010-10-19 17:14:24 +00:00
Evan Cheng
9c3f6f486e
- Add a hook for target to determine whether an instruction def is
...
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
llvm-svn: 116781
2010-10-19 00:55:07 +00:00
Bob Wilson
c3fb4427f4
Support alignment for NEON vld-lane and vst-lane instructions.
...
llvm-svn: 116776
2010-10-19 00:16:32 +00:00
Jim Grosbach
10fd33ecfc
ARM encoding information for [SU]SAT* instructions.
...
llvm-svn: 116768
2010-10-18 23:35:38 +00:00
Eric Christopher
5850afe5f2
Revert r116220 - thus turning arm fast isel back on by default.
...
llvm-svn: 116762
2010-10-18 22:53:53 +00:00
Bill Wendling
3b3d9aaa86
Don't recompute MachineRegisterInfo in the Optimize* method.
...
llvm-svn: 116750
2010-10-18 21:22:31 +00:00
Jim Grosbach
ffb06eda57
For Thumb2, try to use frame pointer references for stack slots even when a
...
base register is available. rdar://8525298
llvm-svn: 116729
2010-10-18 18:39:46 +00:00
Jim Grosbach
3e41568604
ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
...
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625
llvm-svn: 116714
2010-10-18 16:48:59 +00:00
Jim Grosbach
f93e92a4c1
Grammar tweak.
...
llvm-svn: 116712
2010-10-18 16:38:50 +00:00
Eric Christopher
e453bd6697
Remove the check for invalid calling conventions. Testing shows that they're
...
working just fine.
llvm-svn: 116698
2010-10-18 06:49:12 +00:00
Eric Christopher
6287738105
Lift arg promotion from the X86 backend. This should be unified at some point.
...
llvm-svn: 116694
2010-10-18 02:17:53 +00:00
Eric Christopher
79c2206640
Now that we handle all allocas via a non-SP reg offset remove all of the
...
special case handling for ARM::SP.
llvm-svn: 116688
2010-10-17 11:08:44 +00:00
Eric Christopher
d99f79f92b
Allow more load types to be materialized through the allocas.
...
llvm-svn: 116683
2010-10-17 06:07:26 +00:00
Eric Christopher
5fcaab5d0e
Optimize GEP off of intermediate allocas.
...
llvm-svn: 116681
2010-10-17 01:51:42 +00:00
Eric Christopher
20bbcbeceb
Fix comment.
...
llvm-svn: 116680
2010-10-17 01:42:53 +00:00
Eric Christopher
d9b4b47b9a
Turn on AddOperator folding in GEP.
...
llvm-svn: 116679
2010-10-17 01:41:46 +00:00
Eric Christopher
490f82bc32
Use the i12 immediate versions of the load instructions - they're handled
...
more in the post-passes.
llvm-svn: 116678
2010-10-17 01:40:27 +00:00
Rafael Espindola
be5c52d2dc
Add a MCObjectFormat class so that code common to all targets that use a
...
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
Eric Christopher
98c6ce755a
Fix some funky formatting that got through.
...
llvm-svn: 116653
2010-10-16 01:10:35 +00:00
Bill Wendling
8e4ceb45f2
ARMCodeEmitter::emitMiscInstruction is dead. Long live
...
ARMCodeEmitter::emitMiscInstruction!
llvm-svn: 116644
2010-10-15 23:35:12 +00:00
Eric Christopher
69eaf30a42
Make sure offset is 0 for load/store register to the stack call.
...
llvm-svn: 116640
2010-10-15 23:07:10 +00:00
Eric Christopher
c6e4aaec0a
Formatting.
...
llvm-svn: 116635
2010-10-15 22:49:28 +00:00
Eric Christopher
7f8c3dff07
Fix else if -> if in store machinery.
...
llvm-svn: 116628
2010-10-15 22:32:37 +00:00
Bill Wendling
64d2bf006c
Reformatting. No functionalogicality changes.
...
llvm-svn: 116625
2010-10-15 21:50:45 +00:00
Eric Christopher
a875589580
Refactor ARM fast-isel reg + offset to be a base + offset.
...
llvm-svn: 116622
2010-10-15 21:32:12 +00:00
Jim Grosbach
5d7a5f8d33
Encoding information for the various ARM saturating add/sub instructions.
...
llvm-svn: 116612
2010-10-15 19:49:46 +00:00
Jim Grosbach
785858b2ba
ARM binary encoding information for RSB and RSC instructions.
...
llvm-svn: 116604
2010-10-15 18:42:41 +00:00
Jim Grosbach
440b0e6b34
Don't mark argument value stores as immutable, as otherwise the post-RA
...
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer
llvm-svn: 116602
2010-10-15 18:34:47 +00:00
Bob Wilson
3b63270ed3
Use simple RegState::Define flag instead of getDefRegState(true).
...
llvm-svn: 116601
2010-10-15 18:25:59 +00:00
Eric Christopher
b287ab82d7
Expand GEP handling for constant offsets.
...
llvm-svn: 116594
2010-10-15 18:02:07 +00:00
Jim Grosbach
cb52aee60e
When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
...
an explicit def. Make sure to capture that properly. rdar://8556556
llvm-svn: 116591
2010-10-15 17:35:17 +00:00
Jim Grosbach
67f94c42d8
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
Bob Wilson
6b6b53ad6f
Remove unused ARMISD::AND selection DAG node.
...
llvm-svn: 116566
2010-10-15 04:34:40 +00:00
Bob Wilson
fcc42f2f3a
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
Jim Grosbach
b01bcbd047
Encoding info for extension instructions.
...
llvm-svn: 116560
2010-10-15 02:29:58 +00:00
Jim Grosbach
6da1b52d7b
Add missing Rd encoding for MOVs instruction.
...
llvm-svn: 116537
2010-10-14 23:28:31 +00:00
Jim Grosbach
804505c7d4
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
...
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
Jim Grosbach
29dc23398f
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
Jim Grosbach
73c78f8790
MOVi16 and MOVT ARM mode encodings.
...
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
Jim Grosbach
6d5cb39757
Simplify encoding information and add 'dst' operand info for TAILJMP.
...
llvm-svn: 116488
2010-10-14 17:24:28 +00:00
Oscar Fuentes
1f9f1cc125
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
...
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
llvm-svn: 116480
2010-10-14 15:54:46 +00:00
Eric Christopher
9060ac1be3
Handle more complex GEP based loads and add a few TODOs to deal with
...
GEP + alloca.
llvm-svn: 116474
2010-10-14 09:29:41 +00:00
Bill Wendling
2c335d364c
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
...
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
Bill Wendling
33a2ecd5e4
Add encoding for 'fmstat'.
...
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
Bill Wendling
cd41f22ec1
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
Jim Grosbach
684289bc3c
Regenerate. No functional change, just cleanup.
...
llvm-svn: 116459
2010-10-14 00:15:18 +00:00
Jim Grosbach
151502662e
Detabify and clean up 80 column violations.
...
llvm-svn: 116454
2010-10-13 23:47:11 +00:00
Jim Grosbach
506b966b9d
A few 80 column fixes.
...
llvm-svn: 116451
2010-10-13 23:34:31 +00:00
Jim Grosbach
2e8a589fb2
trailing whitespace
...
llvm-svn: 116450
2010-10-13 23:12:26 +00:00
Jim Grosbach
41cd0dd4ba
Add a FIXME.
...
llvm-svn: 116449
2010-10-13 22:55:33 +00:00
Jim Grosbach
4c80dbda49
Add operand encoding bits for SMC and SVC in ARM mode.
...
llvm-svn: 116447
2010-10-13 22:38:23 +00:00
Jim Grosbach
66822f70b8
More encoding cleanup. Also add register Rd operands for indirect branches.
...
llvm-svn: 116444
2010-10-13 22:09:34 +00:00
Jim Grosbach
630efeb050
Simplify some ARM encoding information.
...
llvm-svn: 116440
2010-10-13 21:48:54 +00:00
Eric Christopher
19be5bd87c
Update comment.
...
llvm-svn: 116438
2010-10-13 21:41:51 +00:00
Jim Grosbach
f1d59d0fd5
Add a FIXME. The ADR instruction is a bit odd.
...
llvm-svn: 116437
2010-10-13 21:32:30 +00:00
Jim Grosbach
1699d40f80
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
Bill Wendling
bf63d6eb63
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
Jim Grosbach
3a4bfe4573
Add a FIXME.
...
llvm-svn: 116428
2010-10-13 20:38:04 +00:00
Jim Grosbach
d079fee8b1
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
...
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
llvm-svn: 116427
2010-10-13 20:30:55 +00:00
Jim Grosbach
8f0bea85bf
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
Jim Grosbach
79156dadf2
Fix encoding for compares. No Rd register.
...
llvm-svn: 116414
2010-10-13 18:05:25 +00:00
Jim Grosbach
9c4a598ef2
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
Eric Christopher
f7ab2cd3df
Start handling more global variables.
...
llvm-svn: 116401
2010-10-13 09:11:46 +00:00
Evan Cheng
d07bee932d
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
...
llvm-svn: 116389
2010-10-13 01:54:21 +00:00
Bill Wendling
6d8a23c978
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
Bill Wendling
ea062d454d
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
Jim Grosbach
3fe0337063
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
Bill Wendling
e6c2fdebbd
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
Bill Wendling
fddde4cc72
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
Jim Grosbach
79cebf409d
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
Bill Wendling
47155cfddd
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
Bill Wendling
185b548b07
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
Jim Grosbach
de78ccb013
Move the ARM so_imm encoding into a custom operand encoder and remove the
...
explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
Bill Wendling
d1f06024ce
Refactor some of the encoding logic into a base class. This keeps us from having
...
to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
llvm-svn: 116362
2010-10-12 23:06:54 +00:00
Jim Grosbach
f4cf5bef46
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
...
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
Bill Wendling
cd3cb8da45
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
Bill Wendling
33a26354c1
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
Bill Wendling
79d57782ad
Split out the "size" field from the encoding. The newer documentation has it as
...
a separate bit in the coding.
llvm-svn: 116347
2010-10-12 22:03:19 +00:00
Eric Christopher
af5b22e150
Fix thinko in arm fast isel alloca rewrite.
...
llvm-svn: 116339
2010-10-12 21:23:43 +00:00
Jim Grosbach
58ee6f3972
Encoding for ARM-mode VADD.F32 instruction.
...
llvm-svn: 116338
2010-10-12 21:22:40 +00:00
Jim Grosbach
a0f673b561
Add MOVi ARM encoding.
...
llvm-svn: 116321
2010-10-12 18:09:12 +00:00
Jim Grosbach
dbf116be66
Nuke unused wrapper function.
...
llvm-svn: 116318
2010-10-12 17:53:25 +00:00
Jim Grosbach
10d9bbe0ca
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
Bob Wilson
bbb91c6a1c
PR8359: The ARM backend may end up allocating registers D16 to D31 when
...
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
Eric Christopher
0763cc04c5
Rework alloca handling so that we can load or store from casted
...
address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
Eric Christopher
8789aa8799
Handle a wider arrangement of loads.
...
llvm-svn: 116284
2010-10-12 00:43:21 +00:00
Evan Cheng
6aac1548ab
More ARM scheduling itinerary fixes.
...
llvm-svn: 116266
2010-10-11 23:41:41 +00:00
Jim Grosbach
29ef87e765
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
Jason W Kim
59375bae75
Second set of ARM/MC/ELF changes.
...
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
Evan Cheng
77ba7b098a
Proper VST scheduling itineraries.
...
llvm-svn: 116251
2010-10-11 22:03:18 +00:00
Eric Christopher
e1574aa60a
Use a sane mechanism for that assert.
...
llvm-svn: 116249
2010-10-11 22:01:22 +00:00
Eric Christopher
926a41a84b
We're not going to handle dynamic allocas anywhere else.
...
llvm-svn: 116240
2010-10-11 21:37:35 +00:00
Eric Christopher
cac7b248c7
Make sure that the call stack adjustments have default operands. Also
...
leave custom lowerings for later.
Fixes some nightly tests.
llvm-svn: 116232
2010-10-11 21:20:02 +00:00
Eric Christopher
fa961e31b1
Found a bug turning this on by default. Disable again for now.
...
llvm-svn: 116220
2010-10-11 20:26:21 +00:00
Eric Christopher
ff35a1f090
Fix help text.
...
llvm-svn: 116218
2010-10-11 20:15:02 +00:00
Eric Christopher
b1a93706f7
Change flag from Enable to Disable since we're enabled by default.
...
Also don't use fast-isel on non-darwin since it's untested.
llvm-svn: 116217
2010-10-11 20:05:22 +00:00
Jim Grosbach
a697e32f36
More binary encoding stuff, taking advantage of the new "by name" operand
...
matching in tblgen to do the predicate operand.
llvm-svn: 116213
2010-10-11 18:51:51 +00:00
Eric Christopher
52c102fef0
Turn on arm fast isel by default.
...
llvm-svn: 116212
2010-10-11 18:48:18 +00:00
Francois Pichet
80ec466cf5
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
...
llvm-svn: 116201
2010-10-11 11:36:19 +00:00
Eric Christopher
019eeb9c55
Copy and pasteo.
...
llvm-svn: 116198
2010-10-11 08:40:05 +00:00
Eric Christopher
a412d25090
Whitespace cleanup in ARM fast isel.
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llvm-svn: 116197
2010-10-11 08:38:55 +00:00
Eric Christopher
c100a052eb
Add srem libcall support to ARM fast isel.
...
llvm-svn: 116196
2010-10-11 08:37:26 +00:00
Eric Christopher
af5baa8a0f
Add i8 sdiv support for ARM fast isel.
...
llvm-svn: 116195
2010-10-11 08:31:54 +00:00
Eric Christopher
6f65f8a4d3
Implement select handling for ARM fast-isel.
...
llvm-svn: 116194
2010-10-11 08:27:59 +00:00
Evan Cheng
8c17a06411
Add VLD4 scheduling itineraries.
...
llvm-svn: 116143
2010-10-09 04:07:58 +00:00
Evan Cheng
df7f5672ee
Finish vld3 and vld4.
...
llvm-svn: 116140
2010-10-09 01:45:34 +00:00
Evan Cheng
bf6307d869
Complete vld2 instruction itineries.
...
llvm-svn: 116136
2010-10-09 01:26:12 +00:00
Evan Cheng
c0933d5ec1
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
...
llvm-svn: 116135
2010-10-09 01:15:04 +00:00
Evan Cheng
15fc769cf2
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
Bill Wendling
ba58fb0f42
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
Eric Christopher
a1d180e00e
Fix the store part of this as well. Fixes smg2000.
...
llvm-svn: 116123
2010-10-08 23:52:16 +00:00
Jim Grosbach
3075d28c15
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
Jim Grosbach
85b45fcc52
Reapply 116059, this time without the fatfingered pasto at the top.
...
''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
Jim Grosbach
674fa65e33
Reverting 116059. Bots are unhappy with it.
...
llvm-svn: 116064
2010-10-08 17:28:40 +00:00
Jim Grosbach
8d4bb23650
'const'ify getMachineOpValue() and associated helpers.
...
llvm-svn: 116059
2010-10-08 16:52:44 +00:00
Bob Wilson
8689a52c10
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
Eric Christopher
45a5ff5ca3
Move to thumb2 loads, fixes a problem with incoming registers
...
as thumb1.
Fixes lencod.
llvm-svn: 116027
2010-10-08 01:13:17 +00:00
Jim Grosbach
1214818a3e
Enable binary encoding of some simple instructions.
...
llvm-svn: 116022
2010-10-08 00:39:21 +00:00
Jim Grosbach
df2ff926a6
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
Evan Cheng
7fa1e3a474
Code refactoring.
...
llvm-svn: 116002
2010-10-07 23:12:15 +00:00
Jim Grosbach
e949170bad
Trivial MC code emitter shell. No instruction forms actually handled yet.
...
llvm-svn: 115993
2010-10-07 22:12:50 +00:00
Jim Grosbach
ec0a25f2b1
Include the auto-generated bits for machine encoding.
...
llvm-svn: 115987
2010-10-07 21:57:55 +00:00
Eric Christopher
183b18d430
Remember to promote load/store types for stack to register size.
...
llvm-svn: 115984
2010-10-07 21:40:18 +00:00
Jim Grosbach
671713cc62
ARM instruction don't have instruction prefixes, so remove the helper functions
...
for them from the MCCodeEmitter.
llvm-svn: 115975
2010-10-07 20:41:30 +00:00
Eric Christopher
3a068c4252
Use the correct register class for load instructions - fixes
...
compilation of MultiSource/Benchmarks/Bullet.
llvm-svn: 115907
2010-10-07 05:50:44 +00:00
Eric Christopher
b3e9588644
Use the correct register class here.
...
llvm-svn: 115906
2010-10-07 05:39:19 +00:00
Eric Christopher
67ca7a8fe3
Use the thumb2 conditional move instruction.
...
llvm-svn: 115905
2010-10-07 05:31:49 +00:00
Eric Christopher
8b8bce9a5b
Remove in-progress assertion, add TODO.
...
llvm-svn: 115904
2010-10-07 05:14:08 +00:00
Evan Cheng
1ce29574c2
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
...
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
Jim Grosbach
c0a61c0796
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
Jim Grosbach
1e2566c20d
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
Jim Grosbach
f2c54c9cf3
remove trailing whitespace
...
llvm-svn: 115860
2010-10-06 22:46:47 +00:00
Jason W Kim
de3044dcd1
First in a sequence of ARM/MC/*ELF* specific work.
...
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
Jim Grosbach
de2bd8cd3f
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
Jim Grosbach
4c7da8acbc
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
Jim Grosbach
e8a4fef4ea
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
...
"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
Jim Grosbach
e1e07b6bf1
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
...
pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
Jim Grosbach
54490de165
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
Jim Grosbach
dd7ee2836f
target operand flag values aren't a bitmask
...
llvm-svn: 115798
2010-10-06 16:51:55 +00:00
Evan Cheng
6fbb6dea7c
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
Chris Lattner
0b644ced02
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
Eric Christopher
9096fe41cb
Comment out fastisel debugging message.
...
llvm-svn: 115717
2010-10-05 23:50:58 +00:00
Eric Christopher
58254f68df
Random cleanup and make the intermediate register in fptosi a
...
32-bit fp reg, not 64-bit.
Fixes SingleSource.
llvm-svn: 115711
2010-10-05 23:13:24 +00:00
Jim Grosbach
7c112a9c65
Increase the number of bits used internally by the ARM target to represent the
...
addressing mode from four to five.
llvm-svn: 115645
2010-10-05 18:14:55 +00:00
Michael J. Spencer
d26ae30ed9
fix MSVC 2010 build.
...
llvm-svn: 115594
2010-10-05 06:00:43 +00:00
Michael J. Spencer
12a13def14
Cleanup Whitespace.
...
llvm-svn: 115593
2010-10-05 06:00:33 +00:00
Rafael Espindola
49d508fd19
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
...
so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
Evan Cheng
e8eec016c8
Major changes to Cortex-A9 itinerary.
...
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
llvm-svn: 115457
2010-10-03 02:03:59 +00:00
Eric Christopher
9e303eeb6f
Start on lowering global addresses.
...
llvm-svn: 115390
2010-10-02 00:32:44 +00:00
Jim Grosbach
a158e3e6c1
PrintSpecial() can go away now.
...
llvm-svn: 115376
2010-10-01 23:27:48 +00:00
Eric Christopher
c1f6f9a730
Stub out constant GV handling, fixes C++ eh tests.
...
llvm-svn: 115375
2010-10-01 23:24:42 +00:00
Jim Grosbach
619f1c1cc5
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
Jim Grosbach
8440cebbe9
Nuke a bunch of no-longer-needed comment-only asm strings.
...
llvm-svn: 115370
2010-10-01 23:09:33 +00:00
Evan Cheng
b068d1483a
Fix r115332: correctly model AGU / NEON mux.
...
llvm-svn: 115365
2010-10-01 22:52:29 +00:00
Owen Anderson
95581657a4
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
...
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
llvm-svn: 115364
2010-10-01 22:45:50 +00:00
Jim Grosbach
2143c9d321
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
Evan Cheng
0da8dff3c7
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
...
llvm-svn: 115354
2010-10-01 21:48:06 +00:00
Evan Cheng
cf5ed3cd53
Add operand cycles for vldr / vstr.
...
llvm-svn: 115353
2010-10-01 21:40:30 +00:00
Eric Christopher
669452e47f
Direct calls only for arm fast isel for now.
...
llvm-svn: 115350
2010-10-01 21:33:12 +00:00
Evan Cheng
fc1aee5b3c
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
...
llvm-svn: 115344
2010-10-01 20:50:58 +00:00
Eric Christopher
7daf669802
Fix thinko on store instructions. Fixes test_indvars failure.
...
llvm-svn: 115342
2010-10-01 20:46:04 +00:00
Owen Anderson
e93e24ee5d
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
...
llvm-svn: 115341
2010-10-01 20:33:47 +00:00
Owen Anderson
d6aa3da08e
Provide an option to restore old-style if-conversion heuristics for Thumb2.
...
llvm-svn: 115339
2010-10-01 20:28:06 +00:00
Evan Cheng
c7c6c2d04d
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
...
llvm-svn: 115332
2010-10-01 19:41:46 +00:00
Jim Grosbach
1a837b8495
grammar
...
llvm-svn: 115314
2010-10-01 14:57:48 +00:00
Eric Christopher
48606deb11
Implement double return values in calls. Fixes
...
SingleSource/Regression/C/casts.c.
llvm-svn: 115246
2010-10-01 00:00:11 +00:00
Owen Anderson
918c558636
Temporarily add a flag to make it easier to compare the new-style ARM if
...
conversion heuristics to the old-style ones.
llvm-svn: 115239
2010-09-30 23:48:38 +00:00