RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
Code Issues Projects Releases Wiki Activity
78,901 Commits 4 Branches 5 Tags 704 MiB
f9c7f9e3f3
Commit Graph

78901 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Rafael Espindola
f9c7f9e3f3 Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059
 2011-12-21 17:00:36 +00:00
Rafael Espindola
2334fc676a Add const. 
llvm-svn: 147054
 2011-12-21 14:48:04 +00:00
Rafael Espindola
318dc6e7f4 Small refactoring so that RelocNeedsGOT can stay in the target independent 
side when the target specific bits are moved to the Target directory.

llvm-svn: 147053
 2011-12-21 14:26:29 +00:00
Manuel Klimek
9f612635f4 Removes unused field TheError from LLLexer. 
llvm-svn: 147049
 2011-12-21 10:02:45 +00:00
Craig Topper
496932a88a Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. 
llvm-svn: 147046
 2011-12-21 08:06:52 +00:00
Craig Topper
e2e670bee5 Fix typo in a couple comments 
llvm-svn: 147045
 2011-12-21 06:30:53 +00:00
Nick Lewycky
98758f0c39 A call to a function marked 'noinline' is not an inline candidate. The sole 
call site of an intrinsic is also not an inline candidate. While here, make it
more obvious that this code ignores all intrinsics. Noticed by inspection!

llvm-svn: 147037
 2011-12-21 06:06:30 +00:00
Nick Lewycky
9adbd36737 Make some intrinsics safe to speculatively execute. 
llvm-svn: 147036
 2011-12-21 05:52:02 +00:00
Evan Cheng
fb22f64814 Fix a couple of copy-n-paste bugs. Noticed by George Russell. 
llvm-svn: 147032
 2011-12-21 03:04:10 +00:00
Jim Grosbach
2c2140a128 ARM assembly parsing allows constant expressions for lane indices. 
llvm-svn: 147028
 2011-12-21 01:19:23 +00:00
Eric Christopher
288c5842b8 Regenerate. 
llvm-svn: 147027
 2011-12-21 00:52:44 +00:00
Jim Grosbach
6bd1044b03 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Akira Hatanaka
4ab17eaca0 Fix bug in zero-store peephole pattern reported in pr11615. 
The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024
 2011-12-21 00:31:10 +00:00
Akira Hatanaka
0af792d12b Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.

llvm-svn: 147022
 2011-12-21 00:20:27 +00:00
Akira Hatanaka
6454b0ffc1 Expand 64-bit CTPOP and CTTZ. 
llvm-svn: 147021
 2011-12-21 00:14:05 +00:00
Akira Hatanaka
0cc0498ea1 Expand 64-bit atomic load and store. 
llvm-svn: 147019
 2011-12-21 00:02:58 +00:00
Akira Hatanaka
fb94688c7a Test case for r147017. 
llvm-svn: 147018
 2011-12-20 23:58:36 +00:00
Akira Hatanaka
2d293d2f4c Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
 2011-12-20 23:56:43 +00:00
Akira Hatanaka
fa96454cb4 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015
 2011-12-20 23:47:44 +00:00
Akira Hatanaka
6f31d220e7 64-bit uint-fp conversion nodes are expanded. 
llvm-svn: 147014
 2011-12-20 23:40:56 +00:00
Akira Hatanaka
02fe8adb97 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
llvm-svn: 147013
 2011-12-20 23:35:46 +00:00
Akira Hatanaka
507cdacdde Set the correct stack pointer register that should be saved or restored. 
llvm-svn: 147012
 2011-12-20 23:28:36 +00:00
Jim Grosbach
0768f2c420 Enable and fix a test. 
llvm-svn: 147011
 2011-12-20 23:20:00 +00:00
Chris Lattner
4ed5f7791d Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on 
the build bot in some cases.  The basic issue happens when a source module contains
both a "%foo" type and a "%foo.42" type.  It will see the later one, check to see if
the destination module contains a "%foo" type, and it will return true... because
both the source and destination modules are in the same LLVMContext.  We don't want
to map source types to other source types, so don't do the remapping if the mapped
type came from the source module.

Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is 
pretty great that way.

llvm-svn: 147010
 2011-12-20 23:14:57 +00:00
Jim Grosbach
7baaa0fc64 ARM .req register name aliases are case insensitive, just like regnames. 
llvm-svn: 147009
 2011-12-20 23:11:00 +00:00
Akira Hatanaka
2e4f1786b1 Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008
 2011-12-20 23:10:57 +00:00
Akira Hatanaka
8e3e6b14c8 Fix indentation. 
llvm-svn: 147007
 2011-12-20 22:58:01 +00:00
Akira Hatanaka
f728a1b2c5 64-bit data directive. 
llvm-svn: 147005
 2011-12-20 22:52:19 +00:00
Akira Hatanaka
ad193d95ae 32-to-64-bit sext_inreg pattern. 
llvm-svn: 147004
 2011-12-20 22:40:40 +00:00
Akira Hatanaka
13f23f5895 Add 64-bit extload patterns. 
llvm-svn: 147003
 2011-12-20 22:36:08 +00:00
Akira Hatanaka
ed1a29d5c2 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.

llvm-svn: 147001
 2011-12-20 22:33:53 +00:00
Jim Grosbach
ff31b81fe2 Move comment to appropriate place. 
llvm-svn: 147000
 2011-12-20 22:26:38 +00:00
Akira Hatanaka
8728f4ed69 Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999
 2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
2b24e1eac4 Heed spill slot alignment on ARM. 
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

llvm-svn: 146997
 2011-12-20 22:15:04 +00:00
Akira Hatanaka
1af9c41014 Revert part of r146995 that was accidentally commmitted. 
llvm-svn: 146996
 2011-12-20 22:09:36 +00:00
Akira Hatanaka
9c5e4d3b90 32-to-64-bit sign extension pattern. 
llvm-svn: 146995
 2011-12-20 22:06:20 +00:00
Akira Hatanaka
dba6358adc Add a pattern for matching zero-store with 64-bit address. The pattern is enabled 
only when the target ABI is N64. 

llvm-svn: 146992
 2011-12-20 21:50:49 +00:00
Jim Grosbach
8978194025 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Lang Hames
843255f890 Fix assert condition. 
llvm-svn: 146987
 2011-12-20 20:23:40 +00:00
Jakub Staszak
6f3beda2b4 Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 
llvm-svn: 146986
 2011-12-20 20:03:10 +00:00
Jim Grosbach
3f48367a1b ARM enable a few more tests. 
llvm-svn: 146985
 2011-12-20 20:03:00 +00:00
Devang Patel
a57e0b8f49 Add support to add named metadata operand. 
Patch by Andrew Wilkins!

llvm-svn: 146984
 2011-12-20 19:29:36 +00:00
Jim Grosbach
8156a5dcee ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Evan Cheng
46b085721a ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
llvm-svn: 146981
 2011-12-20 18:26:50 +00:00
Jason W Kim
139dd49440 First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

llvm-svn: 146977
 2011-12-20 17:38:12 +00:00
Elena Demikhovsky
b37883fe87 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]

llvm-svn: 146975
 2011-12-20 13:34:28 +00:00
Chandler Carruth
7564e8371a Begin teaching the X86 target how to efficiently codegen patterns that 
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

llvm-svn: 146974
 2011-12-20 11:19:37 +00:00
Manuel Klimek
94bfd4f3fc Fixes a potential compilation error. 
Pulling the template implementation into the header to guarantee
that it's visible to all possible instantiations.

llvm-svn: 146973
 2011-12-20 11:04:23 +00:00
Manuel Klimek
9661304f32 Pulls the implementation of skip() into JSONParser. 
This is the first step towards migrating more of the parser
implementation into the parser class.

llvm-svn: 146971
 2011-12-20 10:42:52 +00:00
Manuel Klimek
8c643f1ae2 Fixing option for JSON benchmark broken since the change to size_t. 
llvm-svn: 146970
 2011-12-20 10:34:29 +00:00