Jim Grosbach
7b62c2f71d
ARM assmebler parsing for two-operand VMUL instructions.
...
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
llvm-svn: 145842
2011-12-05 19:55:46 +00:00
Bob Wilson
f054e82281
Fix 80-column issues.
...
llvm-svn: 145783
2011-12-04 00:52:23 +00:00
Anton Korobeynikov
e2277de6a7
Emit the ctors in the proper order on ARM/EABI.
...
Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
Chad Rosier
d1968c9ed6
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
Jim Grosbach
fb734dff3c
ARM NEON VEXT aliases for data type suffices.
...
llvm-svn: 145726
2011-12-02 23:34:39 +00:00
Jim Grosbach
b15f862d86
ARM VEXT tighten up operand classes a bit.
...
llvm-svn: 145722
2011-12-02 22:57:57 +00:00
Jim Grosbach
3b245f9c39
ARM VST1 single lane assembly parsing.
...
llvm-svn: 145718
2011-12-02 22:34:51 +00:00
Nick Lewycky
7d0d3c2d58
Move global variables in TargetMachine into new TargetOptions class. As an API
...
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
Jim Grosbach
82ae7f46ea
ARM VLD1 single lane assembly parsing.
...
llvm-svn: 145712
2011-12-02 22:01:52 +00:00
Jim Grosbach
cbde5d4877
ARM encoder method needs the physical register number, not the enum.
...
llvm-svn: 145711
2011-12-02 22:01:25 +00:00
Chad Rosier
b3b2871bbf
[arm-fast-isel] After promoting a function parameter be sure to update the
...
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
Jim Grosbach
a568ef0db6
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
Jim Grosbach
d5c0c63223
ARM start parsing VLD1 single lane instructions.
...
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
Matt Beaumont-Gay
07afe588d4
Remove unused variable
...
llvm-svn: 145517
2011-11-30 19:53:11 +00:00
Jim Grosbach
6b2f6389cc
ARM parsing for VLD1 all lanes, with writeback.
...
llvm-svn: 145510
2011-11-30 19:35:44 +00:00
Jim Grosbach
fa9f6ccd62
ARM parsing for VLD1 two register all lanes, no writeback.
...
llvm-svn: 145504
2011-11-30 18:21:25 +00:00
Jim Grosbach
693ce8291c
ARM parsing aliases for VLD1 single register all lanes.
...
llvm-svn: 145464
2011-11-30 01:09:44 +00:00
Jim Grosbach
9adabf4dde
Tidy up a bit.
...
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
Jim Grosbach
ccc984051d
Add comment.
...
llvm-svn: 145456
2011-11-29 23:33:40 +00:00
Jim Grosbach
29147b45a5
ARM parsing aliases for data-size suffices on VST1.
...
llvm-svn: 145454
2011-11-29 23:21:31 +00:00
Jim Grosbach
538759efa7
ARM assembly parsing and encoding for four-register VST1.
...
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
Jim Grosbach
5418e87582
ARM assembly parsing and encoding for three-register VST1.
...
llvm-svn: 145442
2011-11-29 22:38:04 +00:00
Andrew Trick
a6c63bda2e
comment.
...
llvm-svn: 145422
2011-11-29 19:33:49 +00:00
Daniel Dunbar
4e00f5f8fd
build/CMake: Finish removal of add_llvm_library_dependencies.
...
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
Jim Grosbach
168778090c
Better fix for ARM MOVT relocation encoding of thumb bit.
...
Replaces r145318 with a more targetted fix for the relocation handling.
llvm-svn: 145346
2011-11-29 01:15:25 +00:00
Duncan Sands
ec13954efd
Silence wrong warnings from GCC about variables possibly being used
...
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
llvm-svn: 145239
2011-11-28 10:31:27 +00:00
Benjamin Kramer
d861d825f2
Move code into anonymous namespaces.
...
llvm-svn: 145154
2011-11-26 23:01:57 +00:00
NAKAMURA Takumi
48face75c4
ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.
...
llvm-svn: 145129
2011-11-25 09:19:57 +00:00
Chad Rosier
70dab03f8e
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
...
llvm-svn: 144959
2011-11-18 01:17:34 +00:00
Chad Rosier
7d2af13ccb
Add TODO comment.
...
llvm-svn: 144920
2011-11-17 21:46:13 +00:00
Chad Rosier
47928b03f3
Dead code.
...
llvm-svn: 144888
2011-11-17 07:24:49 +00:00
Chad Rosier
c9ed1d9072
Don't unconditionally set the kill flag.
...
rdar://10456186
llvm-svn: 144872
2011-11-17 01:16:53 +00:00
Jim Grosbach
fe5f0cfa29
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
Jim Grosbach
a14a3d22b1
Fix encoding of NOP used for padding in ARM mode .align.
...
llvm-svn: 144842
2011-11-16 22:40:25 +00:00
Jim Grosbach
8c8d091ecc
ARM assembly parsing for shifted register operands for MOV instruction.
...
llvm-svn: 144837
2011-11-16 21:50:05 +00:00
Jim Grosbach
6007a95d57
Clean up debug printing of ARM shifted operands.
...
llvm-svn: 144836
2011-11-16 21:46:50 +00:00
Jim Grosbach
e9b1f2aead
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
...
llvm-svn: 144814
2011-11-16 19:12:24 +00:00
Jim Grosbach
18844fca8d
ARM assembly parsing for RRX mnemonic.
...
rdar://9704684
llvm-svn: 144812
2011-11-16 19:05:59 +00:00
Chad Rosier
69f9c432a6
Check to make sure we can select the instruction before trying to put the
...
operands into a register. Otherwise, we may materialize dead code.
llvm-svn: 144805
2011-11-16 18:39:44 +00:00
Jim Grosbach
acb7c2d555
ARM mode aliases for bitwise instructions w/ register operands.
...
rdar://9704684
llvm-svn: 144803
2011-11-16 18:31:45 +00:00
Bob Wilson
70092e2b0a
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
...
llvm-svn: 144798
2011-11-16 17:09:59 +00:00
NAKAMURA Takumi
9a0c941fff
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
...
llvm-svn: 144794
2011-11-16 09:18:28 +00:00
Evan Cheng
2b239cbcf6
Sink codegen optimization level into MCCodeGenInfo along side relocation model
...
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
llvm-svn: 144788
2011-11-16 08:38:26 +00:00
Bob Wilson
0e88464871
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
...
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
llvm-svn: 144781
2011-11-16 07:11:57 +00:00
Chad Rosier
17577c9394
Add FIXME comment.
...
llvm-svn: 144743
2011-11-16 00:32:20 +00:00
Jakob Stoklund Olesen
5ea426cfa8
Enable -widen-vmovs by default.
...
This will widen 32-bit register vmov instructions to 64-bit when
possible. The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.
The copies are only widened if they are marked as clobbering the whole
D-register.
llvm-svn: 144734
2011-11-15 23:53:18 +00:00
Jim Grosbach
044acb8bee
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
Jim Grosbach
778bed02bb
ARM assembly parsing for data type suffices on NEON VMOV aliases.
...
llvm-svn: 144722
2011-11-15 22:54:42 +00:00
Jim Grosbach
b8ebc386df
ARM assembly parsing two operand forms for shift instructions.
...
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
Jim Grosbach
d573473cb8
ARM VFP assembly parsing for VADD and VSUB two-operand forms.
...
llvm-svn: 144710
2011-11-15 22:15:10 +00:00
Jim Grosbach
e991d79b50
ARM accept an immediate offset in memory operands w/o the '#'.
...
llvm-svn: 144709
2011-11-15 22:14:41 +00:00
Jim Grosbach
8f360855cf
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
...
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
llvm-svn: 144701
2011-11-15 21:45:55 +00:00
Jim Grosbach
3c205132ff
ARM size suffix on VFP single-precision 'vmov' is optional.
...
rdar://10435114
llvm-svn: 144698
2011-11-15 21:18:35 +00:00
Jim Grosbach
f68b81adb7
Fix typo.
...
llvm-svn: 144695
2011-11-15 21:01:30 +00:00
Jim Grosbach
4d0ad5a4e0
ARM alternate size suffices for VTRN instructions.
...
rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
Owen Anderson
f71db061ba
Fix a misplaced paren bug.
...
llvm-svn: 144692
2011-11-15 20:30:41 +00:00
Jim Grosbach
8987b277cb
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
...
Yet more of rdar://10435076.
llvm-svn: 144691
2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c
ARM assembly parsing for two-operand form of 'mul' instruction.
...
rdar://10449856.
llvm-svn: 144689
2011-11-15 20:14:51 +00:00
Jim Grosbach
8b1d4c989c
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
Jim Grosbach
6dbfffcbf7
Thumb2 two-operand 'mul' instruction wide encoding parsing.
...
rdar://10449724
llvm-svn: 144684
2011-11-15 19:55:16 +00:00
Owen Anderson
35f049f1fb
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
...
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
Jim Grosbach
df951fa128
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
Jim Grosbach
61c3f1b35b
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
...
rdar://10435076
llvm-svn: 144650
2011-11-15 17:49:59 +00:00
Jay Foad
ebf2ec40e0
Fix typo in comment.
...
llvm-svn: 144633
2011-11-15 07:50:05 +00:00
Jay Foad
b4bb79247a
Make use of MachinePointerInfo::getFixedStack. This removes all mention
...
of PseudoSourceValue from lib/Target/.
llvm-svn: 144632
2011-11-15 07:34:52 +00:00
Jay Foad
7d05fea7f8
Remove some unnecessary includes of PseudoSourceValue.h.
...
llvm-svn: 144631
2011-11-15 07:24:32 +00:00
Evan Cheng
47d8f8af84
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
...
integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
Jim Grosbach
2ac98a24aa
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
...
rdar://10435076
llvm-svn: 144606
2011-11-15 01:46:57 +00:00
Jim Grosbach
6846540505
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
...
rdar://10435076
llvm-svn: 144593
2011-11-14 23:43:46 +00:00
Jim Grosbach
a1a28df278
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
...
rdar://10435076
llvm-svn: 144592
2011-11-14 23:32:59 +00:00
Jim Grosbach
8ec84fbe99
Add explanatory comment.
...
llvm-svn: 144589
2011-11-14 23:21:09 +00:00
Jim Grosbach
1d07736422
Split out the plain '.{8|16|32|64}' suffix handling.
...
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.
llvm-svn: 144588
2011-11-14 23:20:14 +00:00
Jim Grosbach
00283a5c8e
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
...
rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
Chad Rosier
4e05d7f12c
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
...
violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
llvm-svn: 144585
2011-11-14 23:04:09 +00:00
Jim Grosbach
4a2f107b04
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
Chad Rosier
48b92815e0
Add support for inlining small memcpys.
...
rdar://10412592
llvm-svn: 144578
2011-11-14 22:46:17 +00:00
Chad Rosier
8aa8f14940
Fix a performance regression from r144565. Positive offsets were being lowered
...
into registers, rather then encoded directly in the load/store.
llvm-svn: 144576
2011-11-14 22:34:48 +00:00
Jim Grosbach
009733c9e4
ARM assembly parsing type suffix options for VLDR/VSTR.
...
rdar://10435076
llvm-svn: 144575
2011-11-14 22:28:39 +00:00
Chad Rosier
65395ac4d0
Add support for Thumb load/stores with negative offsets.
...
rdar://10412592
llvm-svn: 144565
2011-11-14 20:22:27 +00:00
Jim Grosbach
d791cf718c
Tidy up. 80 column.
...
llvm-svn: 144538
2011-11-14 17:52:47 +00:00
Chad Rosier
0e5094ca87
Add support for ARM halfword load/stores and signed byte loads with negative
...
offsets.
rdar://10412592
llvm-svn: 144518
2011-11-14 04:09:28 +00:00
Chad Rosier
58ab241006
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
...
llvm-svn: 144494
2011-11-13 09:44:21 +00:00
Chad Rosier
8cfccc356e
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
...
llvm-svn: 144492
2011-11-13 05:14:43 +00:00
Chad Rosier
0770c4834a
Fix comments.
...
llvm-svn: 144490
2011-11-13 04:25:02 +00:00
Chad Rosier
acd199b5a4
Add support for emitting both signed- and zero-extend loads. Fix
...
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
Daniel Dunbar
73d41b0f03
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
...
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
2011-11-12 02:10:57 +00:00
Jim Grosbach
7e41554aa7
ARM refactor simple immediate asm operand render methods.
...
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
llvm-svn: 144439
2011-11-12 00:58:43 +00:00
Jim Grosbach
312b583950
Re-apply 144430, this time with the associated isel and disassmbler bits.
...
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
Jim Grosbach
7fccd540c9
Oops. Missed the isel half of this. revert while I sort that out.
...
llvm-svn: 144431
2011-11-11 23:51:31 +00:00
Jim Grosbach
13af5276a1
ARM assembly parsing for VST1 two-register encoding.
...
llvm-svn: 144430
2011-11-11 23:45:47 +00:00
Jim Grosbach
13b7ab7527
ARM optional size suffix for VLDR/VSTR syntax.
...
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
Chad Rosier
a2a0fbeded
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
...
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
Jim Grosbach
bc077320e1
ARM vldm and vstm VFP instructions can take a data type suffix.
...
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
llvm-svn: 144422
2011-11-11 23:08:10 +00:00
Jim Grosbach
01a7117803
Nuke no longer accurate comment.
...
llvm-svn: 144411
2011-11-11 22:30:06 +00:00
Andrew Trick
6ff75a5d8d
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
...
Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
Jim Grosbach
1d581ecb00
ARM allow Q registers in vldm/vstm register lists.
...
rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
Benjamin Kramer
e5295a772e
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
...
llvm-svn: 144384
2011-11-11 12:39:41 +00:00
Chad Rosier
98f48b009e
Rename variables to avoid confusion. No functionallity change intended.
...
llvm-svn: 144377
2011-11-11 06:27:41 +00:00
Chad Rosier
feb72bfc08
Add support for using immediates with select instructions.
...
rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
Eli Friedman
285b451941
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
...
llvm-svn: 144361
2011-11-11 03:16:38 +00:00
Chad Rosier
38f07d3f9c
When loading a value, treat an i1 as an i8.
...
llvm-svn: 144356
2011-11-11 02:38:59 +00:00
Chad Rosier
ac92994773
Add support for using MVN to materialize negative constants.
...
rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
Daniel Dunbar
846fb32afc
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
...
llvm-svn: 144344
2011-11-11 00:23:56 +00:00
Jim Grosbach
ddf85f6be2
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
...
rdar://10429490
llvm-svn: 144338
2011-11-10 23:58:34 +00:00
Jim Grosbach
d1d04109ff
ARM let processInstruction() tranforms chain.
...
llvm-svn: 144337
2011-11-10 23:42:14 +00:00
Jim Grosbach
bd7df609b7
Thumb2 parsing for push/pop w/ hi registers in the reglist.
...
rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
Jim Grosbach
615c824de4
Thumb1 diagnostics for reglist on PUSH/POP fix.
...
Was not checking the first register in the register list.
llvm-svn: 144329
2011-11-10 23:01:27 +00:00
Jim Grosbach
c3651cb620
Thumb MUL assembly parsing for 3-operand form.
...
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
Chad Rosier
7b7dced006
When in ARM mode, LDRH/STRH require special handling of negative offsets.
...
For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
Jim Grosbach
614f35bb30
ARM .thumb_func directive for quoted symbol names.
...
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
llvm-svn: 144315
2011-11-10 20:48:53 +00:00
Jim Grosbach
f5943e4c5e
ARM assembly parsing for LSR/LSL/ROR(immediate).
...
More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
Chad Rosier
69cdae5eb9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
Daniel Dunbar
f0c4aed0ab
llvm-build: Add --native-target and --enable-targets options, and add logic to
...
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
llvm-svn: 144253
2011-11-10 00:50:07 +00:00
Daniel Dunbar
c09b47db8f
llvm-build: Add an explicit component type to represent targets.
...
- Gives us a place to hang target specific metadata (like whether the target has a JIT).
llvm-svn: 144250
2011-11-10 00:49:51 +00:00
Jim Grosbach
ee70556a4e
Tidy up.
...
llvm-svn: 144244
2011-11-10 00:02:33 +00:00
Jim Grosbach
8591bd2bab
Thumb2 assembly parsing STMDB w/ optional .w suffix.
...
rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
Eli Friedman
c93f8aa514
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
...
llvm-svn: 144241
2011-11-09 23:36:02 +00:00
Chad Rosier
f47b941510
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
...
rdar://10418009
llvm-svn: 144213
2011-11-09 21:30:12 +00:00
Chad Rosier
e32fed6868
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
...
remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
Evan Cheng
2b29230fcf
Hide cpu name checking in ARMSubtarget.
...
llvm-svn: 144154
2011-11-09 01:57:03 +00:00
Evan Cheng
08e61752f2
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
...
llvm-svn: 144123
2011-11-08 21:21:09 +00:00
Chad Rosier
24a6e399f8
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
...
No functional change intended.
llvm-svn: 144122
2011-11-08 21:12:00 +00:00
Lang Hames
ee7de1cff0
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
...
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
llvm-svn: 144102
2011-11-08 18:56:23 +00:00
Pete Cooper
224434deec
Added invariant field to the DAG.getLoad method and changed all calls.
...
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
Eli Friedman
d5ba38a3d2
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
...
llvm-svn: 144057
2011-11-08 01:43:53 +00:00
Chad Rosier
4b12a5b7fc
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
...
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
Chad Rosier
7e0e075322
Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well.
...
llvm-svn: 144021
2011-11-07 21:43:40 +00:00
Benjamin Kramer
89ebc7ab4b
Simplify some uses of utohexstr.
...
As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
Benjamin Kramer
c597902ecc
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
...
llvm-svn: 143891
2011-11-06 20:37:06 +00:00
Chad Rosier
806ffd8918
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
...
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
Chad Rosier
af23ffd465
Allow i1 to be promoted to i32 for ARM APCS calling convention.
...
llvm-svn: 143755
2011-11-05 00:02:56 +00:00
Chad Rosier
5e54485e51
Cannot create a result register for non-legal types.
...
llvm-svn: 143749
2011-11-04 23:45:39 +00:00
Chad Rosier
a900a3e2f6
When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
...
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend. This prevents us from materializing things
such as 'true' (i.e., i1 1).
llvm-svn: 143743
2011-11-04 23:09:49 +00:00
Chad Rosier
0143eb6f22
Enable support for materializing i1, i8, and i16 integers via move immediate.
...
llvm-svn: 143739
2011-11-04 22:29:00 +00:00
Daniel Dunbar
799f4bb723
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
...
added a layer of indirection with no value (not even conciseness).
llvm-svn: 143727
2011-11-04 19:04:23 +00:00
Evan Cheng
e4d6efb7c4
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen.
...
llvm-svn: 143675
2011-11-04 01:48:58 +00:00
Chad Rosier
8836fe3bbd
Indentation.
...
llvm-svn: 143670
2011-11-04 00:58:10 +00:00
Chad Rosier
21cd759234
Add fast-isel support for returning i1, i8, and i16.
...
llvm-svn: 143669
2011-11-04 00:50:21 +00:00
Dan Gohman
a5f382da8b
Reapply r143206, with fixes. Disallow physical register lifetimes
...
across calls, and only check for nested dependences on the special
call-sequence-resource register.
llvm-svn: 143660
2011-11-03 21:49:52 +00:00
Daniel Dunbar
3760ebeebb
build: Add initial cut at LLVMBuild.txt files.
...
llvm-svn: 143634
2011-11-03 18:53:17 +00:00
Chad Rosier
74c4e2c2d9
Add support for sign-extending non-legal types in SelectSIToFP().
...
llvm-svn: 143603
2011-11-03 02:04:59 +00:00
Lang Hames
ba63f9da8b
Fixed parameter name.
...
llvm-svn: 143594
2011-11-02 23:37:04 +00:00
Lang Hames
ceec8ec67e
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
...
llvm-svn: 143582
2011-11-02 22:52:45 +00:00
Chad Rosier
8a613c5ec5
Add support for comparing integer non-legal types.
...
llvm-svn: 143559
2011-11-02 18:08:25 +00:00
Owen Anderson
ac9fd95057
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
...
llvm-svn: 143557
2011-11-02 18:03:14 +00:00
Owen Anderson
66d22d36d2
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
...
llvm-svn: 143553
2011-11-02 17:46:18 +00:00
Owen Anderson
9b966e47e2
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
...
llvm-svn: 143552
2011-11-02 17:41:23 +00:00
Chad Rosier
e94ff7c26e
Factor out an EmitIntExt function. No functionality change intended.
...
llvm-svn: 143547
2011-11-02 17:20:24 +00:00
Chad Rosier
f72870096b
Factor out a SelectTrunc function. No functionality change intended.
...
llvm-svn: 143523
2011-11-02 00:18:48 +00:00
Jim Grosbach
577b0f181e
ARM label operands can be quoted.
...
For example, labels from Objective-C sources.
llvm-svn: 143511
2011-11-01 22:38:31 +00:00
Jim Grosbach
e5b5830aa1
ARM label operands can have an optional '#' before them.
...
llvm-svn: 143510
2011-11-01 22:37:37 +00:00
Owen Anderson
0d69f6aa51
Fix disassembly of some VST1 instructions.
...
llvm-svn: 143507
2011-11-01 22:18:13 +00:00
Jim Grosbach
c5f44d0b71
ARM VLD/VST assembly parsing for symbolic address operands.
...
llvm-svn: 143413
2011-11-01 01:24:45 +00:00
Jim Grosbach
76dd8a9702
ARM VST1 w/ writeback assembly parsing and encoding.
...
llvm-svn: 143369
2011-10-31 21:50:31 +00:00
Jim Grosbach
1cca1d4e60
ARM writeback vs. stride operands for VST/VLD.
...
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.
llvm-svn: 143356
2011-10-31 19:11:23 +00:00
Owen Anderson
d7700cb13f
More not-crashing NEON disassembly updates for the vld refactoring.
...
llvm-svn: 143351
2011-10-31 17:17:32 +00:00
Dan Gohman
826cec9a4b
Revert r143206, as there are still some failing tests.
...
llvm-svn: 143262
2011-10-29 00:41:52 +00:00
Jim Grosbach
37119b8a01
ARM mode 'mov' to 'mvn' assembler alias.
...
llvm-svn: 143237
2011-10-28 22:50:54 +00:00
Jim Grosbach
f3285dba99
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
...
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
llvm-svn: 143235
2011-10-28 22:36:30 +00:00
Owen Anderson
5fdb303642
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
...
llvm-svn: 143220
2011-10-28 20:43:24 +00:00
Owen Anderson
3dd6c949a5
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
...
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
Dan Gohman
dedcc22bcd
Reapply r143177 and r143179 (reverting r143188), with scheduler
...
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
llvm-svn: 143206
2011-10-28 17:55:38 +00:00
Owen Anderson
5ccc0979a0
Revert r143202.
...
llvm-svn: 143203
2011-10-28 17:38:30 +00:00
Owen Anderson
5c58be2852
Specify fixed bits on CPS instructions to enable roundtripping.
...
llvm-svn: 143202
2011-10-28 17:29:39 +00:00
Jim Grosbach
72ab459378
Thumb2 ADD/SUB instructions encoding selection outside IT block.
...
Outside an IT block, "add r3, #2 " should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
llvm-svn: 143201
2011-10-28 16:57:07 +00:00
Duncan Sands
a6507c4bcb
Speculatively disable Dan's commits 143177 and 143179 to see if
...
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
llvm-svn: 143188
2011-10-28 09:55:57 +00:00
Dan Gohman
484df993bd
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
...
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
llvm-svn: 143177
2011-10-28 01:29:32 +00:00
Jim Grosbach
dac7815a91
ARM Allow 'q' registers in VLD/VST vector lists.
...
Just treat it as if the constituent D registers where specified.
rdar://10348896
llvm-svn: 143167
2011-10-28 00:06:50 +00:00
Owen Anderson
d35df0aaeb
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
...
llvm-svn: 143162
2011-10-27 22:53:10 +00:00
Jakob Stoklund Olesen
de21509dcd
Also set addrmode6 alignment when align==size.
...
Previously, we were only setting the alignment bits on over-aligned
loads and stores.
llvm-svn: 143160
2011-10-27 22:39:16 +00:00
Jim Grosbach
67d4fb4bc0
ARM isel for vld1, opcode selection for register stride post-index pseudos.
...
llvm-svn: 143158
2011-10-27 22:25:42 +00:00
Evan Cheng
75271d09f1
Avoid partial CPSR dependency from loop backedges. rdar://10357570
...
llvm-svn: 143145
2011-10-27 21:21:05 +00:00
Jim Grosbach
4f7964293a
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
...
rdar://10348844
llvm-svn: 143110
2011-10-27 17:33:59 +00:00
Jim Grosbach
e1ec953149
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
...
rdar://10348584
llvm-svn: 143108
2011-10-27 17:16:55 +00:00
Chad Rosier
e76ba1b654
A branch predicated on a constant can just FastEmit an unconditional branch.
...
llvm-svn: 143086
2011-10-27 00:21:16 +00:00
Chad Rosier
e3141f4f8b
Add a TODO comment. FastISel works by parsing each basic block from the bottom
...
up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
llvm-svn: 143079
2011-10-26 23:34:37 +00:00
Chad Rosier
75378507e3
Factor a little more code into EmitCmp, which should have been done in the first
...
place. No functional change intended.
llvm-svn: 143078
2011-10-26 23:25:44 +00:00
Chad Rosier
52109646da
Use EmitCmp in SelectBranch. No functional change intended.
...
llvm-svn: 143076
2011-10-26 23:17:28 +00:00
Chad Rosier
3f38cb48de
Factor out an EmitCmp function that can be used by both SelectCmp and
...
SelectBranch. No functional change intended.
llvm-svn: 143072
2011-10-26 22:47:55 +00:00
Jim Grosbach
e3c6fa663f
Thumb2 ldr pc-relative encoding fixes.
...
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
llvm-svn: 143068
2011-10-26 22:22:01 +00:00
Jim Grosbach
4597f361f6
ARM parse parenthesized expressions for label references.
...
Partial fix for rdar://10348687.
llvm-svn: 143063
2011-10-26 21:14:08 +00:00
Lang Hames
d87e366c7f
Make sure short memsets on ARM lower to stores, even when optimizing for size.
...
llvm-svn: 143055
2011-10-26 20:56:52 +00:00
Jim Grosbach
5a61a956cb
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
...
llvm-svn: 143034
2011-10-26 17:28:15 +00:00
James Molloy
9afc8b08f7
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
...
llvm-svn: 143023
2011-10-26 08:53:19 +00:00
Bill Wendling
b0dc0e18ca
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.
...
llvm-svn: 143018
2011-10-26 07:16:18 +00:00
Evan Cheng
941d5c148f
Revert part of r142530. The patch potentially hurts performance especially
...
on Darwin platforms where -Os means optimize for size without hurting
performance.
llvm-svn: 143002
2011-10-26 01:17:44 +00:00
Jim Grosbach
fabe0f2f0b
ARM assembly parsing and encoding for VLD1 with writeback.
...
Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
Jim Grosbach
e8a2edd71c
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
...
llvm-svn: 142877
2011-10-24 23:40:46 +00:00
Jim Grosbach
688186941f
ARM assembly parsing and encoding for VLD1 w/ writeback.
...
Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
Eli Friedman
652497e03c
Don't crash on variable insertelement on ARM. PR10258.
...
llvm-svn: 142871
2011-10-24 23:08:52 +00:00
Evan Cheng
b792a7d95b
ARMConstantPoolMBB::print should print BB number.
...
llvm-svn: 142867
2011-10-24 23:01:03 +00:00
Jim Grosbach
cf4fba1dd0
ARM assembly parsing and encoding for VLD1 w/ writeback.
...
One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
Jim Grosbach
4a6508dd4e
ARM refactor am6offset usage for VLD1.
...
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
Owen Anderson
b0e09258e7
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
...
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
Dan Gohman
898ed35860
Change this overloaded use of Sched::Latency to be an overloaded
...
use of Sched::ILP instead, as Sched::Latency is going away.
llvm-svn: 142813
2011-10-24 17:55:11 +00:00
Jim Grosbach
eceea163ef
Thumb2 LDM instructions can target PC. Make sure to encode it.
...
PR11220
llvm-svn: 142801
2011-10-24 17:16:24 +00:00
Benjamin Kramer
03065133c3
Move various generated tables into read-only memory, fixing up const correctness along the way.
...
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
Bill Wendling
66327a8d0e
The different flavors of ARM have different valid subsets of registers. Check
...
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
llvm-svn: 142706
2011-10-22 00:29:28 +00:00
Jim Grosbach
d964cf8939
Assembly parsing for 4-register sequential variant of VLD2.
...
llvm-svn: 142704
2011-10-21 23:58:57 +00:00