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llvm-mirror/test/CodeGen/RISCV
Sam Elliott 8205c3a802 [RISCV] Fix ICE in isDesirableToCommuteWithShift
Summary:
There was an error being thrown from isDesirableToCommuteWithShift in
some tests. This was tracked down to the method being called before
legalisation, with an extended value type, not a machine value type.

In the case I diagnosed, the error was only hit with an instruction sequence
involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is
instead an Extended ValueType which was causing the issue.

I have added a test to cover this case, and fixed the error in the callback.

Reviewers: asb, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64425

llvm-svn: 365511
2019-07-09 16:24:16 +00:00
..
add-before-shl.ll [RISCV] Fix ICE in isDesirableToCommuteWithShift 2019-07-09 16:24:16 +00:00
addc-adde-sube-subc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
addcarry.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
align.ll
alloca.ll
alu8.ll
alu16.ll
alu32.ll
alu64.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
analyze-branch.ll
arith-with-overflow.ll
atomic-cmpxchg-flag.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
atomic-cmpxchg.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
atomic-fence.ll
atomic-load-store.ll
atomic-rmw.ll [RISCV] Regenerate remat.ll and atomic-rmw.ll after D43256 2019-06-15 07:49:14 +00:00
bare-select.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
blockaddress.ll
branch-relaxation.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
branch.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
bswap-ctlz-cttz-ctpop.ll
byval.ll
callee-saved-fpr32s.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
callee-saved-fpr64s.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
callee-saved-gprs.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
calling-conv-ilp32-ilp32f-common.ll
calling-conv-ilp32-ilp32f-ilp32d-common.ll
calling-conv-ilp32.ll
calling-conv-ilp32d.ll
calling-conv-ilp32f-ilp32d-common.ll
calling-conv-lp64-lp64f-common.ll
calling-conv-lp64-lp64f-lp64d-common.ll
calling-conv-lp64.ll
calling-conv-rv32f-ilp32.ll
calling-conv-sext-zext.ll
calls.ll [RISCV] Lower calls through PLT 2019-06-18 14:29:45 +00:00
codemodel-lowering.ll
compress-inline-asm.ll
compress.ll
disable-tail-calls.ll
div.ll
double-arith.ll
double-bitmanip-dagcombines.ll
double-br-fcmp.ll
double-calling-conv.ll
double-convert.ll
double-fcmp.ll
double-frem.ll
double-imm.ll
double-intrinsics.ll
double-mem.ll
double-previous-failure.ll
double-select-fcmp.ll
double-stack-spill-restore.ll
exception-pointer-register.ll [RISCV] Specify registers used in DWARF exception handling 2019-07-08 09:16:47 +00:00
fixups-diff.ll
fixups-relax-diff.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
float-arith.ll
float-bit-preserving-dagcombines.ll [RISCV] Support Bit-Preserving FP in F/D Extensions 2019-06-07 12:20:14 +00:00
float-bitmanip-dagcombines.ll
float-br-fcmp.ll
float-convert.ll
float-fcmp.ll
float-frem.ll
float-imm.ll
float-intrinsics.ll
float-mem.ll
float-select-fcmp.ll
flt-rounds.ll
fp128.ll
frame-info.ll [RISCV] Add CFI directives for RISCV prologue/epilog. 2019-06-12 03:04:22 +00:00
frame.ll
frameaddr-returnaddr.ll
get-setcc-result-type.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
hoist-global-addr-base.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
i32-icmp.ll
imm-cse.ll [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
imm.ll
indirectbr.ll
init-array.ll
inline-asm-i-constraint-i1.ll [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
inline-asm-invalid.ll [RISCV][NFC] Add missing test file for D54093 2019-06-11 12:52:05 +00:00
inline-asm.ll [RISCV] Support z and i operand modifiers 2019-07-08 05:00:26 +00:00
interrupt-attr-args-error.ll
interrupt-attr-invalid.ll
interrupt-attr-nocall.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
interrupt-attr-ret-error.ll
interrupt-attr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
jumptable.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
large-stack.ll
legalize-fneg.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
lit.local.cfg
lsr-legaladdimm.ll
mattr-invalid-combination.ll
mem64.ll
mem.ll
mul.ll
musttail-call.ll
option-norelax.ll
option-norvc.ll
option-relax.ll
option-rvc.ll
pic-models.ll [RISCV] Add lowering of addressing sequences for PIC 2019-06-11 12:57:47 +00:00
pr40333.ll
prefetch.ll
readcyclecounter.ll [RISCV] Support @llvm.readcyclecounter() Intrinsic 2019-07-05 12:35:21 +00:00
rem.ll
remat.ll [RISCV] Regenerate remat.ll and atomic-rmw.ll after D43256 2019-06-15 07:49:14 +00:00
rotl-rotr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv32e.ll
rv32i-rv64i-float-double.ll
rv64d-double-convert.ll
rv64f-float-convert.ll
rv64i-exhaustive-w-insts.ll
rv64i-tricky-shifts.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv64m-exhaustive-w-insts.ll
sdata-limit-0.ll
sdata-limit-4.ll
sdata-limit-8.ll
sdata-local-sym.ll
select-cc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
select-optimize-multiple.ll
select-optimize-multiple.mir [RISCV] Fix test after r363757 2019-06-19 03:18:48 +00:00
setcc-logic.ll
sext-zext-trunc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
shift-masked-shamt.ll
shifts.ll
split-offsets.ll [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting 2019-06-17 10:54:12 +00:00
tail-calls.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
target-abi-invalid.ll
target-abi-valid.ll
tls-models.ll [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
umulo-128-legalisation-lowering.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
vararg.ll
wide-mem.ll
zext-with-load-is-free.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00