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llvm-mirror/lib/Target/AMDGPU
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Michael Liao 7a293f5b3c [amdgpu] Skip OR combining on 64-bit integer before legalizing ops. 
Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81710
2020-06-12 15:22:38 -04:00
..
AsmParser
[AMDGPU][MC][GFX908] Corrected src0 of v_accvgpr_write to accept only VGPRs and inline constants.
2020-05-28 15:10:55 +03:00
Disassembler
[AMDGPU][MC][DISASSEMBLER] Corrected decoder to consume each code fragment only once
2020-05-28 14:20:18 +03:00
MCTargetDesc
AMDGPUInstPrinter.cpp - add CommandLine.h include. NFC.
2020-05-24 14:17:04 +01:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
AMDGPU.h
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
AMDGPU.td
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
AMDGPUAliasAnalysis.cpp
AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory
2020-05-09 16:00:08 -04:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
AMDGPU: Hack out noinline on functions using LDS globals
2020-04-02 14:12:07 -04:00
AMDGPUAnnotateKernelFeatures.cpp
AMDGPU: Annotate functions that have stack objects
2020-05-19 18:51:00 -04:00
AMDGPUAnnotateUniformValues.cpp
AMDGPU: Fix not using scalar loads for global reads in shaders
2020-06-02 09:49:23 -04:00
AMDGPUArgumentUsageInfo.cpp
AMDGPU: Add flag to used fixed function ABI
2020-03-13 13:27:05 -07:00
AMDGPUArgumentUsageInfo.h
AMDGPUArgumentUsageInfo.h - cleanup includes and forward declarations. NFC.
2020-04-24 16:21:37 +01:00
AMDGPUAsmPrinter.cpp
AMDGPU: Support non-entry block static sized allocas
2020-05-27 18:46:10 -04:00
AMDGPUAsmPrinter.h
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
AMDGPUAtomicOptimizer.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPUCallingConv.td
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
AMDGPUCallLowering.cpp
CodeGen: Use Register
2020-05-19 17:56:55 -04:00
AMDGPUCallLowering.h
[Alignment][NFC] Transition to inferAlignFromPtrInfo
2020-03-31 08:06:49 +00:00
AMDGPUCodeGenPrepare.cpp
[SVE] Remove usages of VectorType::getNumElements() from AMDGPU
2020-05-13 15:57:55 -07:00
AMDGPUCombine.td
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
AMDGPUExportClustering.cpp
[AMDGPU] Strengthen export cluster ordering
2020-05-13 23:07:37 +09:00
AMDGPUExportClustering.h
[AMDGPU] Cluster shader exports
2020-05-07 19:05:38 +09:00
AMDGPUFeatures.td
AMDGPU: Change internal tracking of wave size
2020-06-01 17:55:08 -04:00
AMDGPUFixFunctionBitcasts.cpp
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
[Alignment][NFC] Deprecate Align::None()
2020-01-24 12:53:58 +01:00
AMDGPUGenRegisterBankInfo.def
[AMDGPU][GlobalISel] Revise handling of wide loads in RegBankSelect
2020-05-11 18:10:16 -07:00
AMDGPUGISel.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
AMDGPUGlobalISelUtils.cpp
AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR
2020-02-21 13:35:40 -05:00
AMDGPUGlobalISelUtils.h
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
AMDGPUHSAMetadataStreamer.cpp
[SVE] Remove usages of VectorType::getNumElements() from AMDGPU
2020-05-13 15:57:55 -07:00
AMDGPUHSAMetadataStreamer.h
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUInline.cpp
Revert "Revert "[llvm][NFC] Cleanup uses of std::function in Inlining-related APIs""
2020-05-15 12:29:16 -07:00
AMDGPUInstrInfo.cpp
[AMDGPU] Remove AMDGPURegisterInfo
2020-02-11 11:13:38 -08:00
AMDGPUInstrInfo.h
AMDGPU/GlobalISel: Change intrinsic ID for _L to _LZ opt
2020-04-01 13:03:02 -04:00
AMDGPUInstrInfo.td
AMDGPU: Add intrinsic for s_setreg
2020-05-28 14:26:38 -04:00
AMDGPUInstructions.td
AMDGPU: Change pre-gfx9 implementation of fcanonicalize to mul
2020-04-23 15:24:13 -04:00
AMDGPUInstructionSelector.cpp
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
AMDGPUInstructionSelector.h
GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic
2020-05-26 11:48:13 -04:00
AMDGPUISelDAGToDAG.cpp
LegacyDivergenceAnalysis.h - reduce DivergenceAnalysis.h include to forward declaration. NFC.
2020-06-06 13:30:00 +01:00
AMDGPUISelLowering.cpp
AMDGPU: Stop using getSelectCC in division lowering
2020-06-10 13:56:53 -04:00
AMDGPUISelLowering.h
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPULegalizerInfo.cpp
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Legalize 64-bit G_UDIV/G_UREM
2020-03-30 10:57:37 -04:00
AMDGPULibCalls.cpp
[AMDGPU][NFC] Skip processing intrinsics that do not become real instructions
2020-06-09 03:45:33 +03:00
AMDGPULibFunc.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPULibFunc.h
AMDGPULibFunc - fix include order. NFC.
2020-05-24 13:25:59 +01:00
AMDGPULowerIntrinsics.cpp
AMDGPU: Add flag to control mem intrinsic expansion
2020-02-03 14:26:01 -08:00
AMDGPULowerKernelArguments.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPULowerKernelAttributes.cpp
…
AMDGPUMachineCFGStructurizer.cpp
[AMDGPU] Fixes -Wrange-loop-analysis warnings
2019-12-22 19:39:28 +01:00
AMDGPUMachineFunction.cpp
AMDGPU: Use member initializers in MFI
2020-05-19 18:11:34 -04:00
AMDGPUMachineFunction.h
AMDGPU: Use member initializers in MFI
2020-05-19 18:11:34 -04:00
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
2020-03-11 17:59:21 +00:00
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
Avoid SmallString.h include in MD5.h, NFC
2020-02-26 09:10:24 -08:00
AMDGPUPerfHintAnalysis.cpp
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUPerfHintAnalysis.h
…
AMDGPUPostLegalizerCombiner.cpp
AMDGPU/GlobalISel: Combines for V_CVT_F32_UBYTE[0-3]
2020-04-13 19:18:19 -04:00
AMDGPUPreLegalizerCombiner.cpp
AMDGPU/GlobalISel: Introduce post-legalize combiner
2020-02-24 22:12:12 -05:00
AMDGPUPrintfRuntimeBinding.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPUPromoteAlloca.cpp
[AMDGPU] Fixed promote alloca with ptr/int casts
2020-06-10 11:46:57 -07:00
AMDGPUPropagateAttributes.cpp
[AMDGPU] Propagate amdgpu-waves-per-eu to callees
2020-03-26 14:43:44 -07:00
AMDGPUPTNote.h
…
AMDGPURegBankCombiner.cpp
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
AMDGPURegisterBankInfo.cpp
AMDGPU/GlobalISel: cmp/select method for insert element
2020-06-10 13:12:54 -07:00
AMDGPURegisterBankInfo.h
AMDGPU/GlobalISel: cmp/select method for insert element
2020-06-10 13:12:54 -07:00
AMDGPURegisterBanks.td
[AMDGPU] Define AGPR subregs
2020-04-28 15:30:43 -07:00
AMDGPURewriteOutArguments.cpp
[SVE] Remove usages of VectorType::getNumElements() from AMDGPU
2020-05-13 15:57:55 -07:00
AMDGPUSearchableTables.td
AMDGPU: llvm.amdgcn.writelane is a source of divergence
2020-02-12 09:12:56 +01:00
AMDGPUSubtarget.cpp
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
AMDGPUSubtarget.h
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
AMDGPUTargetMachine.cpp
[AMDGPU] Enable structurizer workarounds by default
2020-06-09 13:14:15 +05:30
AMDGPUTargetMachine.h
AMDGPU: Fix wrong null value for private address space
2020-05-26 16:35:13 -04:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
AMDGPUTargetObjectFile.h - remove unnecessary includes. NFC.
2020-05-24 13:57:02 +01:00
AMDGPUTargetTransformInfo.cpp
[CostModel] Unify Shuffle and InsertElement Costs
2020-06-10 09:13:34 +01:00
AMDGPUTargetTransformInfo.h
InferAddressSpaces: Handle ptrmask intrinsic
2020-05-28 10:04:02 -04:00
AMDGPUUnifyDivergentExitNodes.cpp
Correctly report modified status for AMDGPUUnifyDivergentExitNodes
2020-06-05 19:49:37 +01:00
AMDGPUUnifyMetadata.cpp
[AMDGPU] Fixes -Wrange-loop-analysis warnings
2019-12-22 19:39:28 +01:00
AMDILCFGStructurizer.cpp
…
AMDKernelCodeT.h
…
BUFInstructions.td
AMDGPU/GlobalISel: Fix select of private <2 x s16> load
2020-06-11 19:25:25 -04:00
CaymanInstructions.td
AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x)
2020-02-05 00:24:07 -05:00
CMakeLists.txt
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
DSInstructions.td
AMDGPU/GlobalISel: Fix test failure in release build
2020-06-06 11:01:18 -04:00
EvergreenInstructions.td
[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #
2020-04-25 16:26:45 -07:00
FLATInstructions.td
AMDGPU: Fix overriding global FP atomic feature predicates
2020-06-04 17:50:38 -04:00
GCNDPPCombine.cpp
AMDGPU: Fix dropping MI flags when rewriting instructions
2020-05-27 13:27:06 -04:00
GCNHazardRecognizer.cpp
[AMDGPU] Don't implement GCNHazardRecognizer::PreEmitNoops(SUnit *)
2020-05-06 16:11:19 +01:00
GCNHazardRecognizer.h
[AMDGPU] Don't implement GCNHazardRecognizer::PreEmitNoops(SUnit *)
2020-05-06 16:11:19 +01:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU] Add file headers for few files where it is missing.
2020-01-31 02:06:41 +05:30
GCNIterativeScheduler.h
[AMDGPU] Add file headers for few files where it is missing.
2020-01-31 02:06:41 +05:30
GCNMinRegStrategy.cpp
SmallPtrSet::find -> SmallPtrSet::count
2020-06-07 22:38:08 +02:00
GCNNSAReassign.cpp
AMDGPU/GFX10: Fix NSA reassign pass when operands are undef
2020-02-01 22:41:40 +01:00
GCNProcessors.td
…
GCNRegBankReassign.cpp
[AMDGPU] Adapt GCNRegBankReassign for 16 bit subregs
2020-04-28 16:16:04 -07:00
GCNRegPressure.cpp
[AMDGPU] Fix assumption about LaneBitmask content
2020-02-19 09:07:11 -08:00
GCNRegPressure.h
Upgrade some instances of std::sort to llvm::sort. NFC.
2020-03-28 19:23:29 +01:00
GCNSchedStrategy.cpp
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
GCNSchedStrategy.h
[AMDGPU] Attempt to reschedule withou clustering
2020-01-27 10:27:16 -08:00
LLVMBuild.txt
…
MIMGInstructions.td
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
R600.td
…
R600AsmPrinter.cpp
[MC] Add MCStreamer::emitInt{8,16,32,64}
2020-02-29 09:40:21 -08:00
R600AsmPrinter.h
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
[AMDGPU] Make use of divideCeil. NFC.
2020-03-26 16:11:35 +00:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
[AMDGPU] Split R600 and GCN subregs
2020-02-10 08:29:56 -08:00
R600FrameLowering.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600FrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600InstrFormats.td
…
R600InstrInfo.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600InstrInfo.h
…
R600Instructions.td
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
R600ISelLowering.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600ISelLowering.h
…
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
…
R600Packetizer.cpp
…
R600Processors.td
…
R600RegisterInfo.cpp
[TBLGEN] Allow to override RC weight
2020-02-14 15:49:52 -08:00
R600RegisterInfo.h
[TBLGEN] Allow to override RC weight
2020-02-14 15:49:52 -08:00
R600RegisterInfo.td
[TBLGEN] Allow to override RC weight
2020-02-14 15:49:52 -08:00
R600Schedule.td
…
R700Instructions.td
…
SIAddIMGInit.cpp
[AMDGPU] Split R600 and GCN subregs
2020-02-10 08:29:56 -08:00
SIAnnotateControlFlow.cpp
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
2020-02-03 07:02:05 -08:00
SIDefines.h
AMDGPU: Optimize s_setreg_b32 to s_denorm_mode/s_round_mode
2020-05-29 21:11:36 -04:00
SIFixSGPRCopies.cpp
[AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate
2020-05-28 19:25:51 +03:00
SIFixupVectorISel.cpp
AMDGPU/GlobalISel: Skip DAG hack passes on selected functions
2020-02-17 08:33:17 -08:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
[AMDGPU] Extend constant folding for logical operations
2020-04-07 14:37:16 -04:00
SIFormMemoryClauses.cpp
…
SIFrameLowering.cpp
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
SIFrameLowering.h
For PAL, make sure Scratch Buffer Descriptor do not clobber GIT pointer
2020-05-06 10:31:15 -04:00
SIInsertHardClauses.cpp
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
2020-06-01 22:52:34 +05:30
SIInsertSkips.cpp
[AMDGPU] Add SIPreEmitPeephole pass.
2020-03-25 15:35:35 +00:00
SIInsertWaitcnts.cpp
[AMDGPU] Fix wait counts in the presence of 16bit subregisters
2020-05-26 12:19:27 +03:00
SIInstrFormats.td
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
SIInstrInfo.cpp
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
SIInstrInfo.h
[AMDGPU/MemOpsCluster] Code clean-up around accessing of memory operand width
2020-06-03 14:03:52 +05:30
SIInstrInfo.td
AMDGPU: Add intrinsic for s_setreg
2020-05-28 14:26:38 -04:00
SIInstructions.td
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
SIISelLowering.cpp
[amdgpu] Skip OR combining on 64-bit integer before legalizing ops.
2020-06-12 15:22:38 -04:00
SIISelLowering.h
[AMDGPU] Custom lowering of i64 umulo/smulo
2020-06-08 23:14:19 -07:00
SILoadStoreOptimizer.cpp
AMDGPU: Break read2/write2 search range on a memory fence
2020-04-24 15:53:30 -04:00
SILowerControlFlow.cpp
[AMDGPU] Limit endcf-collapase to simple if
2020-04-07 10:27:23 -07:00
SILowerI1Copies.cpp
AMDGPU/GlobalISel: Skip DAG hack passes on selected functions
2020-02-17 08:33:17 -08:00
SILowerSGPRSpills.cpp
[AMDGPU] Reserving VGPR for future SGPR Spill
2020-05-12 00:33:00 +00:00
SIMachineFunctionInfo.cpp
[AMDGPU] Remove assertion on S1024 SGPR to VGPR spill
2020-05-30 11:16:19 +09:00
SIMachineFunctionInfo.h
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
SIMachineScheduler.cpp
[AMDGPU] Use generated RegisterPressureSets enum
2020-02-18 10:34:03 -08:00
SIMachineScheduler.h
[AMDGPU] Use generated RegisterPressureSets enum
2020-02-18 10:34:03 -08:00
SIMemoryLegalizer.cpp
[AMDGPU] Skip generating cache invalidating instructions on AMDPAL
2020-04-24 13:53:44 +02:00
SIModeRegister.cpp
…
SIOptimizeExecMasking.cpp
AMDGPU: Use Register
2019-12-27 16:53:21 -05:00
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] Don't assert on partial exec copy
2020-04-12 21:14:36 -07:00
SIPeepholeSDWA.cpp
AMDGPU: Fix dropping MI flags when rewriting instructions
2020-05-27 13:27:06 -04:00
SIPostRABundler.cpp
[AMDGPU] Drop const for value that is copied (NFC).
2020-03-30 10:59:59 +01:00
SIPreAllocateWWMRegs.cpp
…
SIPreEmitPeephole.cpp
[AMDGPU] Process V_MOV_B32_indirect in SET_GPR_IDX optimization
2020-05-19 21:37:14 -07:00
SIProgramInfo.h
…
SIRegisterInfo.cpp
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
SIRegisterInfo.h
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
SIRegisterInfo.td
AMDGPU: Define mode register
2020-05-23 13:24:42 -04:00
SIRemoveShortExecBranches.cpp
[AMDGPU] Don't remove short branches over kills
2020-02-03 09:26:52 +00:00
SISchedule.td
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
SIShrinkInstructions.cpp
AMDGPU: Use early return
2020-04-07 13:48:00 -04:00
SIWholeQuadMode.cpp
[AMDGPU] Fix whole wavefront mode
2020-03-17 17:23:23 +01:00
SMInstructions.td
AMDGPU/GlobalISel: Fix select of <8 x s64> scalar load
2020-06-11 19:09:43 -04:00
SOPInstructions.td
AMDGPU: Don't run indexing mode switches with exec = 0
2020-06-02 13:47:48 -04:00
VIInstrFormats.td
…
VOP1Instructions.td
AMDGPU: Set mayRaiseFPException
2020-06-04 17:35:27 -04:00
VOP2Instructions.td
AMDGPU: Select strict_fmul
2020-06-04 17:49:00 -04:00
VOP3Instructions.td
AMDGPU: Select strict_fma
2020-06-04 17:49:00 -04:00
VOP3PInstructions.td
AMDGPU: Select strict_fmul
2020-06-04 17:49:00 -04:00
VOPCInstructions.td
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
VOPInstructions.td
AMDGPU: Set mayRaiseFPException
2020-06-04 17:35:27 -04:00