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35939a70f0
llvm-mirror/lib/Target/AMDGPU
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Daniel Sanders 35939a70f0 [globalisel] Make LegalizerInfo::LegalizeAction available outside of LegalizerInfo. NFC 
Summary:
The improvements to the LegalizerInfo discussed in D42244 require that
LegalizerInfo::LegalizeAction be available for use in other classes. As such,
it needs to be moved out of LegalizerInfo. This has been done separately to the
next patch to minimize the noise in that patch.

llvm-svn: 323669
2018-01-29 17:37:29 +00:00
..
AsmParser [AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16 2018-01-29 14:20:42 +00:00
Disassembler [AMDGPU][MC] Added support of 64-bit image atomics 2018-01-26 15:43:29 +00:00
InstPrinter [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32 2018-01-15 18:49:15 +00:00
MCTargetDesc [AMDGPU][MC][GFX9] Enable inline constants for SDWA operands 2018-01-17 14:00:48 +00:00
TargetInfo Add backend name to Target to enable runtime info to be fed back into TableGen 2017-11-15 23:55:44 +00:00
Utils [AMDGPU][MC] Added support of 64-bit image atomics 2018-01-26 15:43:29 +00:00
AMDGPU.h [AMDGPU] Clean up symbols in the global namespace. 2017-10-31 23:21:30 +00:00
AMDGPU.td AMDGPU/SI: Add d16 support for buffer intrinsics. 2018-01-12 21:12:19 +00:00
AMDGPUAliasAnalysis.cpp [AMDGPU] calling conventions for AMDPAL OS type 2017-09-29 09:51:22 +00:00
AMDGPUAliasAnalysis.h
AMDGPUAlwaysInlinePass.cpp AMDGPU: Add option to stress calls 2017-09-21 07:00:48 +00:00
AMDGPUAnnotateKernelFeatures.cpp [Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC). 2017-08-31 21:56:16 +00:00
AMDGPUAnnotateUniformValues.cpp
AMDGPUArgumentUsageInfo.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
AMDGPUArgumentUsageInfo.h
AMDGPUAsmPrinter.cpp [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support 2018-01-10 14:22:19 +00:00
AMDGPUAsmPrinter.h [AMDGPU] add labels to +DumpCode output 2017-12-08 14:09:34 +00:00
AMDGPUCallingConv.td
AMDGPUCallLowering.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AMDGPUCallLowering.h
AMDGPUCodeGenPrepare.cpp [IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag 2017-11-06 16:27:15 +00:00
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h Move TargetFrameLowering.h to CodeGen where it's implemented 2017-11-03 22:32:11 +00:00
AMDGPUGenRegisterBankInfo.def
AMDGPUInline.cpp [AMDGPU] Port of HSAIL inliner 2017-09-20 04:25:58 +00:00
AMDGPUInstrInfo.cpp AMDGPU/SI: Add d16 support for buffer intrinsics. 2018-01-12 21:12:19 +00:00
AMDGPUInstrInfo.h AMDGPU: Partially fix disassembly of MIMG instructions 2017-12-13 21:07:51 +00:00
AMDGPUInstrInfo.td Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ. 2017-10-12 19:37:14 +00:00
AMDGPUInstructions.td AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction 2017-12-04 23:07:28 +00:00
AMDGPUInstructionSelector.cpp [GISel] Make constrainSelectedInstRegOperands() available to the legalizer. NFC 2018-01-17 19:31:33 +00:00
AMDGPUInstructionSelector.h [globalisel][tablegen] Generate rule coverage and use it to identify untested rules 2017-11-16 00:46:35 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp [AMDGPU] add LDS f32 intrinsics 2018-01-17 14:05:05 +00:00
AMDGPUISelLowering.cpp [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
AMDGPUISelLowering.h AMDGPU/SI: Add d16 support for image intrinsics. 2018-01-18 22:08:53 +00:00
AMDGPULegalizerInfo.cpp [globalisel] Make LegalizerInfo::LegalizeAction available outside of LegalizerInfo. NFC 2018-01-29 17:37:29 +00:00
AMDGPULegalizerInfo.h
AMDGPULibCalls.cpp Make helpers static. NFC. 2017-11-24 14:55:41 +00:00
AMDGPULibFunc.cpp [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc 2017-11-04 17:37:43 +00:00
AMDGPULibFunc.h [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc 2017-11-04 17:37:43 +00:00
AMDGPULowerIntrinsics.cpp
AMDGPUMachineCFGStructurizer.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
AMDGPUMachineFunction.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AMDGPUMachineFunction.h
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h AMDGPU: Handle more than one memory operand in SIMemoryLegalizer 2017-09-07 16:14:21 +00:00
AMDGPUMacroFusion.cpp
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AMDGPUMCInstLower.h
AMDGPUOpenCLEnqueuedBlockLowering.cpp AMDGPU: Fix set but not used warnings related to AMDGPUAS 2017-11-01 19:12:38 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp
AMDGPUPromoteAlloca.cpp AMDGPU: Fix assert on alloca of array of struct 2017-09-14 18:02:29 +00:00
AMDGPUPTNote.h AMDGPU/NFC: Move AMDGPU specific note types to ELF.h 2017-10-12 18:59:54 +00:00
AMDGPURegAsmNames.inc.cpp
AMDGPURegisterBankInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AMDGPURegisterBankInfo.h
AMDGPURegisterBanks.td
AMDGPURegisterInfo.cpp [AMDGPU] Make sure all super regs of reserved regs are marked reserved. 2018-01-24 18:09:53 +00:00
AMDGPURegisterInfo.h [AMDGPU] Make sure all super regs of reserved regs are marked reserved. 2018-01-24 18:09:53 +00:00
AMDGPURegisterInfo.td
AMDGPURewriteOutArguments.cpp
AMDGPUSubtarget.cpp AMDGPU/SI: Add d16 support for buffer intrinsics. 2018-01-12 21:12:19 +00:00
AMDGPUSubtarget.h AMDGPU/SI: Add d16 support for buffer intrinsics. 2018-01-12 21:12:19 +00:00
AMDGPUTargetMachine.cpp [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
AMDGPUTargetMachine.h (Re-landing) Expose a TargetMachine::getTargetTransformInfo function 2017-12-22 18:21:59 +00:00
AMDGPUTargetObjectFile.cpp AMDGPU: Fix set but not used warnings related to AMDGPUAS 2017-11-01 19:12:38 +00:00
AMDGPUTargetObjectFile.h
AMDGPUTargetTransformInfo.cpp [AMDGPU] fix LDS f32 intrinsics 2018-01-26 11:09:38 +00:00
AMDGPUTargetTransformInfo.h LSR: Check more intrinsic pointer operands 2017-12-11 21:38:43 +00:00
AMDGPUUnifyDivergentExitNodes.cpp [Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-10-17 21:27:42 +00:00
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AMDKernelCodeT.h
BUFInstructions.td AMDGPU/SI: Fix typos in d16 support patch the buffer intrinsics. 2018-01-18 22:57:57 +00:00
CaymanInstructions.td [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
CMakeLists.txt AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental) 2017-11-20 14:35:53 +00:00
DSInstructions.td [AMDGPU] add LDS f32 intrinsics 2018-01-17 14:05:05 +00:00
EvergreenInstructions.td [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
FLATInstructions.td [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes 2017-11-27 17:14:35 +00:00
GCNHazardRecognizer.cpp [AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards(). 2017-12-07 20:34:25 +00:00
GCNHazardRecognizer.h [AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards(). 2017-12-07 20:34:25 +00:00
GCNILPSched.cpp AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental) 2017-11-20 14:35:53 +00:00
GCNIterativeScheduler.cpp [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
GCNIterativeScheduler.h AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental) 2017-11-20 14:35:53 +00:00
GCNMinRegStrategy.cpp
GCNProcessors.td AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
GCNRegPressure.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
GCNRegPressure.h Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
GCNSchedStrategy.cpp [NFC] fix trivial typos in comments 2018-01-22 05:54:46 +00:00
GCNSchedStrategy.h
LLVMBuild.txt
MIMGInstructions.td [AMDGPU][MC] Added support of 64-bit image atomics 2018-01-26 15:43:29 +00:00
R600ClauseMergePass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
R600ControlFlowFinalizer.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td AMDGPU: Remove global isGCN predicates 2017-10-03 00:06:41 +00:00
R600InstrInfo.cpp [AMDGPU] Make sure all super regs of reserved regs are marked reserved. 2018-01-24 18:09:53 +00:00
R600InstrInfo.h [AMDGPU] Make sure all super regs of reserved regs are marked reserved. 2018-01-24 18:09:53 +00:00
R600Instructions.td AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction 2017-12-04 23:07:28 +00:00
R600Intrinsics.td
R600ISelLowering.cpp AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction 2017-12-04 23:07:28 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
R600Packetizer.cpp
R600Processors.td AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction 2017-12-04 23:07:28 +00:00
R600RegisterInfo.cpp [AMDGPU] Make sure all super regs of reserved regs are marked reserved. 2018-01-24 18:09:53 +00:00
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R700Instructions.td
SIAnnotateControlFlow.cpp AMDGPU: Error in SIAnnotateControlFlow instead of assert 2018-01-17 16:30:01 +00:00
SIDebuggerInsertNops.cpp
SIDefines.h AMDGPU/SI: Add d16 support for image intrinsics. 2018-01-18 22:08:53 +00:00
SIFixSGPRCopies.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
SIFixVGPRCopies.cpp
SIFixWWMLiveness.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
SIFoldOperands.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIFrameLowering.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIFrameLowering.h [AMDGPU] AMDPAL scratch buffer support 2017-09-29 09:49:35 +00:00
SIInsertSkips.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIInsertWaitcnts.cpp [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
SIInsertWaits.cpp [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
SIInstrFormats.td AMDGPU/SI: Add d16 support for image intrinsics. 2018-01-18 22:08:53 +00:00
SIInstrInfo.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIInstrInfo.h [NFC] fix trivial typos in comments 2018-01-24 05:04:35 +00:00
SIInstrInfo.td [AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16 2018-01-29 14:20:42 +00:00
SIInstructions.td AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
SIIntrinsics.td
SIISelLowering.cpp [AMDGPU] fix LDS f32 intrinsics 2018-01-26 11:09:38 +00:00
SIISelLowering.h AMDGPU/SI: Add d16 support for buffer intrinsics. 2018-01-12 21:12:19 +00:00
SILoadStoreOptimizer.cpp [AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64 2018-01-22 21:46:43 +00:00
SILowerControlFlow.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
SILowerI1Copies.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
SIMachineFunctionInfo.cpp AMDGPU: Use unique PSVs for buffer resources 2017-12-29 17:18:21 +00:00
SIMachineFunctionInfo.h [AMDGPU] stop image_store being moved illegally 2018-01-12 22:57:24 +00:00
SIMachineScheduler.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
SIMachineScheduler.h
SIMemoryLegalizer.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIOptimizeExecMasking.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIOptimizeExecMaskingPreRA.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIPeepholeSDWA.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIRegisterInfo.cpp [AMDGPU] Make sure all super regs of reserved regs are marked reserved. 2018-01-24 18:09:53 +00:00
SIRegisterInfo.h [AMDGPU] Make sure all super regs of reserved regs are marked reserved. 2018-01-24 18:09:53 +00:00
SIRegisterInfo.td [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support 2018-01-10 14:22:19 +00:00
SISchedule.td
SIShrinkInstructions.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SIWholeQuadMode.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
SMInstructions.td AMDGPU: Set IntrReadMem on memtime intrinsics 2017-12-08 20:01:02 +00:00
SOPInstructions.td AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic 2017-10-24 10:26:59 +00:00
VIInstrFormats.td
VIInstructions.td
VOP1Instructions.td [AMDGPU] Copy impdefs from pseudo to real instructions 2018-01-15 17:55:35 +00:00
VOP2Instructions.td [AMDGPU] Copy impdefs from pseudo to real instructions 2018-01-15 17:55:35 +00:00
VOP3Instructions.td [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16 2017-11-24 15:37:14 +00:00
VOP3PInstructions.td AMDGPU: Add max-mix-insts subtarget feature 2017-10-25 07:00:51 +00:00
VOPCInstructions.td [AMDGPU] Copy impdefs from pseudo to real instructions 2018-01-15 17:55:35 +00:00
VOPInstructions.td [AMDGPU] Copy impdefs from pseudo to real instructions 2018-01-15 17:55:35 +00:00