mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 02:52:53 +02:00
47f4c40e25
This is a long-awaited follow-up suggested in D33578. Since then, we've picked up even more opportunities for vector narrowing from changes like D53784, so there are a lot of test diffs. Apart from 2-3 strange cases, these are all wins. I've structured this to be no-functional-change-intended for any target except for x86 because I couldn't tell if AArch64, ARM, and AMDGPU would improve or not. All of those targets have existing regression tests (4, 4, 10 files respectively) that would be affected. Also, Hexagon overrides the shouldReduceLoadWidth() hook, but doesn't show any regression test diffs. The trade-off is deciding if an extra vector load is better than a single wide load + extract_subvector. For x86, this is almost always better (on paper at least) because we often can fold loads into subsequent ops and not increase the official instruction count. There's also some unknown -- but potentially large -- benefit from using narrower vector ops if wide ops are implemented with multiple uops and/or frequency throttling is avoided. Differential Revision: https://reviews.llvm.org/D54073 llvm-svn: 346595 |
||
|---|---|---|
| .. | ||
| AsmParser | ||
| Disassembler | ||
| InstPrinter | ||
| MCTargetDesc | ||
| TargetInfo | ||
| Utils | ||
| AArch64.h | ||
| AArch64.td | ||
| AArch64A53Fix835769.cpp | ||
| AArch64A57FPLoadBalancing.cpp | ||
| AArch64AdvSIMDScalarPass.cpp | ||
| AArch64AsmPrinter.cpp | ||
| AArch64BranchTargets.cpp | ||
| AArch64CallingConvention.h | ||
| AArch64CallingConvention.td | ||
| AArch64CallLowering.cpp | ||
| AArch64CallLowering.h | ||
| AArch64CleanupLocalDynamicTLSPass.cpp | ||
| AArch64CollectLOH.cpp | ||
| AArch64CompressJumpTables.cpp | ||
| AArch64CondBrTuning.cpp | ||
| AArch64ConditionalCompares.cpp | ||
| AArch64ConditionOptimizer.cpp | ||
| AArch64DeadRegisterDefinitionsPass.cpp | ||
| AArch64ExpandPseudoInsts.cpp | ||
| AArch64FalkorHWPFFix.cpp | ||
| AArch64FastISel.cpp | ||
| AArch64FrameLowering.cpp | ||
| AArch64FrameLowering.h | ||
| AArch64GenRegisterBankInfo.def | ||
| AArch64InstrAtomics.td | ||
| AArch64InstrFormats.td | ||
| AArch64InstrInfo.cpp | ||
| AArch64InstrInfo.h | ||
| AArch64InstrInfo.td | ||
| AArch64InstructionSelector.cpp | ||
| AArch64ISelDAGToDAG.cpp | ||
| AArch64ISelLowering.cpp | ||
| AArch64ISelLowering.h | ||
| AArch64LegalizerInfo.cpp | ||
| AArch64LegalizerInfo.h | ||
| AArch64LoadStoreOptimizer.cpp | ||
| AArch64MachineFunctionInfo.h | ||
| AArch64MacroFusion.cpp | ||
| AArch64MacroFusion.h | ||
| AArch64MCInstLower.cpp | ||
| AArch64MCInstLower.h | ||
| AArch64PBQPRegAlloc.cpp | ||
| AArch64PBQPRegAlloc.h | ||
| AArch64PerfectShuffle.h | ||
| AArch64PfmCounters.td | ||
| AArch64PreLegalizerCombiner.cpp | ||
| AArch64PromoteConstant.cpp | ||
| AArch64RedundantCopyElimination.cpp | ||
| AArch64RegisterBankInfo.cpp | ||
| AArch64RegisterBankInfo.h | ||
| AArch64RegisterBanks.td | ||
| AArch64RegisterInfo.cpp | ||
| AArch64RegisterInfo.h | ||
| AArch64RegisterInfo.td | ||
| AArch64SchedA53.td | ||
| AArch64SchedA57.td | ||
| AArch64SchedA57WriteRes.td | ||
| AArch64SchedCyclone.td | ||
| AArch64SchedExynosM1.td | ||
| AArch64SchedExynosM3.td | ||
| AArch64SchedFalkor.td | ||
| AArch64SchedFalkorDetails.td | ||
| AArch64SchedKryo.td | ||
| AArch64SchedKryoDetails.td | ||
| AArch64SchedThunderX2T99.td | ||
| AArch64SchedThunderX.td | ||
| AArch64Schedule.td | ||
| AArch64SelectionDAGInfo.cpp | ||
| AArch64SelectionDAGInfo.h | ||
| AArch64SIMDInstrOpt.cpp | ||
| AArch64StorePairSuppress.cpp | ||
| AArch64Subtarget.cpp | ||
| AArch64Subtarget.h | ||
| AArch64SVEInstrInfo.td | ||
| AArch64SystemOperands.td | ||
| AArch64TargetMachine.cpp | ||
| AArch64TargetMachine.h | ||
| AArch64TargetObjectFile.cpp | ||
| AArch64TargetObjectFile.h | ||
| AArch64TargetTransformInfo.cpp | ||
| AArch64TargetTransformInfo.h | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| SVEInstrFormats.td | ||