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AsmParser
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Upgrade MC to v0.9.
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2020-08-01 07:42:06 +08:00 |
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Disassembler
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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MCTargetDesc
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[RISCV] Enable MCCodeEmitter instruction predicate verifier
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2020-08-20 18:36:54 +01:00 |
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TargetInfo
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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Utils
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[RISCV] Support Shadow Call Stack
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2020-09-17 16:02:35 -07:00 |
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CMakeLists.txt
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[RISCV] Split the pseudo instruction splitting pass
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2020-06-29 14:35:57 +01:00 |
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LLVMBuild.txt
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RISCV.h
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[RISCV] Split the pseudo instruction splitting pass
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2020-06-29 14:35:57 +01:00 |
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RISCV.td
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[RISCV] Use the extensions in the canonical order (NFC)
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2020-09-29 20:03:02 -05:00 |
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RISCVAsmPrinter.cpp
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[RISCV] ELF attribute section for RISC-V.
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2020-03-31 16:16:19 +08:00 |
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RISCVCallingConv.td
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVExpandAtomicPseudoInsts.cpp
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[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
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2020-07-15 10:50:55 +01:00 |
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RISCVExpandPseudoInsts.cpp
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[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
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2020-07-15 10:50:55 +01:00 |
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RISCVFrameLowering.cpp
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[RISCV] Support Shadow Call Stack
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2020-09-17 16:02:35 -07:00 |
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RISCVFrameLowering.h
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CodeGen: Use Register in TargetFrameLowering
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2020-04-07 17:07:44 -04:00 |
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RISCVInstrFormats.td
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Upgrade MC to v0.9.
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2020-08-01 07:42:06 +08:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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[RISCV] add the MC layer support of riscv vector Zvamo extension
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2020-08-27 14:11:38 +08:00 |
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RISCVInstrInfo.cpp
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[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
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2020-09-21 10:21:11 +01:00 |
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RISCVInstrInfo.h
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[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
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2020-09-21 10:21:11 +01:00 |
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RISCVInstrInfo.td
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[RISCV] Do not mandate scheduling for CSR instructions
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2020-09-21 18:24:53 -05:00 |
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RISCVInstrInfoA.td
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RISCV: Avoid GlobalISel build break in a future patch
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2020-07-13 14:01:57 -04:00 |
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RISCVInstrInfoB.td
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[SelectionDAG] Better legalization for FSHL and FSHR
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2020-08-21 10:32:49 +01:00 |
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RISCVInstrInfoC.td
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[RISC-V] Mark C_MV as a move instruction
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2020-08-27 10:32:23 +01:00 |
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RISCVInstrInfoD.td
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[RISCV] Add patterns for checking isnan
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2020-05-02 15:01:04 +01:00 |
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RISCVInstrInfoF.td
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[RISCV] Add patterns for checking isnan
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2020-05-02 15:01:04 +01:00 |
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RISCVInstrInfoM.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrInfoV.td
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[RISCV] add the MC layer support of riscv vector Zvamo extension
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2020-08-27 14:11:38 +08:00 |
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RISCVInstructionSelector.cpp
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RISCV: Avoid GlobalISel build break in a future patch
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2020-07-13 14:01:57 -04:00 |
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RISCVISelDAGToDAG.cpp
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[SelectionDAG] Better legalization for FSHL and FSHR
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2020-08-21 10:32:49 +01:00 |
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RISCVISelDAGToDAG.h
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[SelectionDAG] Better legalization for FSHL and FSHR
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2020-08-21 10:32:49 +01:00 |
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RISCVISelLowering.cpp
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[RISCV] eliminate the repetition declare of SDLoc DL
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2020-08-03 10:24:30 +08:00 |
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RISCVISelLowering.h
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[RISCV] Optimize multiplication by constant
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2020-07-07 18:50:24 -07:00 |
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
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2020-07-01 07:28:11 +00:00 |
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RISCVMCInstLower.cpp
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Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
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2020-07-14 11:15:01 +01:00 |
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RISCVMergeBaseOffset.cpp
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[NFC][RISCV] Simplify pass arg of RISCVMergeBaseOffsetOpt
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2020-09-03 20:01:23 +08:00 |
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RISCVRegisterBankInfo.cpp
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Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
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2020-03-20 11:02:50 +01:00 |
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RISCVRegisterBankInfo.h
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Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
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2020-03-20 11:02:50 +01:00 |
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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RISCV: Don't store function in RISCVMachineFunctionInfo
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2020-06-30 16:08:51 -04:00 |
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RISCVRegisterInfo.h
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CodeGen: More conversions to use Register
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2020-04-07 18:54:36 -04:00 |
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RISCVRegisterInfo.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVSchedBullet.td
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[RISCV] Scheduler description for Bullet
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2020-09-25 18:36:53 -05:00 |
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RISCVSchedRocket.td
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[RISCV] Fix formatting (NFC)
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2020-09-25 18:15:04 -05:00 |
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RISCVSchedule.td
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[RISCV] Fix formatting (NFC)
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2020-09-25 18:15:04 -05:00 |
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RISCVSubtarget.cpp
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[X86][MC][Target] Initial backend support a tune CPU to support -mtune
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2020-08-14 15:31:50 -07:00 |
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RISCVSubtarget.h
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[RISCV] add the MC layer support of riscv vector Zvamo extension
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2020-08-27 14:11:38 +08:00 |
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RISCVSystemOperands.td
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[RISCV] Enable the use of the old mucounteren name
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2020-08-17 13:11:49 +01:00 |
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RISCVTargetMachine.cpp
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[GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator.
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2020-09-09 14:31:12 -07:00 |
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RISCVTargetMachine.h
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[RISCV] Add subtargets initialized with target feature
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2019-12-17 09:34:01 -08:00 |
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RISCVTargetObjectFile.cpp
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[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
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2020-05-21 15:23:29 -07:00 |
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RISCVTargetObjectFile.h
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[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
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2020-05-21 15:23:29 -07:00 |
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RISCVTargetTransformInfo.cpp
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[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
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2020-09-22 11:54:10 +00:00 |
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RISCVTargetTransformInfo.h
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[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
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2020-09-22 11:54:10 +00:00 |
