..
GlobalISel
intrinsics
rvv
[RISCV] Permit larger RVV stacks and stack offsets
2021-06-25 07:17:33 +01:00
add-before-shl.ll
add-imm.ll
[RISCV] Optimize addition with immediate
2021-04-26 13:26:17 +08:00
addc-adde-sube-subc.ll
addcarry.ll
addimm-mulimm.ll
addrspacecast.ll
align.ll
alloca.ll
alu8.ll
alu16.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
alu32.ll
[RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffffffff).
2021-03-25 09:03:25 -07:00
alu64.ll
analyze-branch.ll
arith-with-overflow.ll
atomic-cmpxchg-flag.ll
atomic-cmpxchg.ll
[AtomicExpand] Merge cmpxchg success and failure ordering when appropriate.
2021-06-03 11:34:35 -07:00
atomic-fence.ll
atomic-load-store.ll
atomic-rmw.ll
atomic-signext.ll
[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics
2021-05-20 20:34:23 +01:00
attributes.ll
[RISCV] Update the version number to v0.10 for vector.
2021-01-30 07:20:05 +08:00
blockaddress.ll
branch-relaxation.ll
branch.ll
[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
2021-03-15 11:32:43 -07:00
bswap-ctlz-cttz-ctpop.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
byval.ll
callee-saved-fpr32s.ll
callee-saved-fpr64s.ll
callee-saved-gprs.ll
calling-conv-half.ll
[RISCV] Improve 64-bit integer constant materialization for more cases.
2021-04-02 10:18:08 -07:00
calling-conv-ilp32-ilp32f-common.ll
calling-conv-ilp32-ilp32f-ilp32d-common.ll
calling-conv-ilp32.ll
calling-conv-ilp32d.ll
calling-conv-ilp32f-ilp32d-common.ll
calling-conv-lp64-lp64f-common.ll
calling-conv-lp64-lp64f-lp64d-common.ll
calling-conv-lp64.ll
calling-conv-rv32f-ilp32.ll
calling-conv-sext-zext.ll
calls.ll
cmp-bool.ll
codemodel-lowering.ll
compress-float.ll
compress-inline-asm.ll
compress.ll
copy-frameindex.mir
copysign-casts.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
disable-tail-calls.ll
disjoint.ll
div.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
double-arith.ll
double-bitmanip-dagcombines.ll
[RISCV] Improve 64-bit integer materialization for some cases.
2021-04-01 09:12:52 -07:00
double-br-fcmp.ll
double-calling-conv.ll
double-convert.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
double-fcmp.ll
double-frem.ll
double-imm.ll
double-intrinsics.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
double-isnan.ll
double-mem.ll
double-previous-failure.ll
double-select-fcmp.ll
double-stack-spill-restore.ll
dwarf-eh.ll
elf-preemption.ll
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-11 11:29:45 -07:00
exception-pointer-register.ll
fastcc-float.ll
fastcc-int.ll
fixups-diff.ll
test: clean up some of the RISCV tests (NFC)
2021-06-17 09:51:09 -07:00
fixups-relax-diff.ll
test: clean up some of the RISCV tests (NFC)
2021-06-17 09:51:09 -07:00
float-arith.ll
float-bit-preserving-dagcombines.ll
[RISCV] Improve 64-bit integer materialization for some cases.
2021-04-01 09:12:52 -07:00
float-bitmanip-dagcombines.ll
float-br-fcmp.ll
float-convert.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
float-fcmp.ll
float-frem.ll
float-imm.ll
float-intrinsics.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
float-isnan.ll
float-mem.ll
float-select-fcmp.ll
flt-rounds.ll
fold-addi-loadstore.ll
fp16-promote.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
fp128.ll
fp-imm.ll
fpenv.ll
[RISCV] Custom lowering of SET_ROUNDING
2021-04-22 15:04:55 +07:00
frame-info.ll
frame.ll
frameaddr-returnaddr.ll
get-register-invalid.ll
get-register-noreserve.ll
get-register-reserve.ll
get-setcc-result-type.ll
ghccc-rv32.ll
ghccc-rv64.ll
half-arith.ll
half-bitmanip-dagcombines.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
half-br-fcmp.ll
half-convert.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
half-fcmp.ll
half-imm.ll
half-intrinsics.ll
half-isnan.ll
half-mem.ll
half-select-fcmp.ll
hoist-global-addr-base.ll
[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
2021-03-15 11:32:43 -07:00
i32-icmp.ll
imm-cse.ll
imm.ll
[RISCV] Improve 64-bit integer constant materialization for more cases.
2021-04-02 10:18:08 -07:00
indirectbr.ll
init-array.ll
inline-asm-abi-names.ll
inline-asm-clobbers.ll
inline-asm-d-abi-names.ll
inline-asm-d-constraint-f.ll
inline-asm-f-abi-names.ll
inline-asm-f-constraint-f.ll
inline-asm-i-constraint-i1.ll
inline-asm-invalid.ll
inline-asm.ll
interrupt-attr-args-error.ll
interrupt-attr-callee.ll
interrupt-attr-invalid.ll
interrupt-attr-nocall.ll
interrupt-attr-ret-error.ll
interrupt-attr.ll
jumptable.ll
[CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt.
2021-06-23 15:38:11 -07:00
large-stack.ll
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
legalize-fneg.ll
lit.local.cfg
lsr-legaladdimm.ll
machineoutliner.mir
mattr-invalid-combination.ll
mem64.ll
mem.ll
mir-target-flags.ll
module-target-abi2.ll
module-target-abi.ll
mul.ll
[RISCV] Add custom type legalization to form MULHSU when possible.
2021-04-01 10:15:55 -07:00
musttail-call.ll
neg-abs.ll
nomerge.ll
option-nopic.ll
option-norelax.ll
option-norvc.ll
option-pic.ll
option-relax.ll
option-rvc.ll
out-of-reach-emergency-slot.mir
patchable-function-entry.ll
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"
2021-05-29 15:11:37 +01:00
pic-models.ll
pr40333.ll
prefetch.ll
readcyclecounter.ll
rem.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
remat.ll
reserved-reg-errors.ll
reserved-regs.ll
rotl-rotr.ll
rv32e.ll
rv32i-rv64i-float-double.ll
rv32i-rv64i-half.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
rv32zba.ll
[RISCV] Optimize add-mul in the zba extension with SH*ADD
2021-06-19 14:33:27 +08:00
rv32zbb-intrinsic.ll
Recommit "[RISCV] Add IR intrinsic for Zbb extension"
2021-04-02 11:50:19 -07:00
rv32zbb-zbp.ll
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
2021-04-29 09:43:51 -07:00
rv32zbb.ll
[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
2021-03-22 19:17:04 -07:00
rv32zbc-intrinsic.ll
[RISCV] Add IR intrinsics for Zbc extension
2021-04-02 12:09:13 -07:00
rv32zbe-intrinsic.ll
[RISCV] [1/2] Add IR intrinsic for Zbe extension
2021-04-25 19:14:34 -07:00
rv32zbp-intrinsic.ll
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
2021-04-25 21:54:06 -07:00
rv32zbp.ll
[RISCV] Lower i8/i16 bswap/bitreverse to grevi/greviw with Zbp.
2021-06-07 10:31:51 -07:00
rv32zbr.ll
[RISCV] Add IR intrinsic for Zbr extension
2021-04-02 10:58:45 -07:00
rv32zbs.ll
[RISCV] Optimize bitwise and with constant for the Zbs extension
2021-06-08 07:26:00 +08:00
rv32zbt.ll
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
2021-04-29 09:43:51 -07:00
rv64-large-stack.ll
rv64d-double-convert.ll
rv64f-float-convert.ll
rv64f-half-convert.ll
rv64i-complex-float.ll
rv64i-demanded-bits.ll
rv64i-double-softfloat.ll
rv64i-exhaustive-w-insts.ll
[RISCV] Optimize (and (shl GPR:, uimm5:), 0xffffffff) to use 2 shifts instead of 3.
2021-03-25 23:31:01 -07:00
rv64i-single-softfloat.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
rv64i-tricky-shifts.ll
rv64i-w-insts-legalization.ll
[RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64
2021-03-20 14:55:46 -07:00
rv64m-exhaustive-w-insts.ll
[RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.
2021-02-22 14:56:22 -08:00
rv64m-w-insts-legalization.ll
rv64zba.ll
[RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi.
2021-06-19 12:10:42 -07:00
rv64zbb-intrinsic.ll
[RISCV] Use gorciw for i32 orc.b intrinsic when Zbp is enabled.
2021-04-04 17:14:28 -07:00
rv64zbb-zbp.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
rv64zbb.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
rv64zbc-intrinsic.ll
[RISCV] Add IR intrinsics for Zbc extension
2021-04-02 12:09:13 -07:00
rv64zbe-intrinsic.ll
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
2021-04-25 21:54:06 -07:00
rv64zbp-intrinsic.ll
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
2021-04-25 21:54:06 -07:00
rv64zbp.ll
[RISCV] Lower i8/i16 bswap/bitreverse to grevi/greviw with Zbp.
2021-06-07 10:31:51 -07:00
rv64zbr.ll
[RISCV] Add IR intrinsic for Zbr extension
2021-04-02 10:58:45 -07:00
rv64zbs.ll
[RISCV] Optimize bitwise and with constant for the Zbs extension
2021-06-08 07:26:00 +08:00
rv64zbt.ll
[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
2021-03-22 19:17:04 -07:00
sadd_sat_plus.ll
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
2021-04-07 13:47:17 -07:00
sadd_sat.ll
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
2021-04-07 13:47:17 -07:00
saverestore.ll
[RISCV] Don't emit save-restore call if function is a interrupt handler
2021-04-16 12:54:47 +08:00
scalable-vector-struct.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
sdata-limit-0.ll
sdata-limit-4.ll
sdata-limit-8.ll
sdata-local-sym.ll
select-and.ll
select-bare.ll
select-binop-identity.ll
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
2021-04-29 09:43:51 -07:00
select-cc.ll
[RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X.
2021-03-12 11:50:10 -08:00
select-const.ll
select-optimize-multiple.ll
select-optimize-multiple.mir
select-or.ll
setcc-logic.ll
sext-zext-trunc.ll
shadowcallstack.ll
shift-masked-shamt.ll
shifts.ll
shrinkwrap.ll
spill-fpr-scalar.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
split-offsets.ll
split-sp-adjust.ll
srem-lkk.ll
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
2021-02-11 09:43:13 -08:00
srem-seteq-illegal-types.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
srem-vector-lkk.ll
[RISCV] Improve 64-bit integer materialization for some cases.
2021-04-01 09:12:52 -07:00
ssub_sat_plus.ll
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
2021-04-07 13:47:17 -07:00
ssub_sat.ll
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
2021-04-07 13:47:17 -07:00
stack-realignment-with-variable-sized-objects.ll
stack-realignment.ll
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
stack-slot-size.ll
[RISCV] Fix stack slot for argument types (Bug 49500)
2021-04-29 09:10:48 +01:00
stack-store-check.ll
subtarget-features-std-ext.ll
tail-calls.ll
target-abi-invalid.ll
target-abi-valid.ll
thread-pointer.ll
tls-models.ll
uadd_sat_plus.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
uadd_sat.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
umulo-128-legalisation-lowering.ll
urem-lkk.ll
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
2021-02-11 09:43:13 -08:00
urem-seteq-illegal-types.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
urem-vector-lkk.ll
usub_sat_plus.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
usub_sat.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
vararg.ll
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
vec3-setcc-crash.ll
vector-abi.ll
[RISCV] Fix stack slot for argument types (Bug 49500)
2021-04-29 09:10:48 +01:00
verify-instr.mir
wide-mem.ll
xaluo.ll
[RISCV] Add a pattern for (sext_inreg (mul (and X, 0xffffffff), (and Y, 0xffffffff)), i32) to suppress MULW formation
2021-03-27 15:37:18 -07:00
zext-with-load-is-free.ll
zfh-imm.ll
