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AsmParser
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[AArch64][AsmParser] Add rcpc support in .arch_extension
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2020-07-14 10:57:11 +01:00 |
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Disassembler
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[AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB
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2020-06-25 15:56:36 +01:00 |
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GISel
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AArch64: Use Register
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2020-07-22 14:14:44 -04:00 |
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MCTargetDesc
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[AArch64] Print the immediate operand for SPACE pseudo instruction
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2020-06-15 20:55:53 -07:00 |
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TargetInfo
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Utils
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AArch64.h
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[AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions.
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2020-06-12 07:34:33 +01:00 |
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AArch64.td
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[ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM
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2020-07-10 18:24:11 +01:00 |
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AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp
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[DebugInfo] Update MachineInstr to help support variadic DBG_VALUE instructions
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2020-06-22 16:01:12 +01:00 |
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AArch64BranchTargets.cpp
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[AArch64] Fix BTI instruction emission.
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2020-06-15 15:04:36 +02:00 |
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AArch64CallingConvention.cpp
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[Alignment][NFC] Use Align for TargetCallingConv::OrigAlign
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2020-06-25 13:21:22 +00:00 |
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AArch64CallingConvention.h
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AArch64CallingConvention.td
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[Alignment][NFC] Use Align for TargetCallingConv::OrigAlign
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2020-06-25 13:21:22 +00:00 |
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AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
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[AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg
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2020-06-01 16:00:55 -07:00 |
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AArch64Combine.td
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Revert "[AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy"
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2020-07-21 16:01:18 -07:00 |
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AArch64CompressJumpTables.cpp
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AArch64CondBrTuning.cpp
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[AArch64CondBrTuning] Ignore debug insts when scanning for NZCV clobbers [10/14]
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2020-04-22 17:03:40 -07:00 |
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AArch64ConditionalCompares.cpp
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DomTree: Remove getChildren() accessor
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2020-07-06 21:58:11 +02:00 |
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AArch64ConditionOptimizer.cpp
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MachineBasicBlock::updateTerminator now requires an explicit layout successor.
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2020-06-06 22:30:51 -04:00 |
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AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp
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[SVE] Fix invalid assert in expand_DestructiveOp.
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2020-07-04 09:21:40 +00:00 |
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AArch64FalkorHWPFFix.cpp
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AArch64FastISel.cpp
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AArch64: emit @llvm.debugtrap as brk #0xf000 on all platforms
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2020-07-20 10:31:26 +01:00 |
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AArch64FrameLowering.cpp
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[AArch64][SVE] Remove erroneous assert in resolveFrameOffsetReference
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2020-07-14 09:22:45 +01:00 |
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AArch64FrameLowering.h
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Call Frame Information (CFI) Handling for Basic Block Sections
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2020-07-14 12:54:12 -07:00 |
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AArch64GenRegisterBankInfo.def
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AArch64InstrAtomics.td
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AArch64InstrFormats.td
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[AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB
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2020-06-25 15:56:36 +01:00 |
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AArch64InstrGISel.td
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[AArch64][GlobalISel] Add G_EXT and select ext using it
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2020-06-15 12:20:59 -07:00 |
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AArch64InstrInfo.cpp
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[Target] As part of using inclusive language within the llvm project,
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2020-06-20 00:06:39 -07:00 |
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AArch64InstrInfo.h
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[AArch64][SVE] NFC: Rename isOrig -> isReverseInstr
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2020-07-02 17:01:15 +01:00 |
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AArch64InstrInfo.td
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[ARM] Generate [SU]HADD from ((a + b) >> 1)
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2020-07-21 13:22:07 +01:00 |
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AArch64ISelDAGToDAG.cpp
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[SVE] Custom ISel for fixed length extract/insert_subvector.
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2020-07-08 09:49:28 +00:00 |
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AArch64ISelLowering.cpp
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[ARM] Generate [SU]HADD from ((a + b) >> 1)
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2020-07-21 13:22:07 +01:00 |
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AArch64ISelLowering.h
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[ARM] Generate [SU]HADD from ((a + b) >> 1)
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2020-07-21 13:22:07 +01:00 |
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AArch64LoadStoreOptimizer.cpp
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[AArch64] Fix ldst-opt of multiple disjunct subregs.
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2020-06-08 20:18:24 +01:00 |
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AArch64MachineFunctionInfo.cpp
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MachineFunctionInfo for AArch64 in MIR
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2020-04-17 15:16:59 -07:00 |
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AArch64MachineFunctionInfo.h
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[MachineOutliner] Annotation for outlined functions in AArch64
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2020-04-20 13:33:31 -07:00 |
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AArch64MacroFusion.cpp
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AArch64MacroFusion.h
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AArch64MCInstLower.cpp
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AArch64MCInstLower.h
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PromoteConstant.cpp
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[AArch64] Don't promote constants with float ConstantExpr.
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2020-05-13 23:31:47 +01:00 |
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AArch64RedundantCopyElimination.cpp
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp
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[AArch64][SVE] Correctly allocate scavenging slot in presence of SVE.
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2020-07-22 10:50:36 +01:00 |
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AArch64RegisterInfo.h
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[AArch64] Provide Darwin variants of most calling conventions
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2020-05-20 16:03:48 -07:00 |
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AArch64RegisterInfo.td
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[AArch64][BFloat] basic AArch64 bfloat support
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2020-05-27 15:26:40 +01:00 |
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AArch64SchedA53.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedA57.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedExynosM3.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedExynosM4.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedExynosM5.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedFalkor.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedKryoDetails.td
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AArch64SchedPredExynos.td
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AArch64SchedPredicates.td
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AArch64SchedThunderX2T99.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedThunderX3T110.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64SchedThunderX.td
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[AARch64] Add Marvell ThunderX3T110 support
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2020-05-13 16:58:51 -07:00 |
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AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
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[Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align
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2020-06-30 12:46:26 +00:00 |
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AArch64SelectionDAGInfo.h
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[Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align
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2020-06-30 12:46:26 +00:00 |
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AArch64SIMDInstrOpt.cpp
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AArch64SLSHardening.cpp
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[NFC] Clean up uses of MachineModuleInfoWrapperPass
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2020-07-01 09:45:05 -07:00 |
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AArch64SpeculationHardening.cpp
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AArch64StackOffset.h
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AArch64StackTagging.cpp
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[SVE] Remove calls to VectorType::getNumElements from AArch64
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2020-06-30 11:17:50 -07:00 |
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AArch64StackTaggingPreRA.cpp
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AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp
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[ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM
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2020-07-10 18:24:11 +01:00 |
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AArch64Subtarget.h
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[ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM
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2020-07-10 18:24:11 +01:00 |
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AArch64SVEInstrInfo.td
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[AArch64][SVE] Add support for trunc to <vscale x N x i1>.
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2020-07-20 13:11:02 -07:00 |
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AArch64SystemOperands.td
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[AArch64] Remove inexistent system register ERXTS_EL1
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2020-04-29 16:43:48 +01:00 |
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AArch64TargetMachine.cpp
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Reland "[NFCI] createCFGSimplificationPass(): migrate to also take SimplifyCFGOptions"
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2020-07-16 13:40:01 +03:00 |
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AArch64TargetMachine.h
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MachineFunctionInfo for AArch64 in MIR
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2020-04-17 15:16:59 -07:00 |
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AArch64TargetObjectFile.cpp
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AArch64TargetObjectFile.h
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[llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation
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2020-06-10 11:34:16 -07:00 |
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AArch64TargetTransformInfo.cpp
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[NFC] Separate Peeling Properties into its own struct (re-land after minor fix)
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2020-07-10 18:39:30 +00:00 |
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AArch64TargetTransformInfo.h
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[NFC] Separate Peeling Properties into its own struct (re-land after minor fix)
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2020-07-10 18:39:30 +00:00 |
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CMakeLists.txt
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[AArch64] Introduce AArch64SLSHardeningPass, implementing hardening of RET and BR instructions.
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2020-06-11 07:51:17 +01:00 |
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LLVMBuild.txt
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SVEInstrFormats.td
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[SVE] Add lowering for scalable vector fadd, fdiv, fmul and fsub operations.
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2020-07-16 11:31:35 +00:00 |
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SVEIntrinsicOpts.cpp
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[SVEIntrinsicOpts] NFC: Remove unused isReinterpretFromBool for no-assert builds
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2020-04-21 09:49:22 +01:00 |
