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llvm-mirror/test/CodeGen/AMDGPU
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Tom Stellard c738ae1559 AMDGPU/SI: Fix threshold calculation for branching when exec is zero 
Summary:
When control flow is implemented using the exec mask, the compiler will
insert branch instructions to skip over the masked section when exec is
zero if the section contains more than a certain number of instructions.

The previous code would only count instructions in successor blocks,
and this patch modifies the code to start counting instructions in all
blocks between the start and end of the branch.

Reviewers: nhaehnle, arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18282

llvm-svn: 263969
2016-03-21 18:56:58 +00:00
..
32-bit-local-address-space.ll
add_i64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
add-debug.ll
add.ll
address-space.ll PeepholeOptimizer: Remove redundant copies 2015-09-25 20:22:12 +00:00
addrspacecast.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
and-gcn.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
and.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
annotate-kernel-features-hsa.ll AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr 2016-01-30 05:10:59 +00:00
annotate-kernel-features.ll AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr 2016-01-30 05:10:59 +00:00
anyext.ll
array-ptr-calc-i32.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
array-ptr-calc-i64.ll
atomic_cmp_swap_local.ll
atomic_load_add.ll
atomic_load_sub.ll
basic-branch.ll
basic-loop.ll
bfe_uint.ll
bfi_int.ll
bfm.ll AMDGPU: Remove bfi and bfm intrinsics 2016-02-08 19:06:01 +00:00
big_alu.ll AMDGPU: Replace some deprecated intrinsic uses in tests 2016-01-23 05:42:49 +00:00
bitcast.ll
bitreverse-inline-immediates.ll AMDGPU: Materialize sign bits with bfrev 2016-03-11 07:42:49 +00:00
bitreverse.ll AMDGPU: Use generic bitreverse intrinsic 2015-12-14 17:25:38 +00:00
bswap.ll
build_vector.ll
call_fs.ll
call.ll Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
calling-conventions.ll AMDGPU/SI: Remove calling convention assertion from LowerFormalArguments() 2015-10-06 21:16:34 +00:00
cayman-loop-bug.ll
cf_end.ll
cf-stack-bug.ll
cgp-addressing-modes-flat.ll AMDGPU: Implement isNoopAddrSpaceCast 2015-12-01 23:04:00 +00:00
cgp-addressing-modes.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
cgp-bitfield-extract.ll AMDGPU: Set HasExtractBitInsn 2016-03-01 04:58:17 +00:00
ci-use-flat-for-global.ll AMDGPU: Set flat_scratch from flat_scratch_init reg 2016-02-12 06:31:30 +00:00
coalescer_remat.ll
codegen-prepare-addrmode-sext.ll
combine_vloads.ll
commute_modifiers.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
commute-compares.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
commute-shifts.ll AMDGPU: Remove old sample intrinsics 2016-01-26 04:38:08 +00:00
complex-folding.ll
concat_vectors.ll
copy-illegal-type.ll
copy-to-reg.ll
ctlz_zero_undef.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
ctlz.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
ctpop64.ll AMDGPU: fix overlapping copies in copyPhysReg 2015-12-19 01:16:06 +00:00
ctpop.ll
cttz_zero_undef.ll
cube.ll AMDGPU: Add new amdgcn intrinsics for cube instructions 2016-01-26 04:29:56 +00:00
cvt_f32_ubyte.ll AMDGPU: Split x8 and x16 vector loads instead of scalarize 2015-11-24 12:05:03 +00:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dagcombine-reassociate-bug.ll DAGCombiner: Don't unnecessarily swap operands in ReassociateOps 2016-02-27 19:57:45 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
debug.ll
default-fp-mode.ll
disconnected-predset-break-bug.ll
dot4-folding.ll
drop-mem-operand-move-smrd.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
ds_read2_offset_order.ll
ds_read2_superreg.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
ds_read2.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
ds_read2st64.ll Update test case to appease bots after 263255. 2016-03-11 17:33:36 +00:00
ds_write2.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
ds_write2st64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
ds-negative-offset-addressing-mode-loop.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
ds-sub-offset.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
dynamic_stackalloc.ll Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
elf.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
elf.r600.ll
empty-function.ll
endcf-loop-header.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
extload-private.ll
extload.ll AMDGPU: Fix alignments in test 2016-02-22 21:04:23 +00:00
extract_vector_elt_i16.ll
extract-vector-elt-i8.ll AMDGPU: Make v32i8/v64i8 illegal types 2016-01-26 04:43:48 +00:00
extract-vector-elt-i64.ll AMDGPU: Make v2i64/v2f64 legal types. 2015-11-25 19:58:34 +00:00
extractelt-to-trunc.ll DAGCombiner: Make sure an integer is being truncated 2016-03-02 01:36:51 +00:00
fabs.f64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
fabs.ll
fadd64.ll AMDGPU: Make v2i64/v2f64 legal types. 2015-11-25 19:58:34 +00:00
fadd.ll
fceil64.ll DAGCombiner: Combine extract_vector_elt from build_vector 2015-10-12 23:59:50 +00:00
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.ll Fix CHECK directives that weren't checking. 2015-08-31 21:10:35 +00:00
fconst64.ll
fcopysign.f32.ll
fcopysign.f64.ll
fdiv.f64.ll
fdiv.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
ffloor.f64.ll
ffloor.ll
flat-address-space.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
flat-scratch-reg.ll AMDGPU/SI: xnack_mask is always reserved on VI 2016-01-07 17:10:20 +00:00
floor.ll
fma-combine.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
fma.f64.ll
fma.ll
fmad.ll
fmax3.f64.ll
fmax3.ll
fmax_legacy.f64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
fmax_legacy.ll AMDGPU: Fix constant bus use check with subregisters 2016-02-11 06:15:39 +00:00
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll AMDGPU: Materialize sign bits with bfrev 2016-03-11 07:42:49 +00:00
fmed3.ll AMDGPU: Match fmed3 patterns with legacy fmin/fmax 2016-01-28 20:53:48 +00:00
fmin3.ll
fmin_legacy.f64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
fmin_legacy.ll AMDGPU: Fix constant bus use check with subregisters 2016-02-11 06:15:39 +00:00
fmin.ll
fminnum.f64.ll
fminnum.ll AMDGPU: Materialize sign bits with bfrev 2016-03-11 07:42:49 +00:00
fmul64.ll
fmul-2-combine-multi-use.ll
fmul.ll
fmuladd.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
fnearbyint.ll
fneg-fabs.f64.ll AMDGPU: Materialize sign bits with bfrev 2016-03-11 07:42:49 +00:00
fneg-fabs.ll AMDGPU/SI: use S_OR for fneg (fabs f32) 2015-10-29 15:29:05 +00:00
fneg.f64.ll
fneg.ll
fp16_to_fp.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
fp_to_sint.ll
fp_to_uint.f64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
fp_to_uint.ll
fp-classify.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
fpext.ll
fptrunc.ll
fract.f64.ll AMDGPU: Remove AMDGPU.fract intrinsic 2016-01-22 18:42:38 +00:00
fract.ll AMDGPU: Remove AMDGPU.fract intrinsic 2016-01-22 18:42:38 +00:00
frem.ll
fsqrt.ll
fsub64.ll
fsub.ll AMDGPU/SI: Fold operands with sub-registers 2016-01-07 17:10:29 +00:00
ftrunc.f64.ll Revert "Remove unnecessary call to getAllocatableRegClass" 2015-11-12 21:43:25 +00:00
ftrunc.ll
gep-address-space.ll DAGCombiner: Combine extract_vector_elt from build_vector 2015-10-12 23:59:50 +00:00
global_atomics.ll AMDGPU: Set flat_scratch from flat_scratch_init reg 2016-02-12 06:31:30 +00:00
global-constant.ll AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA 2015-12-15 22:39:36 +00:00
global-directive.ll
global-extload-i1.ll
global-extload-i8.ll
global-extload-i16.ll
global-extload-i32.ll AMDGPU: Make v2i64/v2f64 legal types. 2015-11-25 19:58:34 +00:00
global-zero-initializer.ll Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
gv-const-addrspace-fail.ll
gv-const-addrspace.ll
half.ll DAGCombiner: Turn truncate of a bitcasted vector to an extract 2016-03-01 21:31:53 +00:00
hsa-default-device.ll AMDGPU: Fix default device handling 2016-01-27 02:17:49 +00:00
hsa-fp-mode.ll AMDGPU: Set DX10Clamp bit 2016-01-28 20:53:35 +00:00
hsa-globals.ll AMDGPU/SI: Emit global variable sizes when targeting HSA 2016-01-08 14:50:28 +00:00
hsa-group-segment.ll AMDGPU/SI: Don't emit group segment global variables 2015-12-02 17:00:42 +00:00
hsa-note-no-func.ll AMDGPU/SI: Update ISA version for FIJI 2016-01-13 20:39:25 +00:00
hsa.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
i1-copy-implicit-def.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
i1-copy-phi.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
image-attributes.ll ScheduleDAGInstrs: Rework schedule graph builder. 2015-12-04 01:51:19 +00:00
image-resource-id.ll
imm.ll AMDGPU: Materialize sign bits with bfrev 2016-03-11 07:42:49 +00:00
indirect-addressing-si.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
indirect-private-64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
infinite-loop-evergreen.ll
infinite-loop.ll
inline-asm.ll SelectionDAG: Fix a crash on inline asm when output register supports multiple types 2016-03-09 16:02:52 +00:00
inline-calls.ll
inline-constraints.ll AMDGPU/SI: Add support for sgpr and vgpr inline assembly constraints 2015-12-10 02:12:53 +00:00
input-mods.ll
insert_subreg.ll
insert_vector_elt.ll AMDGPU: Make v2i64/v2f64 legal types. 2015-11-25 19:58:34 +00:00
invariant-load-no-alias-store.ll
jump-address.ll
kcache-fold.ll AMDGPU: Replace some deprecated intrinsic uses in tests 2016-01-23 05:42:49 +00:00
kernel-args.ll AMDGPU: Remove SIPrepareScratchRegs 2015-11-30 21:15:53 +00:00
large-alloca-compute.ll AMDGPU: Set flat_scratch from flat_scratch_init reg 2016-02-12 06:31:30 +00:00
large-alloca-graphics.ll AMDGPU: Set element_size in private resource descriptor 2016-02-12 02:40:47 +00:00
large-constant-initializer.ll
lds-alignment.ll AMDGPU: Account for LDS alignment 2016-02-05 19:47:29 +00:00
lds-initializer.ll Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
lds-zero-initializer.ll Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll ScheduleDAGInstrs: Rework schedule graph builder. 2015-12-04 01:51:19 +00:00
llvm.amdgcn.buffer.atomic.ll AMDGPU/SI: Add llvm.amdgcn.buffer.atomic.* intrinsics 2016-03-18 16:24:31 +00:00
llvm.amdgcn.buffer.load.format.ll AMDGPU: Overload return type of llvm.amdgcn.buffer.load.format 2016-03-18 16:24:40 +00:00
llvm.amdgcn.buffer.store.format.ll AMDGPU: Overload return type of llvm.amdgcn.buffer.load.format 2016-03-18 16:24:40 +00:00
llvm.amdgcn.buffer.wbinvl1.ll AMDGPU: Add cache invalidation instructions. 2015-09-24 19:52:21 +00:00
llvm.amdgcn.buffer.wbinvl1.sc.ll AMDGPU: Add cache invalidation instructions. 2015-09-24 19:52:21 +00:00
llvm.amdgcn.buffer.wbinvl1.vol.ll AMDGPU: Add cache invalidation instructions. 2015-09-24 19:52:21 +00:00
llvm.amdgcn.class.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
llvm.amdgcn.cos.ll AMDGPU: Add intrinsics for sin/cos 2016-02-13 01:19:56 +00:00
llvm.amdgcn.cubeid.ll AMDGPU: Add new amdgcn intrinsics for cube instructions 2016-01-26 04:29:56 +00:00
llvm.amdgcn.cubema.ll AMDGPU: Add new amdgcn intrinsics for cube instructions 2016-01-26 04:29:56 +00:00
llvm.amdgcn.cubesc.ll AMDGPU: Add new amdgcn intrinsics for cube instructions 2016-01-26 04:29:56 +00:00
llvm.amdgcn.cubetc.ll AMDGPU: Add new amdgcn intrinsics for cube instructions 2016-01-26 04:29:56 +00:00
llvm.amdgcn.dispatch.ptr.ll Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
llvm.amdgcn.div.fixup.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
llvm.amdgcn.div.fmas.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
llvm.amdgcn.div.scale.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
llvm.amdgcn.ds.bpermute.ll AMDGPU/SI: Do not generate s_waitcnt after ds_permute/ds_bpermute 2016-03-17 16:43:50 +00:00
llvm.amdgcn.ds.permute.ll AMDGPU/SI: Do not generate s_waitcnt after ds_permute/ds_bpermute 2016-03-17 16:43:50 +00:00
llvm.amdgcn.frexp.mant.ll AMDGPU: Add frexp_mant intrinsic 2016-03-21 16:11:05 +00:00
llvm.amdgcn.groupstaticgroup.ll AMDGPU/SI: Implement GroupStaticSize Intrinsic for Dynamic LDS 2016-03-15 17:28:44 +00:00
llvm.amdgcn.image.atomic.ll AMDGPU/SI: add llvm.amdgcn.image.atomic.* intrinsics 2016-03-04 10:39:50 +00:00
llvm.amdgcn.image.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
llvm.amdgcn.interp.ll AMDGPU/SI: Add llvm.amdgcn.v.interp.p[12] intrinsics 2015-12-15 17:02:49 +00:00
llvm.amdgcn.ldexp.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
llvm.amdgcn.log.clamp.ll AMDGPU: Add intrinsics for sin/cos 2016-02-13 01:19:56 +00:00
llvm.amdgcn.mbcnt.ll AMDGPU/SI: Add llvm.amdgcn.mbcnt.* intrinsics 2015-12-15 17:02:52 +00:00
llvm.amdgcn.mov.dpp.ll [AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3 2016-03-18 15:35:51 +00:00
llvm.amdgcn.rcp.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
llvm.amdgcn.read.workdim.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
llvm.amdgcn.rsq.clamp.ll MachineCopyPropagation: Catch copies of the form A<-B;A<-B 2016-02-26 03:18:55 +00:00
llvm.amdgcn.rsq.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
llvm.amdgcn.s.barrier.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
llvm.amdgcn.s.dcache.inv.ll AMDGPU: Add s_dcache_* instructions 2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.inv.vol.ll AMDGPU: Add s_dcache_* instructions 2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.wb.ll AMDGPU: Add s_dcache_* instructions 2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.dcache.wb.vol.ll AMDGPU: Add s_dcache_* instructions 2015-09-24 19:52:27 +00:00
llvm.amdgcn.s.getreg.ll AMDGPU/SI: Define S_GETREG Intrinsic 2016-03-10 16:47:15 +00:00
llvm.amdgcn.s.memrealtime.ll AMDGPU: Implement readcyclecounter 2016-02-27 08:53:46 +00:00
llvm.amdgcn.s.memtime.ll AMDGPU: Implement readcyclecounter 2016-02-27 08:53:46 +00:00
llvm.amdgcn.s.sleep.ll AMDGPU: Add s_sleep intrinsic 2016-02-27 08:53:52 +00:00
llvm.amdgcn.sin.ll AMDGPU: Add intrinsics for sin/cos 2016-02-13 01:19:56 +00:00
llvm.amdgcn.trig.preop.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
llvm.amdgcn.workgroup.id.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
llvm.amdgcn.workitem.id.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
llvm.AMDGPU.barrier.global.ll
llvm.AMDGPU.barrier.local.ll
llvm.AMDGPU.bfe.i32.ll
llvm.AMDGPU.bfe.u32.ll
llvm.AMDGPU.clamp.ll
llvm.AMDGPU.cube.ll AMDGPU: Add new amdgcn intrinsics for cube instructions 2016-01-26 04:29:56 +00:00
llvm.AMDGPU.cvt_f32_ubyte.ll
llvm.amdgpu.dp4.ll
llvm.AMDGPU.flbit.i32.ll
llvm.AMDGPU.kill.ll
llvm.amdgpu.kilp.ll
llvm.AMDGPU.rsq.clamped.f64.ll MachineCopyPropagation: Catch copies of the form A<-B;A<-B 2016-02-26 03:18:55 +00:00
llvm.AMDGPU.rsq.clamped.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
llvm.AMDGPU.rsq.ll AMDGPU: Restore AMDGPU prefixed rsq intrinsic for now 2016-01-26 04:14:16 +00:00
llvm.AMDGPU.tex.ll
llvm.cos.ll
llvm.dbg.value.ll AMDGPU/SI: Use flat for global load/store when targeting HSA 2015-12-22 20:55:23 +00:00
llvm.exp2.ll
llvm.log2.ll
llvm.memcpy.ll AMDGPU: Split LDS vector loads 2015-11-24 12:18:54 +00:00
llvm.pow.ll
llvm.r600.read.local.size.ll ScheduleDAGInstrs: Rework schedule graph builder. 2015-12-04 01:51:19 +00:00
llvm.r600.read.workdim.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
llvm.rint.f64.ll
llvm.rint.ll AMDGPU: Remove AMDIL.round.nearest intrinsic 2016-01-20 21:05:40 +00:00
llvm.round.f64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
llvm.round.ll
llvm.SI.fs.interp.ll AMDGPU/SI: Stoney has only 16 LDS banks 2016-01-27 11:19:45 +00:00
llvm.SI.gather4.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
llvm.SI.getlod.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
llvm.SI.image.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
llvm.SI.image.sample-masked.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
llvm.SI.image.sample.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
llvm.SI.image.sample.o.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
llvm.SI.load.dword.ll
llvm.SI.packf16.ll AMDGPU/SI: handle undef for llvm.SI.packf16 2015-10-29 15:29:09 +00:00
llvm.SI.sendmsg-m0.ll
llvm.SI.sendmsg.ll
llvm.SI.tbuffer.store.ll
llvm.SI.tid.ll
llvm.sin.ll
llvm.sqrt.ll DAGCombiner: Relax sqrt NaN folding check 2016-02-27 09:38:05 +00:00
load64.ll
load-i1.ll
load-input-fold.ll AMDGPU: Replace some deprecated intrinsic uses in tests 2016-01-23 05:42:49 +00:00
load.ll AMDGPU/SI: Select non-uniform constant addrspace loads to flat instructions for HSA 2016-01-05 03:40:16 +00:00
load.vec.ll
local-64.ll
local-atomics64.ll
local-atomics.ll
local-memory-two-objects.ll AMDGPU: Rework how private buffer passed for HSA 2015-11-30 21:16:03 +00:00
local-memory.ll AMDGPU: Rework how private buffer passed for HSA 2015-11-30 21:16:03 +00:00
loop-address.ll
loop-idiom.ll
lower-range-metadata-intrinsic-call.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
lshl.ll
lshr.ll
m0-spill.ll
mad_int24.ll AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
mad_uint24.ll
mad-combine.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
mad-sub.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
madak.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
madmk.ll [AMDGPU] Assembler: change v_madmk operands to have same order as mad. 2016-03-11 09:27:25 +00:00
max3.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
max-literals.ll
max.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
merge-stores.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
min3.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
min.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
missing-store.ll AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointer 2016-02-20 00:37:25 +00:00
move-addr64-rsrc-dead-subreg-writes.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
move-to-valu-atomicrmw.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
mubuf.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
mul_int24.ll
mul_uint24.ll
mul.ll
mulhu.ll
no-hsa-graphics-shaders.ll Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
no-initializer-constant-addrspace.ll
no-shrink-extloads.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
opencl-image-metadata.ll AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering pass 2015-10-01 21:16:05 +00:00
operand-folding.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
operand-spacing.ll
or.ll ScheduleDAGInstrs: Rework schedule graph builder. 2015-12-04 01:51:19 +00:00
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partially-dead-super-register-immediate.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
predicate-dp4.ll
predicates.ll
private-element-size.ll AMDGPU: More bits of frame index are known to be zero 2016-02-27 20:26:57 +00:00
private-memory-atomics.ll AMDGPU: Do not promote allocas with non-inbounds GEPs 2016-02-02 21:16:12 +00:00
private-memory-broken.ll
private-memory-r600.ll AMDGPU: Do not promote allocas with non-inbounds GEPs 2016-02-02 21:16:12 +00:00
private-memory.ll AMDGPU: Remove SignBitIsZero for mubuf scratch offsets 2016-03-21 18:02:18 +00:00
promote-alloca-bitcast-function.ll Refactor backend diagnostics for unsupported features 2016-02-02 13:52:43 +00:00
promote-alloca-invariant-markers.ll AMDGPU: Fix crash with invariant markers 2016-01-22 19:47:54 +00:00
promote-alloca-mem-intrinsics.ll AMDGPU: Preserve alignments on new created globals 2016-02-05 19:47:23 +00:00
promote-alloca-no-opts.ll AMDGPU: Skip promote alloca with no optimizations 2016-02-02 19:32:42 +00:00
promote-alloca-stored-pointer-value.ll
promote-alloca-unhandled-intrinsic.ll AMDGPU: Whitelist handled intrinsics 2016-02-02 19:18:53 +00:00
pv-packing.ll
pv.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600cfg.ll
rcp-pattern.ll AMDGPU: Rename intrinsics to use amdgcn prefix 2016-01-22 21:30:34 +00:00
read_register.ll AMDGPU: Implement read_register and write_register intrinsics 2016-01-26 04:29:24 +00:00
read-register-invalid-subtarget.ll AMDGPU: Implement read_register and write_register intrinsics 2016-01-26 04:29:24 +00:00
read-register-invalid-type-i32.ll AMDGPU: Implement read_register and write_register intrinsics 2016-01-26 04:29:24 +00:00
read-register-invalid-type-i64.ll AMDGPU: Implement read_register and write_register intrinsics 2016-01-26 04:29:24 +00:00
readcyclecounter.ll AMDGPU: Implement readcyclecounter 2016-02-27 08:53:46 +00:00
README
reciprocal.ll
reg-coalescer-sched-crash.ll RegisterCoalescer: Remap subregister lanemasks before exchanging operands 2016-03-05 04:36:13 +00:00
register-count-comments.ll AMDGPU/SI: Use flat for global load/store when targeting HSA 2015-12-22 20:55:23 +00:00
reorder-stores.ll AMDGPU: Make v2i64/v2f64 legal types. 2015-11-25 19:58:34 +00:00
ret_jump.ll AMDGPU/SI: Incomplete shader binaries need to finish execution at the end 2016-03-14 15:57:14 +00:00
ret.ll AMDGPU/SI: Fix a GPU hang with POS_W_FLOAT enabled 2016-01-13 17:23:20 +00:00
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
rv7x0_count3.ll
s_movk_i32.ll AMDGPU: Reduce number of copies emitted 2015-09-24 07:16:37 +00:00
saddo.ll
salu-to-valu.ll AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointer 2016-02-20 00:37:25 +00:00
sampler-resource-id.ll
scalar_to_vector.ll
schedule-fs-loop-nested-if.ll AMDGPU: Replace some deprecated intrinsic uses in tests 2016-01-23 05:42:49 +00:00
schedule-fs-loop-nested.ll AMDGPU: Replace some deprecated intrinsic uses in tests 2016-01-23 05:42:49 +00:00
schedule-fs-loop.ll AMDGPU: Replace some deprecated intrinsic uses in tests 2016-01-23 05:42:49 +00:00
schedule-global-loads.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
schedule-if-2.ll
schedule-if.ll
schedule-kernel-arg-loads.ll
schedule-vs-if-nested-loop-failure.ll AMDGPU: Switch barrier intrinsics to using convergent 2015-12-19 01:46:41 +00:00
schedule-vs-if-nested-loop.ll
scratch-buffer.ll AMDGPU: Remove SignBitIsZero for mubuf scratch offsets 2016-03-21 18:02:18 +00:00
sdiv.ll
sdivrem24.ll
sdivrem64.ll
select64.ll AMDGPU/SI: Fold operands through REG_SEQUENCE instructions 2015-09-09 15:43:26 +00:00
select-i1.ll
select-vectors.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
set-dx10.ll ScheduleDAGInstrs: Rework schedule graph builder. 2015-12-04 01:51:19 +00:00
setcc64.ll
setcc-equivalent.ll
setcc-opt.ll AMDGPU/SI: Prevent the DAGCombiner from creating setcc with i1 inputs 2016-01-20 00:13:22 +00:00
setcc.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg.ll AMDGPU: Remove min/max intrinsics 2016-01-20 20:50:19 +00:00
sgpr-control-flow.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
shared-op-cycle.ll
shift-i64-opts.ll AMDGPU: Reduce 64-bit SRAs 2016-01-18 22:09:04 +00:00
shl_add_constant.ll DAGCombiner: Don't unnecessarily swap operands in ReassociateOps 2016-02-27 19:57:45 +00:00
shl_add_ptr.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
shl.ll AMDGPU: Split 64-bit and of constant up 2016-01-18 22:01:13 +00:00
si-annotate-cf-assertion.ll
si-annotate-cf.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
si-annotate-cfg-loop-assert.ll AMDGPU/SI: Annotate Loops with Constant Condition in SIAnnotateControlFlow pass. 2016-02-12 17:11:04 +00:00
si-instr-info-correct-implicit-operands.ll AMDGPU: Don't reserve SCRATCH_PTR input register 2015-11-30 15:46:47 +00:00
si-literal-folding.ll
si-lod-bias.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
si-scheduler.ll AMDGPU: Remove old sample intrinsics 2016-01-26 04:38:08 +00:00
si-sgpr-spill.ll AMDGPU: Remove old sample intrinsics 2016-01-26 04:38:08 +00:00
si-spill-cf.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
si-spill-sgpr-stack.ll AMDGPU/SI: Add support for spiling SGPRs to scratch buffer 2016-03-04 18:31:18 +00:00
si-triv-disjoint-mem-access.ll AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointer 2016-02-20 00:37:25 +00:00
si-vector-hang.ll
sign_extend.ll
simplify-demanded-bits-build-pair.ll
sint_to_fp.f64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
sint_to_fp.i64.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
sint_to_fp.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
smed3.ll AMDGPU: Match more med3 integer patterns 2016-03-07 21:54:48 +00:00
sminmax.ll SelectionDAG: Match min/max if the scalar operation is legal 2015-12-11 23:16:47 +00:00
smrd-vccz-bug.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
smrd.ll
spill-alloc-sgpr-init-bug.ll AMDGPU/SI: Do not move scratch resource register on Tonga & Iceland 2016-01-05 20:42:49 +00:00
spill-scavenge-offset.ll AMDGPU: Quick fix for extreme slowness in spill-scavenge-offset.ll test 2016-02-12 00:05:34 +00:00
split-scalar-i64-add.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
split-smrd.ll [AMDGPU] Assembler: Basic support for MIMG 2016-02-26 09:51:05 +00:00
split-vector-memoperand-offsets.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
sra.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
srem.ll
srl.ll ScheduleDAGInstrs: Rework schedule graph builder. 2015-12-04 01:51:19 +00:00
ssubo.ll
store_typed.ll AMDGPU: Add MEM_RAT STORE_TYPED. 2015-10-01 17:51:34 +00:00
store-barrier.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
store-v3i32.ll
store-v3i64.ll
store-vector-ptrs.ll
store.ll AMDGPU/R600: Implement allowsMisalignedMemoryAccess 2016-02-22 21:04:16 +00:00
store.r600.ll
structurize1.ll
structurize.ll
sub.ll
subreg-coalescer-crash.ll AMDGPU: Remove old sample intrinsics 2016-01-26 04:38:08 +00:00
subreg-coalescer-undef-use.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
subreg-eliminate-dead.ll
swizzle-export.ll
tex-clause-antidep.ll AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix 2016-01-22 19:00:09 +00:00
texture-input-merge.ll AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix 2016-01-22 19:00:09 +00:00
trunc-bitcast-vector.ll DAGCombiner: Turn truncate of a bitcasted vector to an extract 2016-03-01 21:31:53 +00:00
trunc-cmp-constant.ll AMDGPU/SI: Prevent the DAGCombiner from creating setcc with i1 inputs 2016-01-20 00:13:22 +00:00
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store.ll
trunc-vector-store-assertion-failure.ll
trunc.ll AMDGPU/SI: use S_AND for i1 trunc 2015-10-29 15:05:03 +00:00
tti-unroll-prefs.ll
uaddo.ll
udiv.ll AMDGPU: Cleanup udiv test 2016-01-11 21:18:40 +00:00
udivrem24.ll
udivrem64.ll
udivrem.ll AMDGPU: Stop reserving v[254:255] 2015-10-20 03:59:58 +00:00
uint_to_fp.f64.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
uint_to_fp.i64.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
uint_to_fp.ll [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 2016-02-12 17:57:54 +00:00
umed3.ll AMDGPU: Match more med3 integer patterns 2016-03-07 21:54:48 +00:00
unaligned-load-store.ll
unhandled-loop-condition-assertion.ll
uniform-cfg.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
uniform-crash.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
uniform-loop-inside-nonuniform.ll AMDGPU/SI: Fix threshold calculation for branching when exec is zero 2016-03-21 18:56:58 +00:00
unroll.ll
unsupported-cc.ll ScheduleDAGInstrs: Rework schedule graph builder. 2015-12-04 01:51:19 +00:00
urecip.ll
urem.ll
use-sgpr-multiple-times.ll AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
usubo.ll
v1i64-kernel-arg.ll
v_cndmask.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
v_mac.ll
valu-i1.ll AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
vector-alloca.ll
vertex-fetch-encoding.ll
vgpr-spill-emergency-stack-slot-compute.ll AMDGPU: Prepare for reducing private element size. 2016-02-13 04:18:53 +00:00
vgpr-spill-emergency-stack-slot.ll AMDGPU: Prepare for reducing private element size. 2016-02-13 04:18:53 +00:00
vop-shrink.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
waitcnt-flat.ll AMDGPU/SI: Fix s_waitcnt insertion for flat instructions 2016-02-19 15:33:13 +00:00
work-item-intrinsics.ll AMDGPU: Add new amdgcn workitem intrinsics 2016-01-30 04:25:19 +00:00
write_register.ll AMDGPU: Implement read_register and write_register intrinsics 2016-01-26 04:29:24 +00:00
write-register-vgpr-into-sgpr.ll AMDGPU: Remove some old intrinsic uses from tests 2016-02-11 06:02:01 +00:00
wrong-transalu-pos-fix.ll
xor.ll ScheduleDAGInstrs: Rework schedule graph builder. 2015-12-04 01:51:19 +00:00
zero_extend.ll AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCE 2015-11-02 23:15:42 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.