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llvm-mirror/test/MC/RISCV
History
Alex Bradbury dbb6015f8e [RISCV][NFC] Remove old CHECK lines from linker-relaxation.s test 
The RELOC: check lines are no longer used.

llvm-svn: 356654
2019-03-21 09:53:19 +00:00
..
align.s
[RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled
2019-01-30 11:16:59 +00:00
cfi-regs-invalid.s
[RISCV] Fix RISCVAsmParser::ParseRegister and add tests
2019-03-17 12:00:58 +00:00
cfi-regs-valid.s
[RISCV] Fix RISCVAsmParser::ParseRegister and add tests
2019-03-17 12:00:58 +00:00
cnop.s
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
compress-cjal.s
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
compress-rv32d.s
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
compress-rv32f.s
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
compress-rv32i.s
[RISCV] Add UNIMP instruction (32- and 16-bit forms)
2018-11-30 13:39:17 +00:00
compress-rv64i.s
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
compressed-relocations.s
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced
2018-05-18 06:42:21 +00:00
csr-aliases.s
[RISCV] Allow access to FP CSRs without F extension
2019-03-08 23:01:08 +00:00
data-directives-invalid.s
[RISCV] Add support for .half, .hword, .word, .dword directives
2018-05-17 05:58:08 +00:00
data-directives-valid.s
[RISCV] Add support for .half, .hword, .word, .dword directives
2018-05-17 05:58:08 +00:00
elf-flags.s
[RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer
2018-01-26 07:53:07 +00:00
elf-header.s
[RISCV] Bugfix createRISCVELFObjectWriter
2017-10-18 16:11:31 +00:00
empty-string.s
Move some llvm-mc tests where they belong
2019-02-05 20:12:48 +00:00
fixups-compressed.s
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
fixups-diagnostics.s
[RISCV] Add common fixups and relocations
2017-09-28 08:26:24 +00:00
fixups-expr.s
[RISCV] Add symbol diff relocation support for RISC-V
2018-05-23 12:36:18 +00:00
fixups.s
[RISCV] Properly evaluate fixup_riscv_pcrel_lo12
2018-12-20 14:52:15 +00:00
function-call-invalid.s
[RISCV] Support "call" pseudoinstruction in the MC layer
2018-04-25 14:18:55 +00:00
function-call.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00
hilo-constaddr-expr.s
[RISCV] Add symbol diff relocation support for RISC-V
2018-05-23 12:36:18 +00:00
hilo-constaddr.s
[RISCV] Add symbol diff relocation support for RISC-V
2018-05-23 12:36:18 +00:00
linker-relaxation.s
[RISCV][NFC] Remove old CHECK lines from linker-relaxation.s test
2019-03-21 09:53:19 +00:00
lit.local.cfg
…
lla-invalid.s
[RISCV] Add "lla" pseudo-instruction to assembler
2018-08-09 07:08:20 +00:00
machine-csr-names-invalid.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00
machine-csr-names.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00
option-invalid.s
[RISCV] Support .option push and .option pop
2018-11-28 16:39:14 +00:00
option-mix.s
[RISCV][MC] Find matching pcrel_hi fixup in more cases.
2019-03-12 18:14:16 +00:00
option-pushpop.s
[RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates.
2019-01-21 05:27:09 +00:00
option-relax.s
[RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates.
2019-01-21 05:27:09 +00:00
option-rvc.s
[RISCV] Support .option rvc and norvc assembler directives
2018-05-11 17:30:28 +00:00
pcrel-lo12-invalid.s
[RISCV] Properly evaluate fixup_riscv_pcrel_lo12
2018-12-20 14:52:15 +00:00
priv-invalid.s
[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools
2017-12-13 12:46:55 +00:00
priv-valid.s
[RISCV] Enable emission of alias instructions by default
2017-12-15 09:47:01 +00:00
relocations.s
[RISCV] Support assembling %got_pcrel_hi operator
2019-02-15 09:43:46 +00:00
rv32-machine-csr-names.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00
rv32-relaxation.s
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced
2018-05-18 06:42:21 +00:00
rv32-user-csr-names.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00
rv32a-invalid.s
[RISCV] MC layer support for the standard RV64A instruction set extension
2017-12-07 10:59:12 +00:00
rv32a-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv32c-aliases-valid.s
[RISC-V] Fixed alias for addi x2, x2, 0
2018-08-09 20:51:53 +00:00
rv32c-fuzzed-invalid.s
[RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed.
2018-08-24 23:47:49 +00:00
rv32c-invalid.s
[RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types
2018-09-13 18:37:23 +00:00
rv32c-only-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv32c-valid.s
[RISCV] Add UNIMP instruction (32- and 16-bit forms)
2018-11-30 13:39:17 +00:00
rv32d-invalid.s
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
rv32d-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv32dc-invalid.s
[RISCV] MC layer support for the remaining RVC instructions
2017-12-13 09:32:55 +00:00
rv32dc-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv32f-invalid.s
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
rv32f-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv32fc-aliases-valid.s
[RISCV] Add implied zero offset load/store alias patterns
2019-02-21 14:09:34 +00:00
rv32fc-invalid.s
[RISCV] MC layer support for the remaining RVC instructions
2017-12-13 09:32:55 +00:00
rv32fc-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv32i-aliases-invalid.s
[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate
2018-08-08 14:45:44 +00:00
rv32i-aliases-valid.s
[RISCV] Add implied zero offset load/store alias patterns
2019-02-21 14:09:34 +00:00
rv32i-invalid.s
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
rv32i-valid.s
[RISCV] Allow access to FP CSRs without F extension
2019-03-08 23:01:08 +00:00
rv32m-invalid.s
[RISCV] MC layer support for the standard RV64M instruction set extension
2017-12-07 10:56:07 +00:00
rv32m-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv64-machine-csr-names.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00
rv64-relaxation.s
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced
2018-05-18 06:42:21 +00:00
rv64-user-csr-names.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00
rv64a-invalid.s
[RISCV] MC layer support for the standard RV64A instruction set extension
2017-12-07 10:59:12 +00:00
rv64a-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv64c-aliases-valid.s
[RISCV] Add implied zero offset load/store alias patterns
2019-02-21 14:09:34 +00:00
rv64c-invalid.s
[RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types
2018-09-13 18:37:23 +00:00
rv64c-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv64d-aliases-valid.s
[RISCV] Enable emission of alias instructions by default
2017-12-15 09:47:01 +00:00
rv64d-invalid.s
[RISCV] Add missed tests for RV64D MC layer support
2017-12-07 11:05:38 +00:00
rv64d-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv64dc-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv64f-aliases-valid.s
[RISCV] Enable emission of alias instructions by default
2017-12-15 09:47:01 +00:00
rv64f-invalid.s
[RISCV] MC layer support for the standard RV64F instruction set extension
2017-12-07 11:02:55 +00:00
rv64f-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rv64i-aliases-invalid.s
[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate
2018-08-08 14:45:44 +00:00
rv64i-aliases-valid.s
[RISCV] Add implied zero offset load/store alias patterns
2019-02-21 14:09:34 +00:00
rv64i-invalid.s
[RISCV][MC] Reject bare symbols for the simm12 operand type
2018-09-18 15:13:29 +00:00
rv64i-pseudos.s
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
rv64i-valid.s
[RISCV][MC] Add support for evaluating constant symbols as immediates
2019-01-10 15:33:17 +00:00
rv64m-valid.s
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
2018-09-06 13:41:04 +00:00
rvc-aliases-valid.s
[RISCV] Add implied zero offset load/store alias patterns
2019-02-21 14:09:34 +00:00
rvd-aliases-valid.s
[RISCV] Add implied zero offset load/store alias patterns
2019-02-21 14:09:34 +00:00
rvd-pseudos.s
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
rvdc-aliases-valid.s
[RISCV] Add implied zero offset load/store alias patterns
2019-02-21 14:09:34 +00:00
rvf-aliases-valid.s
[RISCV] Add implied zero offset load/store alias patterns
2019-02-21 14:09:34 +00:00
rvf-pseudos.s
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
rvf-user-csr-names.s
[RISCV] Allow access to FP CSRs without F extension
2019-03-08 23:01:08 +00:00
rvi-aliases-valid.s
[RISCV] Add additional CSR instruction aliases (imm. operands)
2018-11-30 14:10:52 +00:00
rvi-alternate-abi-names.s
[RISCV] Allow fp as an alias of s0
2019-03-11 21:35:26 +00:00
rvi-pseudos-invalid.s
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
rvi-pseudos.s
[RISCV] Implement pseudo instructions for load/store from a symbol address.
2019-02-20 03:31:32 +00:00
supervisor-csr-names.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00
tail-call-invalid.s
[RISCV] Implement MC layer support for the tail pseudoinstruction
2018-05-17 17:31:27 +00:00
tail-call.s
[RISCV] Tail calls don't need to save return address
2018-06-21 14:37:09 +00:00
target-abi-invalid.s
[RISCV] Support -target-abi at the MC layer and for codegen
2019-03-09 09:28:06 +00:00
target-abi-valid.s
[RISCV] Support -target-abi at the MC layer and for codegen
2019-03-09 09:28:06 +00:00
user-csr-names-invalid.s
[RISCV] Allow access to FP CSRs without F extension
2019-03-08 23:01:08 +00:00
user-csr-names.s
[RISCV] Support named operands for CSR instructions.
2018-10-04 21:50:54 +00:00