| .. |
|
AsmParser
|
[AMDGPU][MC] Corrected error position for some operands and modifiers
|
2020-11-16 16:11:23 +03:00 |
|
Disassembler
|
llvmbuildectomy - replace llvm-build by plain cmake
|
2020-11-13 10:35:24 +01:00 |
|
MCTargetDesc
|
Fix MSVC signed/unsigned comparison warning. NFCI.
|
2020-11-13 10:20:48 +00:00 |
|
TargetInfo
|
llvmbuildectomy - replace llvm-build by plain cmake
|
2020-11-13 10:35:24 +01:00 |
|
Utils
|
llvmbuildectomy - replace llvm-build by plain cmake
|
2020-11-13 10:35:24 +01:00 |
|
AMDGPU.h
|
[amdgpu] Add the late codegen preparation pass.
|
2020-10-27 14:07:59 -04:00 |
|
AMDGPU.td
|
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
|
2020-11-11 14:40:14 +00:00 |
|
AMDGPUAliasAnalysis.cpp
|
[amdgpu] Enhance AMDGPU AA.
|
2020-10-20 09:54:12 -04:00 |
|
AMDGPUAliasAnalysis.h
|
|
|
|
AMDGPUAlwaysInlinePass.cpp
|
|
|
|
AMDGPUAnnotateKernelFeatures.cpp
|
|
|
|
AMDGPUAnnotateUniformValues.cpp
|
|
|
|
AMDGPUArgumentUsageInfo.cpp
|
|
|
|
AMDGPUArgumentUsageInfo.h
|
|
|
|
AMDGPUAsmPrinter.cpp
|
[AMDGPU] Enable multi-dword flat scratch load/stores
|
2020-11-12 13:38:56 -08:00 |
|
AMDGPUAsmPrinter.h
|
|
|
|
AMDGPUAtomicOptimizer.cpp
|
[AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer
|
2020-09-30 11:09:18 +02:00 |
|
AMDGPUCallingConv.td
|
[AMDGPU] Add amdgpu_gfx calling convention
|
2020-11-09 16:51:44 +01:00 |
|
AMDGPUCallLowering.cpp
|
[AMDGPU] Omit buffer resource with flat scratch.
|
2020-11-09 08:05:20 -08:00 |
|
AMDGPUCallLowering.h
|
|
|
|
AMDGPUCodeGenPrepare.cpp
|
SelectionDAG.h - remove unnecessary FunctionLoweringInfo.h include. NFCI.
|
2020-09-03 18:33:25 +01:00 |
|
AMDGPUCombine.td
|
AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner
|
2020-11-03 09:24:50 +01:00 |
|
AMDGPUExportClustering.cpp
|
[AMDGPU] Fix scheduling of exp pos4
|
2020-11-12 19:57:14 +00:00 |
|
AMDGPUExportClustering.h
|
|
|
|
AMDGPUFeatures.td
|
|
|
|
AMDGPUFixFunctionBitcasts.cpp
|
|
|
|
AMDGPUFrameLowering.cpp
|
|
|
|
AMDGPUFrameLowering.h
|
|
|
|
AMDGPUGenRegisterBankInfo.def
|
AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping
|
2020-08-17 09:53:26 -04:00 |
|
AMDGPUGISel.td
|
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
|
2020-08-21 12:26:31 +02:00 |
|
AMDGPUGlobalISelUtils.cpp
|
[AMDGPU] Remove an unused return value. NFC.
|
2020-11-10 09:15:14 +00:00 |
|
AMDGPUGlobalISelUtils.h
|
[AMDGPU] Remove an unused return value. NFC.
|
2020-11-10 09:15:14 +00:00 |
|
AMDGPUHSAMetadataStreamer.cpp
|
|
|
|
AMDGPUHSAMetadataStreamer.h
|
|
|
|
AMDGPUInline.cpp
|
|
|
|
AMDGPUInstCombineIntrinsic.cpp
|
[AMDGPU] Add simplification/combines for llvm.amdgcn.fma.legacy
|
2020-10-23 16:16:13 +01:00 |
|
AMDGPUInstrInfo.cpp
|
|
|
|
AMDGPUInstrInfo.h
|
[AMDGPU] Use tablegen for argument indices
|
2020-10-05 11:50:52 +02:00 |
|
AMDGPUInstrInfo.td
|
|
|
|
AMDGPUInstructions.td
|
[TableGen] Add the !filter bang operator.
|
2020-11-09 10:56:55 -05:00 |
|
AMDGPUInstructionSelector.cpp
|
[GlobalISel] Add matchers for specific constants and a matcher for negations
|
2020-11-13 09:24:54 -08:00 |
|
AMDGPUInstructionSelector.h
|
[AMDGPU] Fix ds_read2/write2 with unaligned offsets
|
2020-11-03 15:16:10 +00:00 |
|
AMDGPUISelDAGToDAG.cpp
|
AMDGPU: Factor out large flat offset splitting
|
2020-11-13 11:22:13 -05:00 |
|
AMDGPUISelLowering.cpp
|
[AMDGPU] Add amdgpu_gfx calling convention
|
2020-11-09 16:51:44 +01:00 |
|
AMDGPUISelLowering.h
|
[AMDGPU] Some refactoring after D90404. NFC.
|
2020-11-01 13:18:53 +05:30 |
|
AMDGPULateCodeGenPrepare.cpp
|
[amdgpu] Add the late codegen preparation pass.
|
2020-10-27 14:07:59 -04:00 |
|
AMDGPULegalizerInfo.cpp
|
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
|
2020-11-11 14:40:14 +00:00 |
|
AMDGPULegalizerInfo.h
|
[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
|
AMDGPULibCalls.cpp
|
[AMDGPU] Mark sin/cos load folding as modifying the function.
|
2020-11-13 14:49:33 -08:00 |
|
AMDGPULibFunc.cpp
|
|
|
|
AMDGPULibFunc.h
|
|
|
|
AMDGPULowerIntrinsics.cpp
|
AMDGPU: Use caller subtarget, not intrinsic declaration
|
2020-08-27 16:42:09 -04:00 |
|
AMDGPULowerKernelArguments.cpp
|
|
|
|
AMDGPULowerKernelAttributes.cpp
|
|
|
|
AMDGPUMachineCFGStructurizer.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
AMDGPUMachineFunction.cpp
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
AMDGPUMachineFunction.h
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
AMDGPUMachineModuleInfo.cpp
|
|
|
|
AMDGPUMachineModuleInfo.h
|
|
|
|
AMDGPUMacroFusion.cpp
|
|
|
|
AMDGPUMacroFusion.h
|
|
|
|
AMDGPUMCInstLower.cpp
|
AMDGPU: Increase branch size estimate with offset bug
|
2020-10-23 10:34:24 -04:00 |
|
AMDGPUOpenCLEnqueuedBlockLowering.cpp
|
|
|
|
AMDGPUPerfHintAnalysis.cpp
|
|
|
|
AMDGPUPerfHintAnalysis.h
|
|
|
|
AMDGPUPostLegalizerCombiner.cpp
|
AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner
|
2020-11-03 09:24:50 +01:00 |
|
AMDGPUPreLegalizerCombiner.cpp
|
|
|
|
AMDGPUPrintfRuntimeBinding.cpp
|
AMDGPUPrintfRuntimeBinding.cpp - drop unnecessary casts/dyn_casts. NFCI.
|
2020-09-15 14:49:04 +01:00 |
|
AMDGPUPromoteAlloca.cpp
|
|
|
|
AMDGPUPropagateAttributes.cpp
|
AMDGPU: Propagate amdgpu-flat-work-group-size attributes
|
2020-10-21 12:06:24 -04:00 |
|
AMDGPUPTNote.h
|
|
|
|
AMDGPURegBankCombiner.cpp
|
|
|
|
AMDGPURegisterBankInfo.cpp
|
[AMDGPU] Remove an unused return value. NFC.
|
2020-11-10 09:15:14 +00:00 |
|
AMDGPURegisterBankInfo.h
|
|
|
|
AMDGPURegisterBanks.td
|
|
|
|
AMDGPURewriteOutArguments.cpp
|
|
|
|
AMDGPUSearchableTables.td
|
|
|
|
AMDGPUSubtarget.cpp
|
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
|
2020-11-11 14:40:14 +00:00 |
|
AMDGPUSubtarget.h
|
[AMDGPU] Enable multi-dword flat scratch load/stores
|
2020-11-12 13:38:56 -08:00 |
|
AMDGPUTargetMachine.cpp
|
[AMDGPU] Fix insert of SIPreAllocateWWMRegs in FastRegAlloc
|
2020-10-28 12:15:15 +09:00 |
|
AMDGPUTargetMachine.h
|
|
|
|
AMDGPUTargetObjectFile.cpp
|
|
|
|
AMDGPUTargetObjectFile.h
|
|
|
|
AMDGPUTargetTransformInfo.cpp
|
[AMDGPU] Add amdgpu_gfx calling convention
|
2020-11-09 16:51:44 +01:00 |
|
AMDGPUTargetTransformInfo.h
|
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
|
2020-11-11 14:40:14 +00:00 |
|
AMDGPUUnifyDivergentExitNodes.cpp
|
[AMDGPU] One more use of the new export target names. NFC.
|
2020-11-13 09:44:09 +00:00 |
|
AMDGPUUnifyMetadata.cpp
|
|
|
|
AMDILCFGStructurizer.cpp
|
|
|
|
AMDKernelCodeT.h
|
|
|
|
BUFInstructions.td
|
[AMDGPU] Add default 1 glc operand to rtn atomics
|
2020-11-05 10:41:59 -08:00 |
|
CaymanInstructions.td
|
|
|
|
CMakeLists.txt
|
llvmbuildectomy - replace llvm-build by plain cmake
|
2020-11-13 10:35:24 +01:00 |
|
DSInstructions.td
|
[AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds
|
2020-10-29 17:31:59 +00:00 |
|
EvergreenInstructions.td
|
[AMDGPU] Omit needless string concatenations. NFC.
|
2020-10-28 12:56:52 +00:00 |
|
EXPInstructions.td
|
[AMDGPU] Separate out real exp instructions by subtarget. NFC.
|
2020-11-11 17:13:40 +00:00 |
|
FLATInstructions.td
|
[AMDGPU] Add default 1 glc operand to rtn atomics
|
2020-11-05 10:41:59 -08:00 |
|
GCNDPPCombine.cpp
|
|
|
|
GCNHazardRecognizer.cpp
|
[NFC] Use Register/MCRegister
|
2020-11-04 12:20:17 -08:00 |
|
GCNHazardRecognizer.h
|
[AMDGPU] Add Reset function to GCNHazardRecognizer
|
2020-10-28 16:32:32 -07:00 |
|
GCNILPSched.cpp
|
|
|
|
GCNIterativeScheduler.cpp
|
|
|
|
GCNIterativeScheduler.h
|
|
|
|
GCNMinRegStrategy.cpp
|
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
|
2020-09-21 13:33:05 +02:00 |
|
GCNNSAReassign.cpp
|
[NFC][MC] Use MCRegister in LiveRangeMatrix
|
2020-10-12 08:54:36 -07:00 |
|
GCNProcessors.td
|
[AMDGPU] Add gfx1033 target
|
2020-11-03 16:27:48 +00:00 |
|
GCNRegBankReassign.cpp
|
[AMDGPU] Resolve pseudo registers at encoding uses
|
2020-11-04 12:52:32 -05:00 |
|
GCNRegPressure.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
GCNRegPressure.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
GCNSchedStrategy.cpp
|
|
|
|
GCNSchedStrategy.h
|
|
|
|
InstCombineTables.td
|
|
|
|
MIMGInstructions.td
|
[TableGen] Add the !filter bang operator.
|
2020-11-09 10:56:55 -05:00 |
|
R600.td
|
|
|
|
R600AsmPrinter.cpp
|
|
|
|
R600AsmPrinter.h
|
|
|
|
R600ClauseMergePass.cpp
|
|
|
|
R600ControlFlowFinalizer.cpp
|
|
|
|
R600Defines.h
|
|
|
|
R600EmitClauseMarkers.cpp
|
|
|
|
R600ExpandSpecialInstrs.cpp
|
|
|
|
R600FrameLowering.cpp
|
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
|
2020-11-05 11:02:18 +00:00 |
|
R600FrameLowering.h
|
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
|
2020-11-05 11:02:18 +00:00 |
|
R600InstrFormats.td
|
|
|
|
R600InstrInfo.cpp
|
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
|
2020-11-05 11:02:18 +00:00 |
|
R600InstrInfo.h
|
Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate
|
2020-10-21 11:52:47 +01:00 |
|
R600Instructions.td
|
|
|
|
R600ISelLowering.cpp
|
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
|
2020-11-05 11:02:18 +00:00 |
|
R600ISelLowering.h
|
|
|
|
R600MachineFunctionInfo.cpp
|
|
|
|
R600MachineFunctionInfo.h
|
|
|
|
R600MachineScheduler.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600MachineScheduler.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600OpenCLImageTypeLoweringPass.cpp
|
|
|
|
R600OptimizeVectorRegisters.cpp
|
|
|
|
R600Packetizer.cpp
|
|
|
|
R600Processors.td
|
|
|
|
R600RegisterInfo.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600RegisterInfo.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600RegisterInfo.td
|
|
|
|
R600Schedule.td
|
|
|
|
R700Instructions.td
|
|
|
|
SIAddIMGInit.cpp
|
[AMDGPU] gfx1030 RT support
|
2020-09-16 11:40:58 -07:00 |
|
SIAnnotateControlFlow.cpp
|
|
|
|
SIDefines.h
|
[AMDGPU] Fix scheduling of exp pos4
|
2020-11-12 19:57:14 +00:00 |
|
SIFixSGPRCopies.cpp
|
[AMDGPU] Fix iterating in SIFixSGPRCopies
|
2020-11-04 18:43:19 +01:00 |
|
SIFixVGPRCopies.cpp
|
|
|
|
SIFoldOperands.cpp
|
[AMDGPU] Use flat scratch instructions where available
|
2020-10-26 14:40:42 -07:00 |
|
SIFormMemoryClauses.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIFrameLowering.cpp
|
[AMDGPU] Remove scratch rsrc from spill pseudos
|
2020-11-12 15:23:37 -08:00 |
|
SIFrameLowering.h
|
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
|
2020-11-05 11:02:18 +00:00 |
|
SIInsertHardClauses.cpp
|
|
|
|
SIInsertSkips.cpp
|
[AMDGPU] Define and use names for export targets. NFC.
|
2020-11-12 19:57:14 +00:00 |
|
SIInsertWaitcnts.cpp
|
[AMDGPU] Fix scheduling of exp pos4
|
2020-11-12 19:57:14 +00:00 |
|
SIInstrFormats.td
|
[AMDGPU] Split exp instructions out into their own tablegen file. NFC.
|
2020-11-11 17:13:40 +00:00 |
|
SIInstrInfo.cpp
|
AMDGPU: Factor out large flat offset splitting
|
2020-11-13 11:22:13 -05:00 |
|
SIInstrInfo.h
|
AMDGPU: Factor out large flat offset splitting
|
2020-11-13 11:22:13 -05:00 |
|
SIInstrInfo.td
|
[AMDGPU] Split exp instructions out into their own tablegen file. NFC.
|
2020-11-11 17:13:40 +00:00 |
|
SIInstructions.td
|
[AMDGPU] Remove scratch rsrc from spill pseudos
|
2020-11-12 15:23:37 -08:00 |
|
SIISelLowering.cpp
|
[AMDGPU] Enable multi-dword flat scratch load/stores
|
2020-11-12 13:38:56 -08:00 |
|
SIISelLowering.h
|
[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
|
SILoadStoreOptimizer.cpp
|
[AMDGPU] gfx1030 RT support
|
2020-09-16 11:40:58 -07:00 |
|
SILowerControlFlow.cpp
|
[AMDGPU] SILowerControlFlow::removeMBBifRedundant. Refactoring plus fix for the null MBB pointer in MF->splice
|
2020-10-30 14:46:08 +03:00 |
|
SILowerI1Copies.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
SILowerSGPRSpills.cpp
|
[AMDGPU] Add amdgpu_gfx calling convention
|
2020-11-09 16:51:44 +01:00 |
|
SIMachineFunctionInfo.cpp
|
[AMDGPU] Omit buffer resource with flat scratch.
|
2020-11-09 08:05:20 -08:00 |
|
SIMachineFunctionInfo.h
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
SIMachineScheduler.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIMachineScheduler.h
|
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
|
2020-09-21 13:33:05 +02:00 |
|
SIMemoryLegalizer.cpp
|
[NFC][AMDGPU] Reorder SIMemoryLegalizer functions to be consistent
|
2020-10-22 05:39:18 +00:00 |
|
SIModeRegister.cpp
|
[AMDGPU] Enable scheduling around FP MODE-setting instructions
|
2020-09-16 16:10:47 +01:00 |
|
SIOptimizeExecMasking.cpp
|
[AMDGPU] Fix lowering of S_MOV_{B32,B64}_term
|
2020-11-10 12:16:31 +09:00 |
|
SIOptimizeExecMaskingPreRA.cpp
|
[NFC] Use Register/MCRegister
|
2020-11-04 12:20:17 -08:00 |
|
SIPeepholeSDWA.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIPostRABundler.cpp
|
|
|
|
SIPreAllocateWWMRegs.cpp
|
AMDGPU: Reorder checks
|
2020-11-02 10:21:48 -05:00 |
|
SIPreEmitPeephole.cpp
|
|
|
|
SIProgramInfo.cpp
|
[AMDGPU] Set rsrc1 flags for graphics shaders
|
2020-11-04 12:25:41 +01:00 |
|
SIProgramInfo.h
|
[AMDGPU] Set rsrc1 flags for graphics shaders
|
2020-11-04 12:25:41 +01:00 |
|
SIRegisterInfo.cpp
|
[AMDGPU] Remove scratch rsrc from spill pseudos
|
2020-11-12 15:23:37 -08:00 |
|
SIRegisterInfo.h
|
[AMDGPU] Remove scratch rsrc from spill pseudos
|
2020-11-12 15:23:37 -08:00 |
|
SIRegisterInfo.td
|
[TableGen] Add the !filter bang operator.
|
2020-11-09 10:56:55 -05:00 |
|
SIRemoveShortExecBranches.cpp
|
|
|
|
SISchedule.td
|
[AMDGPU] Add XDL resource to scheduling model
|
2020-09-14 13:48:54 -07:00 |
|
SIShrinkInstructions.cpp
|
[AMDGPU] Fix VC warning about singed/unsigned comparison. NFC.
|
2020-10-26 11:55:57 -07:00 |
|
SIWholeQuadMode.cpp
|
[NFC] Use [MC]Register
|
2020-11-09 08:37:14 -08:00 |
|
SMInstructions.td
|
|
|
|
SOPInstructions.td
|
[amdgpu] Add llvm.amdgcn.endpgm support.
|
2020-11-05 19:06:50 -05:00 |
|
VIInstrFormats.td
|
|
|
|
VOP1Instructions.td
|
|
|
|
VOP2Instructions.td
|
[AMDGPU] Fix double space in disassembly of SDWA instructions with vcc
|
2020-10-28 21:39:39 +00:00 |
|
VOP3Instructions.td
|
[AMDGPU] Allow some modifiers on VOP3B instructions
|
2020-10-28 21:54:14 +00:00 |
|
VOP3PInstructions.td
|
[AMDGPU] Set default op_sel_hi on accvgpr read/write
|
2020-11-10 13:07:29 -08:00 |
|
VOPCInstructions.td
|
[AMDGPU] Corrected declaration of VOPC instructions with SDWA addressing mode.
|
2020-11-05 11:15:50 -05:00 |
|
VOPInstructions.td
|
[AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC.
|
2020-10-21 09:56:43 +01:00 |
