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llvm-mirror/lib/CodeGen/MachineVerifier.cpp

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[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
//===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 09:50:56 +01:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
//
//===----------------------------------------------------------------------===//
//
// Pass to verify generated machine code. The following is checked:
//
// Operand counts: All explicit operands must be present.
//
// Register classes: All physical and virtual register operands must be
// compatible with the register class required by the instruction descriptor.
//
// Register live intervals: Registers must be defined only once, and must be
// defined before use.
//
[MachineVerifier] Simplify and delete LLVM_VERIFY_MACHINEINSTRS from a comment. NFC The environment variable has been unused since r228079.
2020-01-27 00:47:32 +01:00
// The machine code verifier is enabled with the command-line option
// -verify-machineinstrs.
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
//===----------------------------------------------------------------------===//
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-03 17:50:05 +01:00
#include "llvm/ADT/DenseSet.h"
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
#include "llvm/ADT/DepthFirstIterator.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/ADT/STLExtras.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-03 17:50:05 +01:00
#include "llvm/ADT/SetOperations.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/ADT/SmallPtrSet.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-03 17:50:05 +01:00
#include "llvm/ADT/SmallVector.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
Move EH-specific helper functions to a more appropriate place No functionality change is intended. llvm-svn: 254562
2015-12-03 00:06:39 +01:00
#include "llvm/Analysis/EHPersonalities.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/LiveInterval.h"
Rename LiveIntervalAnalysis.h to LiveIntervals.h Headers/Implementation files should be named after the class they declare/define. Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in favor of `class LiveIntarvals;` llvm-svn: 320546
2017-12-13 03:51:04 +01:00
#include "llvm/CodeGen/LiveIntervals.h"
Move LiveRangeCalc header to publicily available position. NFC Differential Revision: https://reviews.llvm.org/D69078 llvm-svn: 375075
2019-10-17 05:12:51 +02:00
#include "llvm/CodeGen/LiveRangeCalc.h"
LiveStacks: Rename LiveStack.{h|cpp} to LiveStacks.{h|cpp}; NFC Filenames should match the name of the class they contain. llvm-svn: 321037
2017-12-19 00:19:44 +01:00
#include "llvm/CodeGen/LiveStacks.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-03 17:50:05 +01:00
#include "llvm/CodeGen/LiveVariables.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/CodeGen/MachineBasicBlock.h"
Use pristine register info in machine code verifier. So far these registers are simply tracked as if they were live-in. llvm-svn: 78912
2009-08-13 18:19:51 +02:00
#include "llvm/CodeGen/MachineFrameInfo.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/CodeGen/MachineFunction.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-03 17:50:05 +01:00
#include "llvm/CodeGen/MachineFunctionPass.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
Add a few simple MachineVerifier checks for MachineMemOperands. llvm-svn: 83474
2009-10-07 19:36:00 +02:00
#include "llvm/CodeGen/MachineMemOperand.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/CodeGen/MachineOperand.h"
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
#include "llvm/CodeGen/MachineRegisterInfo.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SlotIndexes.h"
Add placeholder for more extensive verification of psuedo ops This initial patch doesn't actually do much useful. It's just to show where the new code goes. Once this is in, I'll extend the verification logic to check more useful properties. For those curious, the more complicated version of this patch already found one very suspicious thing. Differential Revision: https://reviews.llvm.org/D33819 llvm-svn: 304564
2017-06-02 18:36:37 +02:00
#include "llvm/CodeGen/StackMaps.h"
Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
2017-11-08 02:01:31 +01:00
#include "llvm/CodeGen/TargetInstrInfo.h"
Fix a bunch more layering of CodeGen headers that are in Target All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
2017-11-17 02:07:10 +01:00
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
Move all of the header files which are involved in modelling the LLVM IR into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
2013-01-02 12:36:10 +01:00
#include "llvm/IR/BasicBlock.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/IR/Function.h"
Move all of the header files which are involved in modelling the LLVM IR into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
2013-01-02 12:36:10 +01:00
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instructions.h"
Sink all InitializePasses.h includes This file lists every pass in LLVM, and is included by Pass.h, which is very popular. Every time we add, remove, or rename a pass in LLVM, it caused lots of recompilation. I found this fact by looking at this table, which is sorted by the number of times a file was changed over the last 100,000 git commits multiplied by the number of object files that depend on it in the current checkout: recompiles touches affected_files header 342380 95 3604 llvm/include/llvm/ADT/STLExtras.h 314730 234 1345 llvm/include/llvm/InitializePasses.h 307036 118 2602 llvm/include/llvm/ADT/APInt.h 213049 59 3611 llvm/include/llvm/Support/MathExtras.h 170422 47 3626 llvm/include/llvm/Support/Compiler.h 162225 45 3605 llvm/include/llvm/ADT/Optional.h 158319 63 2513 llvm/include/llvm/ADT/Triple.h 140322 39 3598 llvm/include/llvm/ADT/StringRef.h 137647 59 2333 llvm/include/llvm/Support/Error.h 131619 73 1803 llvm/include/llvm/Support/FileSystem.h Before this change, touching InitializePasses.h would cause 1345 files to recompile. After this change, touching it only causes 550 compiles in an incremental rebuild. Reviewers: bkramer, asbirlea, bollu, jdoerfert Differential Revision: https://reviews.llvm.org/D70211
2019-11-13 22:15:01 +01:00
#include "llvm/InitializePasses.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/MC/LaneBitmask.h"
SjLj EH could produce a machine basic block that legitimately has more than one landing pad as its successor. SjLj exception handling jumps to the correct landing pad via a switch statement that's generated right before code-gen. Loosen the constraint in the machine instruction verifier to allow for this. Note, this isn't the most rigorous check since we cannot determine where that switch statement came from. But it's marginally better than turning this check off when SjLj exceptions are used. <rdar://problem/9187612> llvm-svn: 130881
2011-05-05 00:54:05 +02:00
#include "llvm/MC/MCAsmInfo.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
Convert more assert(0)+abort() -> LLVM_UNREACHABLE, and abort()/exit() -> llvm_report_error(). llvm-svn: 75363
2009-07-11 15:10:19 +02:00
#include "llvm/Support/ErrorHandling.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Support/MathExtras.h"
Convert more assert(0)+abort() -> LLVM_UNREACHABLE, and abort()/exit() -> llvm_report_error(). llvm-svn: 75363
2009-07-11 15:10:19 +02:00
#include "llvm/Support/raw_ostream.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-03 17:50:05 +01:00
#include "llvm/Target/TargetMachine.h"
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
#include <algorithm>
#include <cassert>
#include <cstddef>
#include <cstdint>
#include <iterator>
#include <string>
#include <utility>
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
using namespace llvm;
namespace {
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
struct MachineVerifier {
MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
MachineVerifier: Add parameter to choose if MachineFunction::verify() aborts The abort on error behaviour is unpractical for debugger and unittest usage. llvm-svn: 260904
2016-02-15 20:25:31 +01:00
unsigned verify(MachineFunction &MF);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
Pass *const PASS;
Pass a Banner argument to the machine code verifier both from createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. llvm-svn: 122113
2010-12-18 01:06:56 +01:00
const char *Banner;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
const MachineFunction *MF;
const TargetMachine *TM;
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. llvm-svn: 133944
2011-06-27 23:26:13 +02:00
const TargetInstrInfo *TII;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
const TargetRegisterInfo *TRI;
const MachineRegisterInfo *MRI;
unsigned foundErrors;
[GlobalISel] Verify RegBankSelected MF property. RegBankSelected functions shouldn't have any generic virtual register not assigned to a bank. Verify that. llvm-svn: 277476
2016-08-02 18:17:15 +02:00
// Avoid querying the MachineFunctionProperties for each operand.
bool isFunctionRegBankSelected;
[GlobalISel] Verify Selected MF property. After instruction selection, there should be no pre-isel generic instructions remaining, nor should generic virtual registers be used. Verify that. llvm-svn: 277483
2016-08-02 18:49:22 +02:00
bool isFunctionSelected;
[GlobalISel] Verify RegBankSelected MF property. RegBankSelected functions shouldn't have any generic virtual register not assigned to a bank. Verify that. llvm-svn: 277476
2016-08-02 18:17:15 +02:00
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
using RegVector = SmallVector<unsigned, 16>;
using RegMaskVector = SmallVector<const uint32_t *, 4>;
using RegSet = DenseSet<unsigned>;
using RegMap = DenseMap<unsigned, const MachineInstr *>;
using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
[machineverifier] Detect PHI's that are preceeded by non-PHI's If present, PHI nodes must appear before non-PHI nodes in a basic block. The register allocator relies on this and will fail to eliminate PHI's that do not meet this requirement. llvm-svn: 343731
2018-10-04 00:05:31 +02:00
const MachineInstr *FirstNonPHI;
Verify that terminators follow non-terminators. This exposes a -segmented-stacks bug. llvm-svn: 140429
2011-09-24 00:45:39 +02:00
const MachineInstr *FirstTerminator;
Add CFG checks to MachineVerifier. Verify that the predecessor and successor lists are consistent and free of duplicates. llvm-svn: 162223
2012-08-20 22:52:06 +02:00
BlockSet FunctionBlocks;
Verify that terminators follow non-terminators. This exposes a -segmented-stacks bug. llvm-svn: 140429
2011-09-24 00:45:39 +02:00
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
BitVector regsReserved;
RegSet regsLive;
Update the machine code verifier to keep up with the scavenger. * Cleaner handling of <undef>. * <def> takes precedence over <def,dead>. * Implement the OK-to-redefine-a-register-that-was- live-in-but-has-not-been-used-before rule. llvm-svn: 78467
2009-08-08 15:19:25 +02:00
RegVector regsDefined, regsDead, regsKilled;
Handle regmasks in the machine code verifier. llvm-svn: 151607
2012-02-28 02:42:41 +01:00
RegMaskVector regMasks;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
Verify slot index ordering. The slot indexes must be monotonically increasing through the function. llvm-svn: 123324
2011-01-12 22:27:48 +01:00
SlotIndex lastIndex;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
// Add Reg and any sub-registers to RV
void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
RV.push_back(Reg);
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isPhysicalRegister(Reg))
[MCRegInfo] Add forward sub and super register iterators. (NFC) This patch adds forward iterators mc_difflist_iterator, mc_subreg_iterator and mc_superreg_iterator, based on the existing DiffListIterator. Those are used to provide iterator ranges over sub- and super-register from TRI, which are slightly more convenient than the existing MCSubRegIterator/MCSuperRegIterator. Unfortunately, it duplicates a bit of functionality, but the new iterators are a bit more convenient (and can be used with various existing iterator utilities) and should probably replace the old iterators in the future. This patch updates some existing users. Reviewers: evandro, qcolombet, paquette, MatzeB, arsenm Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D70565
2019-12-05 10:16:08 +01:00
for (const MCPhysReg &SubReg : TRI->subregs(Reg))
RV.push_back(SubReg);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
struct BBInfo {
// Is this MBB reachable from the MF entry point?
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
bool reachable = false;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
// Vregs that must be live in because they are used without being
// defined. Map value is the user.
RegMap vregsLiveIn;
// Regs killed in MBB. They may be defined again, and will then be in both
// regsKilled and regsLiveOut.
RegSet regsKilled;
// Regs defined in MBB and live out. Note that vregs passing through may
// be live out without being mentioned here.
RegSet regsLiveOut;
// Vregs that pass through MBB untouched. This set is disjoint from
// regsKilled and regsLiveOut.
RegSet vregsPassed;
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
// Vregs that must pass through MBB because they are needed by a successor
// block. This set is disjoint from regsLiveOut.
RegSet vregsRequired;
Add CFG checks to MachineVerifier. Verify that the predecessor and successor lists are consistent and free of duplicates. llvm-svn: 162223
2012-08-20 22:52:06 +02:00
// Set versions of block's predecessor and successor lists.
BlockSet Preds, Succs;
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
BBInfo() = default;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
// Add register to vregsPassed if it belongs there. Return true if
// anything changed.
bool addPassed(unsigned Reg) {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (!Register::isVirtualRegister(Reg))
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
return false;
if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
return false;
return vregsPassed.insert(Reg).second;
}
// Same for a full set.
bool addPassed(const RegSet &RS) {
bool changed = false;
for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
if (addPassed(*I))
changed = true;
return changed;
}
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
// Add register to vregsRequired if it belongs there. Return true if
// anything changed.
bool addRequired(unsigned Reg) {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (!Register::isVirtualRegister(Reg))
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
return false;
if (regsLiveOut.count(Reg))
return false;
return vregsRequired.insert(Reg).second;
}
// Same for a full set.
bool addRequired(const RegSet &RS) {
bool changed = false;
for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
if (addRequired(*I))
changed = true;
return changed;
}
// Same for a full map.
bool addRequired(const RegMap &RM) {
bool changed = false;
for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
if (addRequired(I->first))
changed = true;
return changed;
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
// Live-out registers are either in regsLiveOut or vregsPassed.
bool isLiveOut(unsigned Reg) const {
return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
}
};
// Extra register info per MBB.
DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
bool isReserved(unsigned Reg) {
Enforce stricter rules in machine code verifier. Implicit operands no longer get a free pass: Imp-use requires a live register and imp-def requires a dead register. There is also no special rule allowing redefinition of a sub-register when the super-register is live. The super register must have imp-kill+imp-def operands instead. llvm-svn: 78090
2009-08-04 21:18:01 +02:00
return Reg < regsReserved.size() && regsReserved.test(Reg);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
ARM: Compute MaxCallFrame size early This exposes a method in MachineFrameInfo that calculates MaxCallFrameSize and calls it after instruction selection in the ARM target. This avoids ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame() giving different answers in early/late phases of codegen. The testcase shows a particular nasty example result of that where we would fail to properly align an alloca. Differential Revision: https://reviews.llvm.org/D32622 llvm-svn: 302303
2017-05-06 00:04:05 +02:00
bool isAllocatable(unsigned Reg) const {
return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
Rename ExpandISelPseudo->FinalizeISel, delay register reservation This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are calls or stack objects in the frame or not, which could have been introduced by legalization. Patch by Matthias Braun llvm-svn: 363757
2019-06-19 02:25:39 +02:00
!regsReserved.test(Reg);
Update MachineVerifier to check the new physreg live-in rules. llvm-svn: 150496
2012-02-14 20:17:48 +01:00
}
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
// Analysis information if available
LiveVariables *LiveVars;
Verify that live intervals are connected. If there are multiple connected components, each should get its own virtual register. llvm-svn: 117407
2010-10-27 00:36:07 +02:00
LiveIntervals *LiveInts;
Add basic LiveStacks verification. When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
2010-11-01 20:49:52 +01:00
LiveStacks *LiveStks;
Teach MachineBasicBlock::print() to annotate instructions and blocks with SlotIndexes when available. llvm-svn: 117392
2010-10-26 22:21:46 +02:00
SlotIndexes *Indexes;
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
void visitMachineFunctionBefore();
void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
void visitMachineBundleBefore(const MachineInstr *MI);
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
GlobalISel: Verify g_select Factor the common vector element consistency check many instructions need out, although this makes the error messages worse. llvm-svn: 353112
2019-02-05 00:29:16 +01:00
bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
void verifyPreISelGenericInstruction(const MachineInstr *MI);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
void visitMachineInstrBefore(const MachineInstr *MI);
void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
void visitMachineInstrAfter(const MachineInstr *MI);
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
void visitMachineBundleAfter(const MachineInstr *MI);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
void visitMachineFunctionAfter();
void report(const char *msg, const MachineFunction *MF);
void report(const char *msg, const MachineBasicBlock *MBB);
void report(const char *msg, const MachineInstr *MI);
[MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visitMachineInstrBefore This is an NFC pre-commit for the following "Checking that generic instrs have LLTs on all vregs" commit. This overloads MachineOperand::print to make it possible to print LLTs with standalone machine operands. This also overloads MachineVerifier::print(...MachineOperand...) with an optional LLT using the newly introduced MachineOperand::print variant; no actual calls added. This also refactors MachineVerifier::visitMachineInstrBefore in the parts dealing with all generic instructions (checking Selected property, LLTs, and phys regs). llvm-svn: 331693
2018-05-08 00:31:12 +02:00
void report(const char *msg, const MachineOperand *MO, unsigned MONum,
LLT MOVRegType = LLT{});
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
void report_context(const LiveInterval &LI) const;
MachineVerifier: Fix printing nonsense for physical registers llvm-svn: 276677
2016-07-25 21:39:01 +02:00
void report_context(const LiveRange &LR, unsigned VRegUnit,
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
LaneBitmask LaneMask) const;
void report_context(const LiveRange::Segment &S) const;
void report_context(const VNInfo &VNI) const;
MachineVerifier: Use report_context() instead of ad-hoc messages. llvm-svn: 259457
2016-02-02 03:44:25 +01:00
void report_context(SlotIndex Pos) const;
[MachineVerifier] Include offending register in allocatable live-in error msg. This patch adds a convenience report() method for physical registers and uses it to print the offending register with the 'MBB has allocatable live-in' error. Reviewers: MatzeB, rtereshin, dsanders Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D55946 llvm-svn: 350630
2019-01-08 16:16:23 +01:00
void report_context(MCPhysReg PhysReg) const;
MachineVerifier: Use report_context() instead of ad-hoc messages. llvm-svn: 259457
2016-02-02 03:44:25 +01:00
void report_context_liverange(const LiveRange &LR) const;
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
void report_context_lanemask(LaneBitmask LaneMask) const;
MachineVerifier: Fix error reporting. Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
2016-05-11 23:31:39 +02:00
void report_context_vreg(unsigned VReg) const;
[CodeGen] Fix inconsistent declaration parameter name llvm-svn: 337200
2018-07-16 20:51:40 +02:00
void report_context_vreg_regunit(unsigned VRegOrUnit) const;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
Verify the consistency of inline asm operands. The operands on an INLINEASM machine instruction are divided into groups headed by immediate flag operands. Verify this structure. Extract verifyTiedOperands(), and only call it for non-inlineasm instructions. llvm-svn: 162849
2012-08-29 20:11:05 +02:00
void verifyInlineAsm(const MachineInstr *MI);
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
void checkLiveness(const MachineOperand *MO, unsigned MONum);
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
[CodeGen] Fix inconsistent declaration parameter name llvm-svn: 337200
2018-07-16 20:51:40 +02:00
SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
LaneBitmask LaneMask = LaneBitmask::getNone());
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
[CodeGen] Fix inconsistent declaration parameter name llvm-svn: 337200
2018-07-16 20:51:40 +02:00
SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
[MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs Summary: Consider an instruction that has multiple defs of the same vreg, but defining different subregs: %7.sub1:rc, dead %7.sub2:rc = inst Calling checkLivenessAtDef for the live interval associated with %7 incorrectly reported "live range continues after a dead def". The live range for %7 has a dead def at the slot index for "inst" even if the live range continues (given that there are later uses of %7.sub1). This patch adjusts MachineVerifier::checkLivenessAtDef to allow dead subregister definitions, unless we are checking a subrange (when tracking subregister liveness). A limitation is that we do not detect the situation when the live range continues past an instruction that defines the full virtual register by multiple dead subreg defines. I also removed some dead code related to physical register in checkLivenessAtDef. Wwe only call that method for virtual registers, so I added an assertion instead. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52237 llvm-svn: 342618
2018-09-20 08:59:18 +02:00
bool SubRangeCheck = false,
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
LaneBitmask LaneMask = LaneBitmask::getNone());
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
void markReachable(const MachineBasicBlock *MBB);
Remove livein checks from machine code verifier. A phi operand that is implicitly defined in a predecessor becomes an undefined register after phi elimination. This causes a lot of false positives when the verifier is checking if live-in registers are live-out from all predecessors. Removing the verifier checks seems like a better solution than insisting on IMPLICIT_DEF instructions in predecessor blocks. llvm-svn: 92769
2010-01-05 21:59:36 +01:00
void calcRegsPassed();
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
void checkPHIOps(const MachineBasicBlock &MBB);
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
void calcRegsRequired();
void verifyLiveVariables();
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
void verifyLiveIntervals();
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
void verifyLiveInterval(const LiveInterval&);
LiveInterval: Add support to track liveness of subregisters. This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
2014-12-10 02:12:10 +01:00
void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
LaneBitmask);
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
void verifyLiveRangeSegment(const LiveRange&,
LiveInterval: Add support to track liveness of subregisters. This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
2014-12-10 02:12:10 +01:00
const LiveRange::const_iterator I, unsigned,
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
LaneBitmask);
void verifyLiveRange(const LiveRange&, unsigned,
LaneBitmask LaneMask = LaneBitmask::getNone());
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
void verifyStackFrame();
MachineVerifier: Check that SlotIndex MBBIndexList is sorted. This introduces a check that the MBBIndexList is sorted as proposed in http://reviews.llvm.org/D12443 but split up into a separate commit. llvm-svn: 247166
2015-09-09 19:49:46 +02:00
void verifySlotIndexes() const;
Add MachineVerifier check for AllVRegsAllocated MachineFunctionProperty Summary: Check that any function that has the property set is free of virtual register operands. Also, it is actually VirtRegMap (and not the register allocators) that acutally remove the VReg operands (except for RegAllocFast). Reviewers: qcolombet Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: http://reviews.llvm.org/D18535 llvm-svn: 264755
2016-03-29 19:40:22 +02:00
void verifyProperties(const MachineFunction &MF);
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
};
struct MachineVerifierPass : public MachineFunctionPass {
static char ID; // Pass ID, replacement for typeid
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
[CodeGen] Let MachineVerifierPass own its banner string llvm-svn: 224041
2014-12-11 20:41:51 +01:00
const std::string Banner;
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
[MachineVerifier] Drop a spurious const As of r298987 the argument is a value that we std::move, so it shouldn't be const anymore. llvm-svn: 298999
2017-03-29 17:25:06 +02:00
MachineVerifierPass(std::string banner = std::string())
[MachineVerifier] Avoid reference to nullptr Instantiation of the MachineVerifierPass through PassInfo::getNormalCtor would yield a segfault since the default constructor of the MachineVerifierPass takes a reference to nullptr. Patch by Simone Pellegrini. Differential Revision: https://reviews.llvm.org/D31387 llvm-svn: 298987
2017-03-29 11:08:25 +02:00
: MachineFunctionPass(ID), Banner(std::move(banner)) {
Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
2010-10-19 19:21:58 +02:00
initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
}
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
[C++11] Add 'override' keyword to virtual methods that override their base class. llvm-svn: 203220
2014-03-07 10:26:03 +01:00
void getAnalysisUsage(AnalysisUsage &AU) const override {
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
[C++11] Add 'override' keyword to virtual methods that override their base class. llvm-svn: 203220
2014-03-07 10:26:03 +01:00
bool runOnMachineFunction(MachineFunction &MF) override {
MachineVerifier: Add parameter to choose if MachineFunction::verify() aborts The abort on error behaviour is unpractical for debugger and unittest usage. llvm-svn: 260904
2016-02-15 20:25:31 +01:00
unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
if (FoundErrors)
report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
return false;
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
};
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
} // end anonymous namespace
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
char MachineVerifierPass::ID = 0;
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API. llvm-svn: 111815
2010-08-23 19:52:01 +02:00
INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
Now with fewer extraneous semicolons! llvm-svn: 115996
2010-10-08 00:25:06 +02:00
"Verify generated machine code", false, false)
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
[CodeGen] Let MachineVerifierPass own its banner string llvm-svn: 224041
2014-12-11 20:41:51 +01:00
FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
Pass a Banner argument to the machine code verifier both from createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. llvm-svn: 122113
2010-12-18 01:06:56 +01:00
return new MachineVerifierPass(Banner);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
MachineVerifier: Add parameter to choose if MachineFunction::verify() aborts The abort on error behaviour is unpractical for debugger and unittest usage. llvm-svn: 260904
2016-02-15 20:25:31 +01:00
bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
const {
MachineFunction &MF = const_cast<MachineFunction&>(*this);
unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
if (AbortOnErrors && FoundErrors)
report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
return FoundErrors == 0;
Add MachineFunction::verify() to call the machine code verifier directly. llvm-svn: 88706
2009-11-13 22:56:09 +01:00
}
MachineVerifier: Check that SlotIndex MBBIndexList is sorted. This introduces a check that the MBBIndexList is sorted as proposed in http://reviews.llvm.org/D12443 but split up into a separate commit. llvm-svn: 247166
2015-09-09 19:49:46 +02:00
void MachineVerifier::verifySlotIndexes() const {
if (Indexes == nullptr)
return;
// Ensure the IdxMBB list is sorted by slot indexes.
SlotIndex Last;
for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
E = Indexes->MBBIndexEnd(); I != E; ++I) {
assert(!Last.isValid() || I->first > Last);
Last = I->first;
}
}
Add MachineVerifier check for AllVRegsAllocated MachineFunctionProperty Summary: Check that any function that has the property set is free of virtual register operands. Also, it is actually VirtRegMap (and not the register allocators) that acutally remove the VReg operands (except for RegAllocFast). Reviewers: qcolombet Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: http://reviews.llvm.org/D18535 llvm-svn: 264755
2016-03-29 19:40:22 +02:00
void MachineVerifier::verifyProperties(const MachineFunction &MF) {
// If a pass has introduced virtual registers without clearing the
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
2016-08-25 03:27:13 +02:00
// NoVRegs property (or set it without allocating the vregs)
Add MachineVerifier check for AllVRegsAllocated MachineFunctionProperty Summary: Check that any function that has the property set is free of virtual register operands. Also, it is actually VirtRegMap (and not the register allocators) that acutally remove the VReg operands (except for RegAllocFast). Reviewers: qcolombet Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: http://reviews.llvm.org/D18535 llvm-svn: 264755
2016-03-29 19:40:22 +02:00
// then report an error.
if (MF.getProperties().hasProperty(
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
2016-08-25 03:27:13 +02:00
MachineFunctionProperties::Property::NoVRegs) &&
MRI->getNumVirtRegs())
report("Function has NoVRegs property but there are VReg operands", &MF);
Add MachineVerifier check for AllVRegsAllocated MachineFunctionProperty Summary: Check that any function that has the property set is free of virtual register operands. Also, it is actually VirtRegMap (and not the register allocators) that acutally remove the VReg operands (except for RegAllocFast). Reviewers: qcolombet Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: http://reviews.llvm.org/D18535 llvm-svn: 264755
2016-03-29 19:40:22 +02:00
}
MachineVerifier: Add parameter to choose if MachineFunction::verify() aborts The abort on error behaviour is unpractical for debugger and unittest usage. llvm-svn: 260904
2016-02-15 20:25:31 +01:00
unsigned MachineVerifier::verify(MachineFunction &MF) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
foundErrors = 0;
this->MF = &MF;
TM = &MF.getTarget();
Access subtarget specific variables off of the MachineFunction's cached subtarget and not the TargetMachine. llvm-svn: 219668
2014-10-14 09:00:33 +02:00
TII = MF.getSubtarget().getInstrInfo();
TRI = MF.getSubtarget().getRegisterInfo();
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
MRI = &MF.getRegInfo();
[GlobalISel] Print/Parse FailedISel MachineFunction property FailedISel MachineFunction property is part of the CodeGen pipeline state as much as every other property, notably, Legalized, RegBankSelected, and Selected. Let's make that part of the state also serializable / de-serializable, so if GlobalISel aborts on some of the functions of a large module, but not the others, it could be easily seen and the state of the pipeline could be maintained through llc's invocations with -stop-after / -start-after. To make MIR printable and generally to not to break it too much too soon, this patch also defers cleaning up the vreg -> LLT map until ResetMachineFunctionPass. To make MIR with FailedISel: true also machine verifiable, machine verifier is changed so it treats a MIR-module as non-regbankselected and non-selected if there is FailedISel property set. Reviewers: qcolombet, ab Reviewed By: dsanders Subscribers: javed.absar, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42877 llvm-svn: 326343
2018-02-28 18:55:45 +01:00
const bool isFunctionFailedISel = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::FailedISel);
[globalisel][verifier] Run the MachineVerifier from IRTranslator onwards -verify-machineinstrs inserts the MachineVerifier after every MachineInstr-based pass. However, GlobalISel creates MachineInstr-based passes earlier than DAGISel and the corresponding verifiers are not being added. This patch fixes that. If GlobalISel triggers the fallback path then the MIR can be left in a bad state that is going to be cleared by ResetMachineFunctions. In this situation verifying between GlobalISel passes will prevent the fallback path from recovering from this. As a result, we bail out of verifying a function if the FailedISel attribute is present. llvm-svn: 343613
2018-10-02 19:56:58 +02:00
// If we're mid-GlobalISel and we already triggered the fallback path then
// it's expected that the MIR is somewhat broken but that's ok since we'll
// reset it and clear the FailedISel attribute in ResetMachineFunctions.
if (isFunctionFailedISel)
return foundErrors;
[MachineVerifier] Simplify and delete LLVM_VERIFY_MACHINEINSTRS from a comment. NFC The environment variable has been unused since r228079.
2020-01-27 00:47:32 +01:00
isFunctionRegBankSelected = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::RegBankSelected);
isFunctionSelected = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Selected);
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. llvm-svn: 206142
2014-04-14 02:51:57 +02:00
LiveVars = nullptr;
LiveInts = nullptr;
LiveStks = nullptr;
Indexes = nullptr;
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
if (PASS) {
Add basic verification of LiveIntervals. We verify that the LiveInterval is live at uses and defs, and that all instructions have a SlotIndex. Stuff we don't check yet: - Is the LiveInterval minimal? - Do all defs correspond to instructions or phis? - Do all defs dominate all their live ranges? - Are all live ranges continually reachable from their def? llvm-svn: 110386
2010-08-06 00:32:21 +02:00
LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
Don't verify LiveVariables if LiveIntervals is available. LiveVariables becomes horribly wrong while the coalescer is running, but the analysis is not zapped until after the coalescer pass has run. This causes tons of false reports when calling verify form the coalescer. llvm-svn: 110402
2010-08-06 01:51:26 +02:00
// We don't want to verify LiveVariables if LiveIntervals is available.
if (!LiveInts)
LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
Add basic LiveStacks verification. When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
2010-11-01 20:49:52 +01:00
LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
Teach MachineBasicBlock::print() to annotate instructions and blocks with SlotIndexes when available. llvm-svn: 117392
2010-10-26 22:21:46 +02:00
Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
}
MachineVerifier: Check that SlotIndex MBBIndexList is sorted. This introduces a check that the MBBIndexList is sorted as proposed in http://reviews.llvm.org/D12443 but split up into a separate commit. llvm-svn: 247166
2015-09-09 19:49:46 +02:00
verifySlotIndexes();
Add MachineVerifier check for AllVRegsAllocated MachineFunctionProperty Summary: Check that any function that has the property set is free of virtual register operands. Also, it is actually VirtRegMap (and not the register allocators) that acutally remove the VReg operands (except for RegAllocFast). Reviewers: qcolombet Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: http://reviews.llvm.org/D18535 llvm-svn: 264755
2016-03-29 19:40:22 +02:00
verifyProperties(MF);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
visitMachineFunctionBefore();
for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
MFI!=MFE; ++MFI) {
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
visitMachineBasicBlockBefore(&*MFI);
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
// Keep track of the current bundle header.
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. llvm-svn: 206142
2014-04-14 02:51:57 +02:00
const MachineInstr *CurBundle = nullptr;
Verify bundle flags for consistency in MachineVerifier. The new bidirectional bundle flags are redundant, so inadvertent bundle tearing can be detected in the machine code verifier. llvm-svn: 170463
2012-12-18 23:55:07 +01:00
// Do we expect the next instruction to be part of the same bundle?
bool InBundle = false;
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
2011-12-14 03:11:42 +01:00
for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
if (MBBI->getParent() != &*MFI) {
ADT: Remove external uses of ilist_iterator, NFC Delete the dead code for Write(ilist_iterator) in the IR Verifier, inline report(ilist_iterator) at its call sites in the MachineVerifier, and use simple_ilist<>::iterator in SymbolTableListTraits. The only remaining reference to ilist_iterator outside of the ilist implementation is from MachineInstrBundleIterator. I'll get rid of that in a follow-up. llvm-svn: 280565
2016-09-03 03:22:56 +02:00
report("Bad instruction parent pointer", &*MFI);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "Instruction: " << *MBBI;
Verify that machine instruction parent pointers are consistent. llvm-svn: 123322
2011-01-12 22:27:41 +01:00
continue;
}
Verify bundle flags for consistency in MachineVerifier. The new bidirectional bundle flags are redundant, so inadvertent bundle tearing can be detected in the machine code verifier. llvm-svn: 170463
2012-12-18 23:55:07 +01:00
// Check for consistent bundle flags.
if (InBundle && !MBBI->isBundledWithPred())
report("Missing BundledPred flag, "
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
"BundledSucc was set on predecessor",
&*MBBI);
Verify bundle flags for consistency in MachineVerifier. The new bidirectional bundle flags are redundant, so inadvertent bundle tearing can be detected in the machine code verifier. llvm-svn: 170463
2012-12-18 23:55:07 +01:00
if (!InBundle && MBBI->isBundledWithPred())
report("BundledPred flag is set, "
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
"but BundledSucc not set on predecessor",
&*MBBI);
Verify bundle flags for consistency in MachineVerifier. The new bidirectional bundle flags are redundant, so inadvertent bundle tearing can be detected in the machine code verifier. llvm-svn: 170463
2012-12-18 23:55:07 +01:00
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
// Is this a bundle header?
if (!MBBI->isInsideBundle()) {
if (CurBundle)
visitMachineBundleAfter(CurBundle);
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
CurBundle = &*MBBI;
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
visitMachineBundleBefore(CurBundle);
} else if (!CurBundle)
ADT: Remove external uses of ilist_iterator, NFC Delete the dead code for Write(ilist_iterator) in the IR Verifier, inline report(ilist_iterator) at its call sites in the MachineVerifier, and use simple_ilist<>::iterator in SymbolTableListTraits. The only remaining reference to ilist_iterator outside of the ilist implementation is from MachineInstrBundleIterator. I'll get rid of that in a follow-up. llvm-svn: 280565
2016-09-03 03:22:56 +02:00
report("No bundle header", &*MBBI);
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
visitMachineInstrBefore(&*MBBI);
MachineVerifier: Don't crash if MachineOperand has no parent If you somehow added a MachineOperand to an instruction that did not have the parent set, the verifier would crash since it attempts to use the operand's parent. llvm-svn: 236249
2015-04-30 21:35:41 +02:00
for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
const MachineInstr &MI = *MBBI;
const MachineOperand &Op = MI.getOperand(I);
if (Op.getParent() != &MI) {
Fix typo llvm-svn: 236283
2015-05-01 01:20:56 +02:00
// Make sure to use correct addOperand / RemoveOperand / ChangeTo
MachineVerifier: Don't crash if MachineOperand has no parent If you somehow added a MachineOperand to an instruction that did not have the parent set, the verifier would crash since it attempts to use the operand's parent. llvm-svn: 236249
2015-04-30 21:35:41 +02:00
// functions when replacing operands of a MachineInstr.
report("Instruction has operand with wrong parent set", &MI);
}
visitMachineOperand(&Op, I);
}
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
visitMachineInstrAfter(&*MBBI);
Verify bundle flags for consistency in MachineVerifier. The new bidirectional bundle flags are redundant, so inadvertent bundle tearing can be detected in the machine code verifier. llvm-svn: 170463
2012-12-18 23:55:07 +01:00
// Was this the last bundled instruction?
InBundle = MBBI->isBundledWithSucc();
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
if (CurBundle)
visitMachineBundleAfter(CurBundle);
Verify bundle flags for consistency in MachineVerifier. The new bidirectional bundle flags are redundant, so inadvertent bundle tearing can be detected in the machine code verifier. llvm-svn: 170463
2012-12-18 23:55:07 +01:00
if (InBundle)
report("BundledSucc flag set on last instruction in block", &MFI->back());
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
visitMachineBasicBlockAfter(&*MFI);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
visitMachineFunctionAfter();
Clean out per-function data after the machine code verifier is done with it. Also don't dereference old pointers after they have been deleted causing random crashes when enabling the machine code verifier. Ahem... I have not included a test case for the crash. It hapened when enabling the verifier on CodeGen/X86/2009-08-06-branchfolder-crash.ll. The crash depends on an MBB being allocated at the same address as a previously deleted MBB. I don't think that can be reproduced reliably. llvm-svn: 78472
2009-08-08 17:34:50 +02:00
// Clean up.
regsLive.clear();
regsDefined.clear();
regsDead.clear();
regsKilled.clear();
Handle regmasks in the machine code verifier. llvm-svn: 151607
2012-02-28 02:42:41 +01:00
regMasks.clear();
Clean out per-function data after the machine code verifier is done with it. Also don't dereference old pointers after they have been deleted causing random crashes when enabling the machine code verifier. Ahem... I have not included a test case for the crash. It hapened when enabling the verifier on CodeGen/X86/2009-08-06-branchfolder-crash.ll. The crash depends on an MBB being allocated at the same address as a previously deleted MBB. I don't think that can be reproduced reliably. llvm-svn: 78472
2009-08-08 17:34:50 +02:00
MBBInfoMap.clear();
MachineVerifier: Add parameter to choose if MachineFunction::verify() aborts The abort on error behaviour is unpractical for debugger and unittest usage. llvm-svn: 260904
2016-02-15 20:25:31 +01:00
return foundErrors;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
remove some dead print method variants. llvm-svn: 79801
2009-08-23 03:03:30 +02:00
void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
assert(MF);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << '\n';
Pass a Banner argument to the machine code verifier both from createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. llvm-svn: 122113
2010-12-18 01:06:56 +01:00
if (!foundErrors++) {
if (Banner)
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "# " << Banner << '\n';
MachineVerifier: print list of live intervals if available llvm-svn: 252549
2015-11-10 00:59:23 +01:00
if (LiveInts != nullptr)
LiveInts->print(errs());
else
MF->print(errs(), Indexes);
Pass a Banner argument to the machine code verifier both from createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. llvm-svn: 122113
2010-12-18 01:06:56 +01:00
}
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "*** Bad machine code: " << msg << " ***\n"
Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
2012-08-22 08:07:19 +02:00
<< "- function: " << MF->getName() << "\n";
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
Whitespace and formatting. llvm-svn: 83285
2009-10-04 20:18:39 +02:00
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
assert(MBB);
report(msg, MBB->getParent());
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 18:18:51 +01:00
errs() << "- basic block: " << printMBBReference(*MBB) << ' '
<< MBB->getName() << " (" << (const void *)MBB << ')';
Teach MachineBasicBlock::print() to annotate instructions and blocks with SlotIndexes when available. llvm-svn: 117392
2010-10-26 22:21:46 +02:00
if (Indexes)
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << " [" << Indexes->getMBBStartIdx(MBB)
Teach MachineBasicBlock::print() to annotate instructions and blocks with SlotIndexes when available. llvm-svn: 117392
2010-10-26 22:21:46 +02:00
<< ';' << Indexes->getMBBEndIdx(MBB) << ')';
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << '\n';
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
Whitespace and formatting. llvm-svn: 83285
2009-10-04 20:18:39 +02:00
void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
assert(MI);
report(msg, MI->getParent());
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "- instruction: ";
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
2016-02-27 07:40:41 +01:00
if (Indexes && Indexes->hasIndex(*MI))
errs() << Indexes->getInstructionIndex(*MI) << '\t';
MachineVerifier: MI::print has no TargetMachine overload The code was passing a target machine pointer which degraded to a true operand to SkipOppers. llvm-svn: 252550
2015-11-10 00:59:25 +01:00
MI->print(errs(), /*SkipOpers=*/true);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
[MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visitMachineInstrBefore This is an NFC pre-commit for the following "Checking that generic instrs have LLTs on all vregs" commit. This overloads MachineOperand::print to make it possible to print LLTs with standalone machine operands. This also overloads MachineVerifier::print(...MachineOperand...) with an optional LLT using the newly introduced MachineOperand::print variant; no actual calls added. This also refactors MachineVerifier::visitMachineInstrBefore in the parts dealing with all generic instructions (checking Selected property, LLTs, and phys regs). llvm-svn: 331693
2018-05-08 00:31:12 +02:00
void MachineVerifier::report(const char *msg, const MachineOperand *MO,
unsigned MONum, LLT MOVRegType) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
assert(MO);
report(msg, MO->getParent());
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "- operand " << MONum << ": ";
[MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visitMachineInstrBefore This is an NFC pre-commit for the following "Checking that generic instrs have LLTs on all vregs" commit. This overloads MachineOperand::print to make it possible to print LLTs with standalone machine operands. This also overloads MachineVerifier::print(...MachineOperand...) with an optional LLT using the newly introduced MachineOperand::print variant; no actual calls added. This also refactors MachineVerifier::visitMachineInstrBefore in the parts dealing with all generic instructions (checking Selected property, LLTs, and phys regs). llvm-svn: 331693
2018-05-08 00:31:12 +02:00
MO->print(errs(), MOVRegType, TRI);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "\n";
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
MachineVerifier: Use report_context() instead of ad-hoc messages. llvm-svn: 259457
2016-02-02 03:44:25 +01:00
void MachineVerifier::report_context(SlotIndex Pos) const {
errs() << "- at: " << Pos << '\n';
}
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
void MachineVerifier::report_context(const LiveInterval &LI) const {
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "- interval: " << LI << '\n';
Add report() functions that take a LiveInterval argument. llvm-svn: 161178
2012-08-02 16:31:49 +02:00
}
MachineVerifier: Fix printing nonsense for physical registers llvm-svn: 276677
2016-07-25 21:39:01 +02:00
void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
LaneBitmask LaneMask) const {
MachineVerifier: Use report_context() instead of ad-hoc messages. llvm-svn: 259457
2016-02-02 03:44:25 +01:00
report_context_liverange(LR);
MachineVerifier: Fix printing nonsense for physical registers llvm-svn: 276677
2016-07-25 21:39:01 +02:00
report_context_vreg_regunit(VRegUnit);
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if (LaneMask.any())
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report_context_lanemask(LaneMask);
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
}
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
void MachineVerifier::report_context(const LiveRange::Segment &S) const {
errs() << "- segment: " << S << '\n';
}
void MachineVerifier::report_context(const VNInfo &VNI) const {
errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
}
MachineVerifier: Use report_context() instead of ad-hoc messages. llvm-svn: 259457
2016-02-02 03:44:25 +01:00
void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
errs() << "- liverange: " << LR << '\n';
}
[MachineVerifier] Include offending register in allocatable live-in error msg. This patch adds a convenience report() method for physical registers and uses it to print the offending register with the 'MBB has allocatable live-in' error. Reviewers: MatzeB, rtereshin, dsanders Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D55946 llvm-svn: 350630
2019-01-08 16:16:23 +01:00
void MachineVerifier::report_context(MCPhysReg PReg) const {
errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
}
MachineVerifier: Fix error reporting. Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
2016-05-11 23:31:39 +02:00
void MachineVerifier::report_context_vreg(unsigned VReg) const {
[CodeGen] Rename functions PrintReg* to printReg* LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
2017-11-28 13:42:37 +01:00
errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
MachineVerifier: Fix error reporting. Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
2016-05-11 23:31:39 +02:00
}
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isVirtualRegister(VRegOrUnit)) {
MachineVerifier: Fix error reporting. Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
2016-05-11 23:31:39 +02:00
report_context_vreg(VRegOrUnit);
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
} else {
[CodeGen] Rename functions PrintReg* to printReg* LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
2017-11-28 13:42:37 +01:00
errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
}
}
void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
}
Whitespace and formatting. llvm-svn: 83285
2009-10-04 20:18:39 +02:00
void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
BBInfo &MInfo = MBBInfoMap[MBB];
if (!MInfo.reachable) {
MInfo.reachable = true;
for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
SuE = MBB->succ_end(); SuI != SuE; ++SuI)
markReachable(*SuI);
}
}
Whitespace and formatting. llvm-svn: 83285
2009-10-04 20:18:39 +02:00
void MachineVerifier::visitMachineFunctionBefore() {
Verify slot index ordering. The slot indexes must be monotonically increasing through the function. llvm-svn: 123324
2011-01-12 22:27:48 +01:00
lastIndex = SlotIndex();
ARM: Compute MaxCallFrame size early This exposes a method in MachineFrameInfo that calculates MaxCallFrameSize and calls it after instruction selection in the ARM target. This avoids ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame() giving different answers in early/late phases of codegen. The testcase shows a particular nasty example result of that where we would fail to properly align an alloca. Differential Revision: https://reviews.llvm.org/D32622 llvm-svn: 302303
2017-05-06 00:04:05 +02:00
regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
: TRI->getReservedRegs(*MF);
Enforce stricter rules in machine code verifier. Implicit operands no longer get a free pass: Imp-use requires a live register and imp-def requires a dead register. There is also no special rule allowing redefinition of a sub-register when the super-register is live. The super register must have imp-kill+imp-def operands instead. llvm-svn: 78090
2009-08-04 21:18:01 +02:00
MIR: Allow parsing of empty machine functions If you run llc -stop-after=codegenprepare and feed the resulting MIR to llc -start-after=codegenprepare, you'll have an empty machine function since we haven't run any isel yet. Of course, this only works if the MIRParser believes you that this is okay. This is essentially a revert of r241862 with a fix for the problem it was papering over. llvm-svn: 299975
2017-04-11 21:32:41 +02:00
if (!MF->empty())
markReachable(&MF->front());
Add CFG checks to MachineVerifier. Verify that the predecessor and successor lists are consistent and free of duplicates. llvm-svn: 162223
2012-08-20 22:52:06 +02:00
// Build a set of the basic blocks in the function.
FunctionBlocks.clear();
Convert several loops over MachineFunction basic blocks to range-based loops llvm-svn: 207683
2014-04-30 20:29:51 +02:00
for (const auto &MBB : *MF) {
FunctionBlocks.insert(&MBB);
BBInfo &MInfo = MBBInfoMap[&MBB];
MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
if (MInfo.Preds.size() != MBB.pred_size())
report("MBB has duplicate entries in its predecessor list.", &MBB);
MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
if (MInfo.Succs.size() != MBB.succ_size())
report("MBB has duplicate entries in its successor list.", &MBB);
Add CFG checks to MachineVerifier. Verify that the predecessor and successor lists are consistent and free of duplicates. llvm-svn: 162223
2012-08-20 22:52:06 +02:00
}
Add an MRI::verifyUseLists() function. This checks the sanity of the register use lists in the MI intermediate representation. llvm-svn: 179895
2013-04-19 23:40:57 +02:00
// Check that the register use lists are sane.
MRI->verifyUseLists();
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
MIR: Allow parsing of empty machine functions If you run llc -stop-after=codegenprepare and feed the resulting MIR to llc -start-after=codegenprepare, you'll have an empty machine function since we haven't run any isel yet. Of course, this only works if the MIRParser believes you that this is okay. This is essentially a revert of r241862 with a fix for the problem it was papering over. llvm-svn: 299975
2017-04-11 21:32:41 +02:00
if (!MF->empty())
verifyStackFrame();
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
Fix polarity of a CFG check in machine verifier. llvm-svn: 88704
2009-11-13 22:55:54 +01:00
// Does iterator point to a and b as the first two elements?
Fix a bunch of namespace polution. llvm-svn: 101376
2010-04-15 19:08:50 +02:00
static bool matchPair(MachineBasicBlock::const_succ_iterator i,
const MachineBasicBlock *a, const MachineBasicBlock *b) {
Fix polarity of a CFG check in machine verifier. llvm-svn: 88704
2009-11-13 22:55:54 +01:00
if (*i == a)
return *++i == b;
if (*i == b)
return *++i == a;
return false;
}
void
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. llvm-svn: 206142
2014-04-14 02:51:57 +02:00
FirstTerminator = nullptr;
[machineverifier] Detect PHI's that are preceeded by non-PHI's If present, PHI nodes must appear before non-PHI nodes in a basic block. The register allocator relies on this and will fail to eliminate PHI's that do not meet this requirement. llvm-svn: 343731
2018-10-04 00:05:31 +02:00
FirstNonPHI = nullptr;
Verify that terminators follow non-terminators. This exposes a -segmented-stacks bug. llvm-svn: 140429
2011-09-24 00:45:39 +02:00
MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. Specifying isSSA is an extra line at best and results in invalid MI at worst. Compute the value instead. Differential Revision: http://reviews.llvm.org/D22722 llvm-svn: 279600
2016-08-24 03:32:41 +02:00
if (!MF->getProperties().hasProperty(
CodeGen: Assert that liveness is up to date when reading block live-ins. Add an assert that checks whether liveins are up to date before they are used. - Do not print liveins into .mir files anymore in situations where they are out of date anyway. - The assert in the RegisterScavenger is superseded by the new one in livein_begin(). - Skip parts of the liveness updating logic in IfConversion.cpp when liveness isn't tracked anymore (just enough to avoid hitting the new assert()). Differential Revision: https://reviews.llvm.org/D27562 llvm-svn: 291169
2017-01-05 21:01:19 +01:00
MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
Update MachineVerifier to check the new physreg live-in rules. llvm-svn: 150496
2012-02-14 20:17:48 +01:00
// If this block has allocatable physical registers live-in, check that
// it is an entry block or landing pad.
Save LaneMask with livein registers With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
2015-09-09 20:08:03 +02:00
for (const auto &LI : MBB->liveins()) {
if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
ADT: Remove == and != comparisons between ilist iterators and pointers I missed == and != when I removed implicit conversions between iterators and pointers in r252380 since they were defined outside ilist_iterator. Since they depend on getNodePtrUnchecked(), they indirectly rely on UB. This commit removes all uses of these operators. (I'll delete the operators themselves in a separate commit so that it can be easily reverted if necessary.) There should be NFC here. llvm-svn: 261498
2016-02-21 21:39:50 +01:00
MBB->getIterator() != MBB->getParent()->begin()) {
Fix typos llvm-svn: 295246
2017-02-15 23:19:06 +01:00
report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
[MachineVerifier] Include offending register in allocatable live-in error msg. This patch adds a convenience report() method for physical registers and uses it to print the offending register with the 'MBB has allocatable live-in' error. Reviewers: MatzeB, rtereshin, dsanders Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D55946 llvm-svn: 350630
2019-01-08 16:16:23 +01:00
report_context(LI.PhysReg);
Update MachineVerifier to check the new physreg live-in rules. llvm-svn: 150496
2012-02-14 20:17:48 +01:00
}
}
}
Permit landing pad successor blocks when verifying basic blocks that end in an unconditional branch. llvm-svn: 117041
2010-10-21 20:47:06 +02:00
// Count the number of landing pad successors.
Revert "Allow output constraints on "asm goto"" This reverts commit 52366088a8e42c2f1e96e8430b84b8b65ec3f7bc. I accidentally pushed this before supporting changes.
2020-01-07 22:43:04 +01:00
SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
E = MBB->succ_end(); I != E; ++I) {
if ((*I)->isEHPad())
LandingPadSuccs.insert(*I);
if (!FunctionBlocks.count(*I))
Allow output constraints on "asm goto" Summary: Remove the restrictions that preventing "asm goto" from returning non-void values. The values returned by "asm goto" are only valid on the "fallthrough" path. Reviewers: jyknight, nickdesaulniers, hfinkel Reviewed By: jyknight, nickdesaulniers Subscribers: rsmith, hiraditya, llvm-commits, cfe-commits, craig.topper, rnk Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69876
2020-01-07 21:53:44 +01:00
report("MBB has successor that isn't part of the function.", MBB);
Revert "Allow output constraints on "asm goto"" This reverts commit 52366088a8e42c2f1e96e8430b84b8b65ec3f7bc. I accidentally pushed this before supporting changes.
2020-01-07 22:43:04 +01:00
if (!MBBInfoMap[*I].Preds.count(MBB)) {
Allow output constraints on "asm goto" Summary: Remove the restrictions that preventing "asm goto" from returning non-void values. The values returned by "asm goto" are only valid on the "fallthrough" path. Reviewers: jyknight, nickdesaulniers, hfinkel Reviewed By: jyknight, nickdesaulniers Subscribers: rsmith, hiraditya, llvm-commits, cfe-commits, craig.topper, rnk Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69876
2020-01-07 21:53:44 +01:00
report("Inconsistent CFG", MBB);
errs() << "MBB is not in the predecessor list of the successor "
Revert "Allow output constraints on "asm goto"" This reverts commit 52366088a8e42c2f1e96e8430b84b8b65ec3f7bc. I accidentally pushed this before supporting changes.
2020-01-07 22:43:04 +01:00
<< printMBBReference(*(*I)) << ".\n";
Add CFG checks to MachineVerifier. Verify that the predecessor and successor lists are consistent and free of duplicates. llvm-svn: 162223
2012-08-20 22:52:06 +02:00
}
}
// Check the predecessor list.
for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
E = MBB->pred_end(); I != E; ++I) {
if (!FunctionBlocks.count(*I))
report("MBB has predecessor that isn't part of the function.", MBB);
if (!MBBInfoMap[*I].Succs.count(MBB)) {
report("Inconsistent CFG", MBB);
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 18:18:51 +01:00
errs() << "MBB is not in the successor list of the predecessor "
<< printMBBReference(*(*I)) << ".\n";
Add CFG checks to MachineVerifier. Verify that the predecessor and successor lists are consistent and free of duplicates. llvm-svn: 162223
2012-08-20 22:52:06 +02:00
}
MachineVerifier should count landing pad successors as basic blocks rather than out-edges. Fixes PR8824. llvm-svn: 122228
2010-12-20 05:19:48 +01:00
}
SjLj EH could produce a machine basic block that legitimately has more than one landing pad as its successor. SjLj exception handling jumps to the correct landing pad via a switch statement that's generated right before code-gen. Loosen the constraint in the machine instruction verifier to allow for this. Note, this isn't the most rigorous check since we cannot determine where that switch statement came from. But it's marginally better than turning this check off when SjLj exceptions are used. <rdar://problem/9187612> llvm-svn: 130881
2011-05-05 00:54:05 +02:00
const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
const BasicBlock *BB = MBB->getBasicBlock();
MachineFunction: Return reference from getFunction(); NFC The Function can never be nullptr so we can return a reference. llvm-svn: 320884
2017-12-15 23:22:58 +01:00
const Function &F = MF->getFunction();
SjLj EH could produce a machine basic block that legitimately has more than one landing pad as its successor. SjLj exception handling jumps to the correct landing pad via a switch statement that's generated right before code-gen. Loosen the constraint in the machine instruction verifier to allow for this. Note, this isn't the most rigorous check since we cannot determine where that switch statement came from. But it's marginally better than turning this check off when SjLj exceptions are used. <rdar://problem/9187612> llvm-svn: 130881
2011-05-05 00:54:05 +02:00
if (LandingPadSuccs.size() > 1 &&
!(AsmInfo &&
AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
[WinEH] Tweak funclet prologue/epilogue insertion to pass verifier For some reason we'd never run MachineVerifier on WinEH code, and you explicitly have to ask for it with llc. I added it to a few test cases to get some coverage. Fixes PR25461. llvm-svn: 252512
2015-11-09 22:04:00 +01:00
BB && isa<SwitchInst>(BB->getTerminator())) &&
[WebAssembly] Add Wasm personality and isScopedEHPersonality() Summary: - Add wasm personality function - Re-categorize the existing `isFuncletEHPersonality()` function into two different functions: `isFuncletEHPersonality()` and `isScopedEHPersonality(). This becomes necessary as wasm EH uses scoped EH instructions (catchswitch, catchpad/ret, and cleanuppad/ret) but not outlined funclets. - Changed some callsites of `isFuncletEHPersonality()` to `isScopedEHPersonality()` if they are related to scoped EH IR-level stuff. Reviewers: majnemer, dschuff, rnk Subscribers: jfb, sbc100, jgravelle-google, eraman, JDevlieghere, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D45559 llvm-svn: 332667
2018-05-17 22:52:03 +02:00
!isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
Permit landing pad successor blocks when verifying basic blocks that end in an unconditional branch. llvm-svn: 117041
2010-10-21 20:47:06 +02:00
report("MBB has more than one landing pad successor", MBB);
Update spelling of {analyze,insert,remove}Branch in strings and comments These names have been changed from CamelCase to camelCase, but there were many places (comments mostly) that still used the old names. This change is NFC.
2020-01-21 16:47:35 +01:00
// Call analyzeBranch. If it succeeds, there several more conditions to check.
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. llvm-svn: 206142
2014-04-14 02:51:57 +02:00
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
SmallVector<MachineOperand, 4> Cond;
Rename AnalyzeBranch* to analyzeBranch*. Summary: NFC. Rename AnalyzeBranch/AnalyzeBranchPredicate to analyzeBranch/analyzeBranchPredicate to follow LLVM coding style and be consistent with TargetInstrInfo's analyzeCompare and analyzeSelect. Reviewers: tstellarAMD, mcrosier Subscribers: mcrosier, jholewinski, jfb, arsenm, dschuff, jyknight, dsanders, nemanjai Differential Revision: https://reviews.llvm.org/D22409 llvm-svn: 275564
2016-07-15 16:41:04 +02:00
if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
Cond)) {
Update spelling of {analyze,insert,remove}Branch in strings and comments These names have been changed from CamelCase to camelCase, but there were many places (comments mostly) that still used the old names. This change is NFC.
2020-01-21 16:47:35 +01:00
// Ok, analyzeBranch thinks it knows what's going on with this block. Let's
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
// check whether its answers match up with reality.
if (!TBB && !FBB) {
// Block falls through to its successor.
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
MachineFunction::const_iterator MBBI = MBB->getIterator();
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
++MBBI;
if (MBBI == MF->end()) {
Adjust the MachineBasicBlock verifier rules to be more tolerant of blocks that end with "unreachable". llvm-svn: 80270
2009-08-27 20:14:26 +02:00
// It's possible that the block legitimately ends with a noreturn
// call or an unreachable, in which case it won't actually fall
// out the bottom of the function.
Revert "Allow output constraints on "asm goto"" This reverts commit 52366088a8e42c2f1e96e8430b84b8b65ec3f7bc. I accidentally pushed this before supporting changes.
2020-01-07 22:43:04 +01:00
} else if (MBB->succ_size() == LandingPadSuccs.size()) {
Adjust the MachineBasicBlock verifier rules to be more tolerant of blocks that end with "unreachable". llvm-svn: 80270
2009-08-27 20:14:26 +02:00
// It's possible that the block legitimately ends with a noreturn
[NFC] fix trivial typos in comments llvm-svn: 350690
2019-01-09 06:11:10 +01:00
// call or an unreachable, in which case it won't actually fall
Adjust the MachineBasicBlock verifier rules to be more tolerant of blocks that end with "unreachable". llvm-svn: 80270
2009-08-27 20:14:26 +02:00
// out of the block.
Revert "Allow output constraints on "asm goto"" This reverts commit 52366088a8e42c2f1e96e8430b84b8b65ec3f7bc. I accidentally pushed this before supporting changes.
2020-01-07 22:43:04 +01:00
} else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via unconditional fall-through but doesn't have "
"exactly one CFG successor!", MBB);
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
} else if (!MBB->isSuccessor(&*MBBI)) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via unconditional fall-through but its successor "
"differs from its CFG successor!", MBB);
}
MachineVerifier: Clean up some syntactic weirdness left behind by find&replace. No functionality change. llvm-svn: 209581
2014-05-24 15:31:10 +02:00
if (!MBB->empty() && MBB->back().isBarrier() &&
CodeGen: TII: Take MachineInstr& in predicate API, NFC Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
2016-02-23 03:46:52 +01:00
!TII->isPredicated(MBB->back())) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via unconditional fall-through but ends with a "
"barrier instruction!", MBB);
}
if (!Cond.empty()) {
report("MBB exits via unconditional fall-through but has a condition!",
MBB);
}
} else if (TBB && !FBB && Cond.empty()) {
// Block unconditionally branches somewhere.
[MachineVerifier] Accept a MBB with a single landing pad successor. The MachineVerifier used to check that there was always exactly one unconditional branch to a non-landingpad (normal) successor. If that normal successor to an invoke BB is unreachable, it seems reasonable to only have one successor, the landing pad. On targets other than AArch64 (and on AArch64 with a different testcase), the branch folder turns the branch to the landing pad into a fallthrough. The MachineVerifier, which relies on AnalyzeBranch, is unable to check the condition, and doesn't complain. However, it does in this specific testcase, where the branch to the landing pad remained. Make the MachineVerifier accept it. llvm-svn: 223059
2014-12-01 19:43:53 +01:00
// If the block has exactly one successor, that happens to be a
// landingpad, accept it as valid control flow.
if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
(MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
Revert "Allow output constraints on "asm goto"" This reverts commit 52366088a8e42c2f1e96e8430b84b8b65ec3f7bc. I accidentally pushed this before supporting changes.
2020-01-07 22:43:04 +01:00
*MBB->succ_begin() != *LandingPadSuccs.begin())) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via unconditional branch but doesn't have "
"exactly one CFG successor!", MBB);
Permit landing pad successor blocks when verifying basic blocks that end in an unconditional branch. llvm-svn: 117041
2010-10-21 20:47:06 +02:00
} else if (!MBB->isSuccessor(TBB)) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via unconditional branch but the CFG "
"successor doesn't match the actual successor!", MBB);
}
if (MBB->empty()) {
report("MBB exits via unconditional branch but doesn't contain "
"any instructions!", MBB);
MachineVerifier: Clean up some syntactic weirdness left behind by find&replace. No functionality change. llvm-svn: 209581
2014-05-24 15:31:10 +02:00
} else if (!MBB->back().isBarrier()) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via unconditional branch but doesn't end with a "
"barrier instruction!", MBB);
MachineVerifier: Clean up some syntactic weirdness left behind by find&replace. No functionality change. llvm-svn: 209581
2014-05-24 15:31:10 +02:00
} else if (!MBB->back().isTerminator()) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via unconditional branch but the branch isn't a "
"terminator instruction!", MBB);
}
} else if (TBB && !FBB && !Cond.empty()) {
// Block conditionally branches somewhere, otherwise falls through.
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
MachineFunction::const_iterator MBBI = MBB->getIterator();
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
++MBBI;
if (MBBI == MF->end()) {
report("MBB conditionally falls through out of function!", MBB);
Add a missing 'else'. Found by grep '} if' No testcase because it is apparently not so trivial to construct. llvm-svn: 170595
2012-12-19 23:13:01 +01:00
} else if (MBB->succ_size() == 1) {
Don't add CFG edges for redundant conditional branches. IR that hasn't been through SimplifyCFG can look like this: br i1 %b, label %r, label %r Make sure we don't create duplicate Machine CFG edges in this case. Fix the machine code verifier to accept conditional branches with a single CFG edge. llvm-svn: 162230
2012-08-20 23:39:52 +02:00
// A conditional branch with only one successor is weird, but allowed.
if (&*MBBI != TBB)
report("MBB exits via conditional branch/fall-through but only has "
"one CFG successor!", MBB);
else if (TBB != *MBB->succ_begin())
report("MBB exits via conditional branch/fall-through but the CFG "
"successor don't match the actual successor!", MBB);
} else if (MBB->succ_size() != 2) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via conditional branch/fall-through but doesn't have "
"exactly two CFG successors!", MBB);
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
} else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via conditional branch/fall-through but the CFG "
"successors don't match the actual successors!", MBB);
}
if (MBB->empty()) {
report("MBB exits via conditional branch/fall-through but doesn't "
"contain any instructions!", MBB);
MachineVerifier: Clean up some syntactic weirdness left behind by find&replace. No functionality change. llvm-svn: 209581
2014-05-24 15:31:10 +02:00
} else if (MBB->back().isBarrier()) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via conditional branch/fall-through but ends with a "
"barrier instruction!", MBB);
MachineVerifier: Clean up some syntactic weirdness left behind by find&replace. No functionality change. llvm-svn: 209581
2014-05-24 15:31:10 +02:00
} else if (!MBB->back().isTerminator()) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via conditional branch/fall-through but the branch "
"isn't a terminator instruction!", MBB);
}
} else if (TBB && FBB) {
// Block conditionally branches somewhere, otherwise branches
// somewhere else.
Don't add CFG edges for redundant conditional branches. IR that hasn't been through SimplifyCFG can look like this: br i1 %b, label %r, label %r Make sure we don't create duplicate Machine CFG edges in this case. Fix the machine code verifier to accept conditional branches with a single CFG edge. llvm-svn: 162230
2012-08-20 23:39:52 +02:00
if (MBB->succ_size() == 1) {
// A conditional branch with only one successor is weird, but allowed.
if (FBB != TBB)
report("MBB exits via conditional branch/branch through but only has "
"one CFG successor!", MBB);
else if (TBB != *MBB->succ_begin())
report("MBB exits via conditional branch/branch through but the CFG "
"successor don't match the actual successor!", MBB);
} else if (MBB->succ_size() != 2) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via conditional branch/branch but doesn't have "
"exactly two CFG successors!", MBB);
Fix polarity of a CFG check in machine verifier. llvm-svn: 88704
2009-11-13 22:55:54 +01:00
} else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via conditional branch/branch but the CFG "
"successors don't match the actual successors!", MBB);
}
if (MBB->empty()) {
report("MBB exits via conditional branch/branch but doesn't "
"contain any instructions!", MBB);
CodeGen: Make MachineBasicBlock::back skip to the beginning of the last bundle. This makes front/back symmetric with begin/end, avoiding some confusion. Added instr_front/instr_back for the old behavior, corresponding to instr_begin/instr_end. Audited all three in-tree users of back(), all of them look like they don't want to look inside bundles. Fixes an assertion (PR19815) when generating debug info on mips, where a delay slot was bundled at the end of a branch. llvm-svn: 209580
2014-05-24 15:13:17 +02:00
} else if (!MBB->back().isBarrier()) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via conditional branch/branch but doesn't end with a "
"barrier instruction!", MBB);
CodeGen: Make MachineBasicBlock::back skip to the beginning of the last bundle. This makes front/back symmetric with begin/end, avoiding some confusion. Added instr_front/instr_back for the old behavior, corresponding to instr_begin/instr_end. Audited all three in-tree users of back(), all of them look like they don't want to look inside bundles. Fixes an assertion (PR19815) when generating debug info on mips, where a delay slot was bundled at the end of a branch. llvm-svn: 209580
2014-05-24 15:13:17 +02:00
} else if (!MBB->back().isTerminator()) {
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
report("MBB exits via conditional branch/branch but the branch "
"isn't a terminator instruction!", MBB);
}
if (Cond.empty()) {
Fix typo in verifier error message llvm-svn: 345083
2018-10-23 23:23:52 +02:00
report("MBB exits via conditional branch/branch but there's no "
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
"condition!", MBB);
}
} else {
Update spelling of {analyze,insert,remove}Branch in strings and comments These names have been changed from CamelCase to camelCase, but there were many places (comments mostly) that still used the old names. This change is NFC.
2020-01-21 16:47:35 +01:00
report("analyzeBranch returned invalid data!", MBB);
Add some checks for MachineCFG consistency. Use AnalyzeBranch and do extra checking when it succeeds, as those are cases where CodeGen will be doing particularly interesting CFG modifications. llvm-svn: 80196
2009-08-27 04:43:49 +02:00
}
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
regsLive.clear();
CodeGen: Assert that liveness is up to date when reading block live-ins. Add an assert that checks whether liveins are up to date before they are used. - Do not print liveins into .mir files anymore in situations where they are out of date anyway. - The assert in the RegisterScavenger is superseded by the new one in livein_begin(). - Skip parts of the liveness updating logic in IfConversion.cpp when liveness isn't tracked anymore (just enough to avoid hitting the new assert()). Differential Revision: https://reviews.llvm.org/D27562 llvm-svn: 291169
2017-01-05 21:01:19 +01:00
if (MRI->tracksLiveness()) {
for (const auto &LI : MBB->liveins()) {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (!Register::isPhysicalRegister(LI.PhysReg)) {
CodeGen: Assert that liveness is up to date when reading block live-ins. Add an assert that checks whether liveins are up to date before they are used. - Do not print liveins into .mir files anymore in situations where they are out of date anyway. - The assert in the RegisterScavenger is superseded by the new one in livein_begin(). - Skip parts of the liveness updating logic in IfConversion.cpp when liveness isn't tracked anymore (just enough to avoid hitting the new assert()). Differential Revision: https://reviews.llvm.org/D27562 llvm-svn: 291169
2017-01-05 21:01:19 +01:00
report("MBB live-in list contains non-physical register", MBB);
continue;
}
[MCRegInfo] Add forward sub and super register iterators. (NFC) This patch adds forward iterators mc_difflist_iterator, mc_subreg_iterator and mc_superreg_iterator, based on the existing DiffListIterator. Those are used to provide iterator ranges over sub- and super-register from TRI, which are slightly more convenient than the existing MCSubRegIterator/MCSuperRegIterator. Unfortunately, it duplicates a bit of functionality, but the new iterators are a bit more convenient (and can be used with various existing iterator utilities) and should probably replace the old iterators in the future. This patch updates some existing users. Reviewers: evandro, qcolombet, paquette, MatzeB, arsenm Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D70565
2019-12-05 10:16:08 +01:00
for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
regsLive.insert(SubReg);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
}
Use pristine register info in machine code verifier. So far these registers are simply tracked as if they were live-in. llvm-svn: 78912
2009-08-13 18:19:51 +02:00
MachineFunction: Return reference for getFrameInfo(); NFC getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
2016-07-28 20:40:00 +02:00
const MachineFrameInfo &MFI = MF->getFrameInfo();
BitVector PR = MFI.getPristineRegs(*MF);
BitVector: add iterators for set bits Differential revision: https://reviews.llvm.org/D32060 llvm-svn: 303227
2017-05-17 03:07:53 +02:00
for (unsigned I : PR.set_bits()) {
[MCRegInfo] Add forward sub and super register iterators. (NFC) This patch adds forward iterators mc_difflist_iterator, mc_subreg_iterator and mc_superreg_iterator, based on the existing DiffListIterator. Those are used to provide iterator ranges over sub- and super-register from TRI, which are slightly more convenient than the existing MCSubRegIterator/MCSuperRegIterator. Unfortunately, it duplicates a bit of functionality, but the new iterators are a bit more convenient (and can be used with various existing iterator utilities) and should probably replace the old iterators in the future. This patch updates some existing users. Reviewers: evandro, qcolombet, paquette, MatzeB, arsenm Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D70565
2019-12-05 10:16:08 +01:00
for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
regsLive.insert(SubReg);
Use pristine register info in machine code verifier. So far these registers are simply tracked as if they were live-in. llvm-svn: 78912
2009-08-13 18:19:51 +02:00
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
regsKilled.clear();
regsDefined.clear();
Verify slot index ordering. The slot indexes must be monotonically increasing through the function. llvm-svn: 123324
2011-01-12 22:27:48 +01:00
if (Indexes)
lastIndex = Indexes->getMBBStartIdx(MBB);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
// This function gets called for all bundle headers, including normal
// stand-alone unbundled instructions.
void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
2016-02-27 07:40:41 +01:00
if (Indexes && Indexes->hasIndex(*MI)) {
SlotIndex idx = Indexes->getInstructionIndex(*MI);
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
if (!(idx > lastIndex)) {
report("Instruction index out of order", MI);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "Last instruction was at " << lastIndex << '\n';
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
}
lastIndex = idx;
}
Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator llvm-svn: 158154
2012-06-07 19:41:39 +02:00
// Ensure non-terminators don't follow terminators.
// Ignore predicated terminators formed by if conversion.
// FIXME: If conversion shouldn't need to violate this rule.
CodeGen: TII: Take MachineInstr& in predicate API, NFC Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
2016-02-23 03:46:52 +01:00
if (MI->isTerminator() && !TII->isPredicated(*MI)) {
Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator llvm-svn: 158154
2012-06-07 19:41:39 +02:00
if (!FirstTerminator)
FirstTerminator = MI;
Reland "[LiveDebugValues] Emit the debug entry values" Emit replacements for clobbered parameters location if the parameter has unmodified value throughout the funciton. This is basic scenario where we can use the debug entry values. ([12/13] Introduce the debug entry values.) Co-authored-by: Ananth Sowda <asowda@cisco.com> Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com> Co-authored-by: Ivan Baev <ibaev@cisco.com> Differential Revision: https://reviews.llvm.org/D58042 llvm-svn: 365444
2019-07-09 10:36:34 +02:00
} else if (FirstTerminator && !MI->isDebugEntryValue()) {
Revert "Allow output constraints on "asm goto"" This reverts commit 52366088a8e42c2f1e96e8430b84b8b65ec3f7bc. I accidentally pushed this before supporting changes.
2020-01-07 22:43:04 +01:00
report("Non-terminator instruction after the first terminator", MI);
errs() << "First terminator was:\t" << *FirstTerminator;
Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator llvm-svn: 158154
2012-06-07 19:41:39 +02:00
}
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
}
Verify the consistency of inline asm operands. The operands on an INLINEASM machine instruction are divided into groups headed by immediate flag operands. Verify this structure. Extract verifyTiedOperands(), and only call it for non-inlineasm instructions. llvm-svn: 162849
2012-08-29 20:11:05 +02:00
// The operands on an INLINEASM instruction must follow a template.
// Verify that the flag operands make sense.
void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
// The first two operands on INLINEASM are the asm string and global flags.
if (MI->getNumOperands() < 2) {
report("Too few operands on inline asm", MI);
return;
}
if (!MI->getOperand(0).isSymbol())
report("Asm string must be an external symbol", MI);
if (!MI->getOperand(1).isImm())
report("Asm flags must be an immediate", MI);
[inline asm] Implement mayLoad and mayStore for inline assembly. In general, the MachineInstr MayLoad/MayLoad flags are based on the tablegen implementation. For inline assembly, however, we need to compute these based on the constraints. Revert r166929 as this is no longer needed, but leave the test case in place. rdar://12033048 and PR13504 llvm-svn: 167040
2012-10-30 20:11:54 +01:00
// Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
AMDGPU: Add convergent flag to INLINEASM instruction. Differential Revision: http://reviews.llvm.org/D21214 llvm-svn: 273455
2016-06-22 20:51:08 +02:00
// Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
// and Extra_IsConvergent = 32.
if (!isUInt<6>(MI->getOperand(1).getImm()))
Verify the consistency of inline asm operands. The operands on an INLINEASM machine instruction are divided into groups headed by immediate flag operands. Verify this structure. Extract verifyTiedOperands(), and only call it for non-inlineasm instructions. llvm-svn: 162849
2012-08-29 20:11:05 +02:00
report("Unknown asm flags", &MI->getOperand(1), 1);
[llvm] Replacing asserts with static_asserts where appropriate Summary: This patch consists of the suggestions of clang-tidy/misc-static-assert check. Reviewers: alexfh Reviewed By: alexfh Subscribers: xazax.hun, llvm-commits Differential Revision: http://reviews.llvm.org/D8343 llvm-svn: 232366
2015-03-16 10:53:42 +01:00
static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
Verify the consistency of inline asm operands. The operands on an INLINEASM machine instruction are divided into groups headed by immediate flag operands. Verify this structure. Extract verifyTiedOperands(), and only call it for non-inlineasm instructions. llvm-svn: 162849
2012-08-29 20:11:05 +02:00
unsigned OpNo = InlineAsm::MIOp_FirstOperand;
unsigned NumOps;
for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
const MachineOperand &MO = MI->getOperand(OpNo);
// There may be implicit ops after the fixed operands.
if (!MO.isImm())
break;
NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
Add a few simple MachineVerifier checks for MachineMemOperands. llvm-svn: 83474
2009-10-07 19:36:00 +02:00
Verify the consistency of inline asm operands. The operands on an INLINEASM machine instruction are divided into groups headed by immediate flag operands. Verify this structure. Extract verifyTiedOperands(), and only call it for non-inlineasm instructions. llvm-svn: 162849
2012-08-29 20:11:05 +02:00
if (OpNo > MI->getNumOperands())
report("Missing operands in last group", MI);
// An optional MDNode follows the groups.
if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
++OpNo;
// All trailing operands must be implicit registers.
for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (!MO.isReg() || !MO.isImplicit())
report("Expected implicit register after groups", &MO, OpNo);
}
}
GlobalISel: Verify g_select Factor the common vector element consistency check many instructions need out, although this makes the error messages worse. llvm-svn: 353112
2019-02-05 00:29:16 +01:00
/// Check that types are consistent when two operands need to have the same
/// number of vector elements.
/// \return true if the types are valid.
bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
const MachineInstr *MI) {
if (Ty0.isVector() != Ty1.isVector()) {
report("operand types must be all-vector or all-scalar", MI);
// Generally we try to report as many issues as possible at once, but in
// this case it's not clear what should we be comparing the size of the
// scalar with: the size of the whole vector or its lane. Instead of
// making an arbitrary choice and emitting not so helpful message, let's
// avoid the extra noise and stop here.
return false;
}
if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
report("operand types must preserve number of vector elements", MI);
return false;
}
return true;
}
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
if (isFunctionSelected)
report("Unexpected generic instruction in a Selected function", MI);
MachineFunction: Introduce NoPHIs property I want to compute the SSA property of .mir files automatically in upcoming patches. The problem with this is that some inputs will be reported as static single assignment with some passes claiming not to support SSA form. In reality though those passes do not support PHI instructions => Track the presence of PHI instructions separate from the SSA property. Differential Revision: https://reviews.llvm.org/D22719 llvm-svn: 279573
2016-08-23 23:19:49 +02:00
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
const MCInstrDesc &MCID = MI->getDesc();
unsigned NumOps = MI->getNumOperands();
Verify the tied operand flags. WHen running with -verify-machineinstrs, check that tied operands come in matching use/def pairs, and that they are consistent with MCInstrDesc when it applies. llvm-svn: 162816
2012-08-29 02:38:03 +02:00
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
// Check types.
SmallVector<LLT, 4> Types;
for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
[MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visitMachineInstrBefore This is an NFC pre-commit for the following "Checking that generic instrs have LLTs on all vregs" commit. This overloads MachineOperand::print to make it possible to print LLTs with standalone machine operands. This also overloads MachineVerifier::print(...MachineOperand...) with an optional LLT using the newly introduced MachineOperand::print variant; no actual calls added. This also refactors MachineVerifier::visitMachineInstrBefore in the parts dealing with all generic instructions (checking Selected property, LLTs, and phys regs). llvm-svn: 331693
2018-05-08 00:31:12 +02:00
I != E; ++I) {
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
if (!MCID.OpInfo[I].isGenericType())
continue;
// Generic instructions specify type equality constraints between some of
// their operands. Make sure these are consistent.
size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
Types.resize(std::max(TypeIdx + 1, Types.size()));
const MachineOperand *MO = &MI->getOperand(I);
GlobalISel: Fix verifier crashing on non-register operands Also correct the wording of error on subregisters. llvm-svn: 353128
2019-02-05 01:53:22 +01:00
if (!MO->isReg()) {
report("generic instruction must use register operands", MI);
continue;
}
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
LLT OpTy = MRI->getType(MO->getReg());
// Don't report a type mismatch if there is no actual mismatch, only a
// type missing, to reduce noise:
if (OpTy.isValid()) {
// Only the first valid type for a type index will be printed: don't
// overwrite it later so it's always clear which type was expected:
if (!Types[TypeIdx].isValid())
Types[TypeIdx] = OpTy;
else if (Types[TypeIdx] != OpTy)
report("Type mismatch in generic instruction", MO, I, OpTy);
Add basic verification of LiveIntervals. We verify that the LiveInterval is live at uses and defs, and that all instructions have a SlotIndex. Stuff we don't check yet: - Is the LiveInterval minimal? - Do all defs correspond to instructions or phis? - Do all defs dominate all their live ranges? - Are all live ranges continually reachable from their def? llvm-svn: 110386
2010-08-06 00:32:21 +02:00
} else {
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
// Generic instructions must have types attached to their operands.
report("Generic instruction is missing a virtual register type", MO, I);
Add basic verification of LiveIntervals. We verify that the LiveInterval is live at uses and defs, and that all instructions have a SlotIndex. Stuff we don't check yet: - Is the LiveInterval minimal? - Do all defs correspond to instructions or phis? - Do all defs dominate all their live ranges? - Are all live ranges continually reachable from their def? llvm-svn: 110386
2010-08-06 00:32:21 +02:00
}
}
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
// Generic opcodes must not have physical register operands.
for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
const MachineOperand *MO = &MI->getOperand(I);
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
report("Generic instruction cannot have physical register", MO, I);
GlobalISel: forbid physical registers on generic MIs. We're intending to move to a world where the type of a register is determined by its (unique) def. This is incompatible with physregs, which are untyped. It also means the other passes don't have to worry quite so much about register-class compatibility and inserting COPYs appropriately. llvm-svn: 280132
2016-08-30 20:52:46 +02:00
}
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
// Avoid out of bounds in checks below. This was already reported earlier.
if (MI->getNumOperands() < MCID.getNumOperands())
return;
Lower ARM adds/subs to add/sub after adding optional CPSR operand. This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
2011-09-21 04:20:46 +02:00
StringRef ErrorInfo;
CodeGen: Use MachineInstr& in TargetInstrInfo, NFC This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
2016-06-30 02:01:54 +02:00
if (!TII->verifyInstruction(*MI, ErrorInfo))
Lower ARM adds/subs to add/sub after adding optional CPSR operand. This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
2011-09-21 04:20:46 +02:00
report(ErrorInfo.data(), MI);
Add placeholder for more extensive verification of psuedo ops This initial patch doesn't actually do much useful. It's just to show where the new code goes. Once this is in, I'll extend the verification logic to check more useful properties. For those curious, the more complicated version of this patch already found one very suspicious thing. Differential Revision: https://reviews.llvm.org/D33819 llvm-svn: 304564
2017-06-02 18:36:37 +02:00
// Verify properties of various specific instruction types
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
switch (MI->getOpcode()) {
GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT llvm-svn: 351853
2019-01-22 19:53:41 +01:00
case TargetOpcode::G_CONSTANT:
case TargetOpcode::G_FCONSTANT: {
if (MI->getNumOperands() < MCID.getNumOperands())
break;
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
if (DstTy.isVector())
report("Instruction cannot use a vector result type", MI);
GlobalISel: Enforce operand types for constants A number of of tests were using imm operands, not cimm. Since CSE relies on the exact ConstantInt* pointer used, and implicit conversions are generally evil, also enforce the bitsize of the types. llvm-svn: 353113
2019-02-05 00:29:31 +01:00
if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
if (!MI->getOperand(1).isCImm()) {
report("G_CONSTANT operand must be cimm", MI);
break;
}
const ConstantInt *CI = MI->getOperand(1).getCImm();
if (CI->getBitWidth() != DstTy.getSizeInBits())
report("inconsistent constant size", MI);
} else {
if (!MI->getOperand(1).isFPImm()) {
report("G_FCONSTANT operand must be fpimm", MI);
break;
}
const ConstantFP *CF = MI->getOperand(1).getFPImm();
if (APFloat::getSizeInBits(CF->getValueAPF().getSemantics()) !=
DstTy.getSizeInBits()) {
report("inconsistent constant size", MI);
}
}
GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT llvm-svn: 351853
2019-01-22 19:53:41 +01:00
break;
}
Add placeholder for more extensive verification of psuedo ops This initial patch doesn't actually do much useful. It's just to show where the new code goes. Once this is in, I'll extend the verification logic to check more useful properties. For those curious, the more complicated version of this patch already found one very suspicious thing. Differential Revision: https://reviews.llvm.org/D33819 llvm-svn: 304564
2017-06-02 18:36:37 +02:00
case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE:
Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload"" I reverted it originally due to a bot failing. The underlying bug has been fixed as of r352311. llvm-svn: 352312
2019-01-27 12:34:41 +01:00
case TargetOpcode::G_ZEXTLOAD:
GlobalISel: Verify load/store has a pointer input I expected this to be automatically verified, but it seems nothing uses that the type index was declared as a "ptype" llvm-svn: 352319
2019-01-27 16:57:23 +01:00
case TargetOpcode::G_SEXTLOAD: {
GlobalISel: Verify memory size for load/store llvm-svn: 352578
2019-01-30 02:10:42 +01:00
LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
GlobalISel: Verify load/store has a pointer input I expected this to be automatically verified, but it seems nothing uses that the type index was declared as a "ptype" llvm-svn: 352319
2019-01-27 16:57:23 +01:00
LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
if (!PtrTy.isPointer())
report("Generic memory instruction must access a pointer", MI);
Add placeholder for more extensive verification of psuedo ops This initial patch doesn't actually do much useful. It's just to show where the new code goes. Once this is in, I'll extend the verification logic to check more useful properties. For those curious, the more complicated version of this patch already found one very suspicious thing. Differential Revision: https://reviews.llvm.org/D33819 llvm-svn: 304564
2017-06-02 18:36:37 +02:00
// Generic loads and stores must have a single MachineMemOperand
// describing that access.
Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload"" I reverted it originally due to a bot failing. The underlying bug has been fixed as of r352311. llvm-svn: 352312
2019-01-27 12:34:41 +01:00
if (!MI->hasOneMemOperand()) {
Add placeholder for more extensive verification of psuedo ops This initial patch doesn't actually do much useful. It's just to show where the new code goes. Once this is in, I'll extend the verification logic to check more useful properties. For those curious, the more complicated version of this patch already found one very suspicious thing. Differential Revision: https://reviews.llvm.org/D33819 llvm-svn: 304564
2017-06-02 18:36:37 +02:00
report("Generic instruction accessing memory must have one mem operand",
MI);
Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload"" I reverted it originally due to a bot failing. The underlying bug has been fixed as of r352311. llvm-svn: 352312
2019-01-27 12:34:41 +01:00
} else {
GlobalISel: Verify memory size for load/store llvm-svn: 352578
2019-01-30 02:10:42 +01:00
const MachineMemOperand &MMO = **MI->memoperands_begin();
Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload"" I reverted it originally due to a bot failing. The underlying bug has been fixed as of r352311. llvm-svn: 352312
2019-01-27 12:34:41 +01:00
if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
Add a getSizeInBits() accessor to MachineMemOperand. NFC. Cleans up a bunch of places where we do getSize() * 8. Differential Revision: https://reviews.llvm.org/D60799 llvm-svn: 358617
2019-04-18 00:21:05 +02:00
if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload"" I reverted it originally due to a bot failing. The underlying bug has been fixed as of r352311. llvm-svn: 352312
2019-01-27 12:34:41 +01:00
report("Generic extload must have a narrower memory type", MI);
GlobalISel: Verify memory size for load/store llvm-svn: 352578
2019-01-30 02:10:42 +01:00
} else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
Add a getSizeInBits() accessor to MachineMemOperand. NFC. Cleans up a bunch of places where we do getSize() * 8. Differential Revision: https://reviews.llvm.org/D60799 llvm-svn: 358617
2019-04-18 00:21:05 +02:00
if (MMO.getSize() > ValTy.getSizeInBytes())
GlobalISel: Verify memory size for load/store llvm-svn: 352578
2019-01-30 02:10:42 +01:00
report("load memory size cannot exceed result size", MI);
} else if (MI->getOpcode() == TargetOpcode::G_STORE) {
Add a getSizeInBits() accessor to MachineMemOperand. NFC. Cleans up a bunch of places where we do getSize() * 8. Differential Revision: https://reviews.llvm.org/D60799 llvm-svn: 358617
2019-04-18 00:21:05 +02:00
if (ValTy.getSizeInBytes() < MMO.getSize())
GlobalISel: Verify memory size for load/store llvm-svn: 352578
2019-01-30 02:10:42 +01:00
report("store memory size cannot exceed value size", MI);
Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload"" I reverted it originally due to a bot failing. The underlying bug has been fixed as of r352311. llvm-svn: 352312
2019-01-27 12:34:41 +01:00
}
}
Add placeholder for more extensive verification of psuedo ops This initial patch doesn't actually do much useful. It's just to show where the new code goes. Once this is in, I'll extend the verification logic to check more useful properties. For those curious, the more complicated version of this patch already found one very suspicious thing. Differential Revision: https://reviews.llvm.org/D33819 llvm-svn: 304564
2017-06-02 18:36:37 +02:00
break;
GlobalISel: Verify load/store has a pointer input I expected this to be automatically verified, but it seems nothing uses that the type index was declared as a "ptype" llvm-svn: 352319
2019-01-27 16:57:23 +01:00
}
[GISEl]: Translate phi into G_PHI G_PHI has the same semantics as PHI but also has types. This lets us verify that the types in the G_PHI are consistent. This also allows specifying legalization actions for G_PHIs. https://reviews.llvm.org/D36990 llvm-svn: 311596
2017-08-23 22:45:48 +02:00
case TargetOpcode::G_PHI: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
if (!DstTy.isValid() ||
!std::all_of(MI->operands_begin() + 1, MI->operands_end(),
[this, &DstTy](const MachineOperand &MO) {
if (!MO.isReg())
return true;
LLT Ty = MRI->getType(MO.getReg());
if (!Ty.isValid() || (Ty != DstTy))
return false;
return true;
}))
report("Generic Instruction G_PHI has operands with incompatible/missing "
"types",
MI);
break;
}
GlobalISel: Verify G_BITCAST llvm-svn: 351594
2019-01-18 22:04:59 +01:00
case TargetOpcode::G_BITCAST: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
if (!DstTy.isValid() || !SrcTy.isValid())
break;
if (SrcTy.isPointer() != DstTy.isPointer())
report("bitcast cannot convert between pointers and other types", MI);
if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
report("bitcast sizes must match", MI);
break;
}
GlobalISel: Verify pointer casts Not sure if the old AArch64 tests should be just deleted or not. llvm-svn: 352562
2019-01-30 00:29:00 +01:00
case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_PTRTOINT:
case TargetOpcode::G_ADDRSPACE_CAST: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
if (!DstTy.isValid() || !SrcTy.isValid())
break;
GlobalISel: Verify g_select Factor the common vector element consistency check many instructions need out, although this makes the error messages worse. llvm-svn: 353112
2019-02-05 00:29:16 +01:00
verifyVectorElementMatch(DstTy, SrcTy, MI);
GlobalISel: Verify pointer casts Not sure if the old AArch64 tests should be just deleted or not. llvm-svn: 352562
2019-01-30 00:29:00 +01:00
DstTy = DstTy.getScalarType();
SrcTy = SrcTy.getScalarType();
if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
if (!DstTy.isPointer())
report("inttoptr result type must be a pointer", MI);
if (SrcTy.isPointer())
report("inttoptr source type must not be a pointer", MI);
} else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
if (!SrcTy.isPointer())
report("ptrtoint source type must be a pointer", MI);
if (DstTy.isPointer())
report("ptrtoint result type must not be a pointer", MI);
} else {
assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
if (!SrcTy.isPointer() || !DstTy.isPointer())
report("addrspacecast types must be pointers", MI);
else {
if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
report("addrspacecast must convert different address spaces", MI);
}
}
break;
}
[globalisel] Rename G_GEP to G_PTR_ADD Summary: G_GEP is rather poorly named. It's a simple pointer+scalar addition and doesn't support any of the complexities of getelementptr. I therefore propose that we rename it. There's a G_PTR_MASK so let's follow that convention and go with G_PTR_ADD Reviewers: volkan, aditya_nandakumar, bogner, rovka, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69734
2019-11-01 21:18:00 +01:00
case TargetOpcode::G_PTR_ADD: {
GlobalISel: Verify G_GEP llvm-svn: 353209
2019-02-05 21:04:12 +01:00
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
break;
if (!PtrTy.getScalarType().isPointer())
report("gep first operand must be a pointer", MI);
if (OffsetTy.getScalarType().isPointer())
report("gep offset operand must not be a pointer", MI);
// TODO: Is the offset allowed to be a scalar with a vector?
break;
}
[MachineVerifier][GlobalISel] Verifying generic extends and truncates Making sure we don't truncate / extend pointers, don't try to change vector topology or bitcast vectors to scalars or back, and most importantly, don't extend to a smaller type or truncate to a large one. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331718
2018-05-08 04:48:15 +02:00
case TargetOpcode::G_SEXT:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_TRUNC:
case TargetOpcode::G_FPEXT:
case TargetOpcode::G_FPTRUNC: {
// Number of operands and presense of types is already checked (and
// reported in case of any issues), so no need to report them again. As
// we're trying to report as many issues as possible at once, however, the
// instructions aren't guaranteed to have the right number of operands or
// types attached to them at this point
assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
if (!DstTy.isValid() || !SrcTy.isValid())
break;
GlobalISel: Verify g_select Factor the common vector element consistency check many instructions need out, although this makes the error messages worse. llvm-svn: 353112
2019-02-05 00:29:16 +01:00
LLT DstElTy = DstTy.getScalarType();
LLT SrcElTy = SrcTy.getScalarType();
[MachineVerifier][GlobalISel] Verifying generic extends and truncates Making sure we don't truncate / extend pointers, don't try to change vector topology or bitcast vectors to scalars or back, and most importantly, don't extend to a smaller type or truncate to a large one. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331718
2018-05-08 04:48:15 +02:00
if (DstElTy.isPointer() || SrcElTy.isPointer())
report("Generic extend/truncate can not operate on pointers", MI);
GlobalISel: Verify g_select Factor the common vector element consistency check many instructions need out, although this makes the error messages worse. llvm-svn: 353112
2019-02-05 00:29:16 +01:00
verifyVectorElementMatch(DstTy, SrcTy, MI);
[MachineVerifier][GlobalISel] Verifying generic extends and truncates Making sure we don't truncate / extend pointers, don't try to change vector topology or bitcast vectors to scalars or back, and most importantly, don't extend to a smaller type or truncate to a large one. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331718
2018-05-08 04:48:15 +02:00
unsigned DstSize = DstElTy.getSizeInBits();
unsigned SrcSize = SrcElTy.getSizeInBits();
switch (MI->getOpcode()) {
default:
if (DstSize <= SrcSize)
report("Generic extend has destination type no larger than source", MI);
break;
case TargetOpcode::G_TRUNC:
case TargetOpcode::G_FPTRUNC:
if (DstSize >= SrcSize)
report("Generic truncate has destination type no smaller than source",
MI);
break;
}
break;
}
GlobalISel: Verify g_select Factor the common vector element consistency check many instructions need out, although this makes the error messages worse. llvm-svn: 353112
2019-02-05 00:29:16 +01:00
case TargetOpcode::G_SELECT: {
LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
if (!SelTy.isValid() || !CondTy.isValid())
break;
// Scalar condition select on a vector is valid.
if (CondTy.isVector())
verifyVectorElementMatch(SelTy, CondTy, MI);
break;
}
[GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes. This patch restricts the capability of G_MERGE_VALUES, and uses the new G_BUILD_VECTOR and G_CONCAT_VECTORS opcodes instead in the appropriate places. This patch also includes AArch64 support for selecting G_BUILD_VECTOR of <4 x s32> and <2 x s64> vectors. Differential Revisions: https://reviews.llvm.org/D53629 llvm-svn: 348788
2018-12-10 19:44:58 +01:00
case TargetOpcode::G_MERGE_VALUES: {
// G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
// e.g. s2N = MERGE sN, sN
// Merging multiple scalars into a vector is not allowed, should use
// G_BUILD_VECTOR for that.
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
if (DstTy.isVector() || SrcTy.isVector())
report("G_MERGE_VALUES cannot operate on vectors", MI);
GlobalISel: Verify G_MERGE_VALUES operand sizes llvm-svn: 364822
2019-07-01 20:01:35 +02:00
const unsigned NumOps = MI->getNumOperands();
if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
report("G_MERGE_VALUES result size is inconsistent", MI);
for (unsigned I = 2; I != NumOps; ++I) {
if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
report("G_MERGE_VALUES source types do not match", MI);
}
[GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes. This patch restricts the capability of G_MERGE_VALUES, and uses the new G_BUILD_VECTOR and G_CONCAT_VECTORS opcodes instead in the appropriate places. This patch also includes AArch64 support for selecting G_BUILD_VECTOR of <4 x s32> and <2 x s64> vectors. Differential Revisions: https://reviews.llvm.org/D53629 llvm-svn: 348788
2018-12-10 19:44:58 +01:00
break;
}
case TargetOpcode::G_UNMERGE_VALUES: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
// For now G_UNMERGE can split vectors.
for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
report("G_UNMERGE_VALUES destination types do not match", MI);
}
if (SrcTy.getSizeInBits() !=
(DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
report("G_UNMERGE_VALUES source operand does not cover dest operands",
MI);
}
break;
}
[GlobalISel] Introduce G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC and G_CONCAT_VECTOR opcodes. These opcodes are intended to subsume some of the capability of G_MERGE_VALUES, as it was too powerful and thus complex to add deal with throughout the GISel pipeline. G_BUILD_VECTOR creates a vector value from a sequence of uniformly typed scalar values. G_BUILD_VECTOR_TRUNC is a special opcode for handling scalar operands which are larger than the destination vector element type, and therefore does an implicit truncate. G_CONCAT_VECTOR creates a vector by concatenating smaller, uniformly typed, vectors together. These will be used in a subsequent commit. This commit just adds the initial infrastructure. Differential Revision: https://reviews.llvm.org/D53594 llvm-svn: 348430
2018-12-06 00:53:30 +01:00
case TargetOpcode::G_BUILD_VECTOR: {
// Source types must be scalars, dest type a vector. Total size of scalars
// must match the dest vector size.
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
GlobalISel: Fix inadequate verification of g_build_vector Testing based on the total size of the elements failed to catch a few invalid scenarios, so explicitly check the number of elements/operands and types. This failed to catch situations like <4 x s16> = G_BUILD_VECTOR s32, s32 since the total size added up. This also would fail to catch an implicit conversion between pointers and scalars. llvm-svn: 354139
2019-02-15 16:24:34 +01:00
if (!DstTy.isVector() || SrcEltTy.isVector()) {
[GlobalISel] Introduce G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC and G_CONCAT_VECTOR opcodes. These opcodes are intended to subsume some of the capability of G_MERGE_VALUES, as it was too powerful and thus complex to add deal with throughout the GISel pipeline. G_BUILD_VECTOR creates a vector value from a sequence of uniformly typed scalar values. G_BUILD_VECTOR_TRUNC is a special opcode for handling scalar operands which are larger than the destination vector element type, and therefore does an implicit truncate. G_CONCAT_VECTOR creates a vector by concatenating smaller, uniformly typed, vectors together. These will be used in a subsequent commit. This commit just adds the initial infrastructure. Differential Revision: https://reviews.llvm.org/D53594 llvm-svn: 348430
2018-12-06 00:53:30 +01:00
report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
GlobalISel: Fix inadequate verification of g_build_vector Testing based on the total size of the elements failed to catch a few invalid scenarios, so explicitly check the number of elements/operands and types. This failed to catch situations like <4 x s16> = G_BUILD_VECTOR s32, s32 since the total size added up. This also would fail to catch an implicit conversion between pointers and scalars. llvm-svn: 354139
2019-02-15 16:24:34 +01:00
break;
}
if (DstTy.getElementType() != SrcEltTy)
report("G_BUILD_VECTOR result element type must match source type", MI);
if (DstTy.getNumElements() != MI->getNumOperands() - 1)
report("G_BUILD_VECTOR must have an operand for each elemement", MI);
[GlobalISel] Introduce G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC and G_CONCAT_VECTOR opcodes. These opcodes are intended to subsume some of the capability of G_MERGE_VALUES, as it was too powerful and thus complex to add deal with throughout the GISel pipeline. G_BUILD_VECTOR creates a vector value from a sequence of uniformly typed scalar values. G_BUILD_VECTOR_TRUNC is a special opcode for handling scalar operands which are larger than the destination vector element type, and therefore does an implicit truncate. G_CONCAT_VECTOR creates a vector by concatenating smaller, uniformly typed, vectors together. These will be used in a subsequent commit. This commit just adds the initial infrastructure. Differential Revision: https://reviews.llvm.org/D53594 llvm-svn: 348430
2018-12-06 00:53:30 +01:00
for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
if (MRI->getType(MI->getOperand(1).getReg()) !=
MRI->getType(MI->getOperand(i).getReg()))
report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
}
GlobalISel: Fix inadequate verification of g_build_vector Testing based on the total size of the elements failed to catch a few invalid scenarios, so explicitly check the number of elements/operands and types. This failed to catch situations like <4 x s16> = G_BUILD_VECTOR s32, s32 since the total size added up. This also would fail to catch an implicit conversion between pointers and scalars. llvm-svn: 354139
2019-02-15 16:24:34 +01:00
[GlobalISel] Introduce G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC and G_CONCAT_VECTOR opcodes. These opcodes are intended to subsume some of the capability of G_MERGE_VALUES, as it was too powerful and thus complex to add deal with throughout the GISel pipeline. G_BUILD_VECTOR creates a vector value from a sequence of uniformly typed scalar values. G_BUILD_VECTOR_TRUNC is a special opcode for handling scalar operands which are larger than the destination vector element type, and therefore does an implicit truncate. G_CONCAT_VECTOR creates a vector by concatenating smaller, uniformly typed, vectors together. These will be used in a subsequent commit. This commit just adds the initial infrastructure. Differential Revision: https://reviews.llvm.org/D53594 llvm-svn: 348430
2018-12-06 00:53:30 +01:00
break;
}
case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
// Source types must be scalars, dest type a vector. Scalar types must be
// larger than the dest vector elt type, as this is a truncating operation.
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
if (!DstTy.isVector() || SrcEltTy.isVector())
report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
MI);
for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
if (MRI->getType(MI->getOperand(1).getReg()) !=
MRI->getType(MI->getOperand(i).getReg()))
report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
MI);
}
if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
"dest elt type",
MI);
break;
}
case TargetOpcode::G_CONCAT_VECTORS: {
// Source types should be vectors, and total size should match the dest
// vector size.
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
if (!DstTy.isVector() || !SrcTy.isVector())
report("G_CONCAT_VECTOR requires vector source and destination operands",
MI);
for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
if (MRI->getType(MI->getOperand(1).getReg()) !=
MRI->getType(MI->getOperand(i).getReg()))
report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
}
if (DstTy.getNumElements() !=
SrcTy.getNumElements() * (MI->getNumOperands() - 1))
report("G_CONCAT_VECTOR num dest and source elements should match", MI);
break;
}
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
case TargetOpcode::G_ICMP:
case TargetOpcode::G_FCMP: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
if ((DstTy.isVector() != SrcTy.isVector()) ||
(DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
report("Generic vector icmp/fcmp must preserve number of lanes", MI);
break;
}
GlobalISel: Verify G_EXTRACT llvm-svn: 353759
2019-02-11 23:12:43 +01:00
case TargetOpcode::G_EXTRACT: {
const MachineOperand &SrcOp = MI->getOperand(1);
if (!SrcOp.isReg()) {
report("extract source must be a register", MI);
break;
}
const MachineOperand &OffsetOp = MI->getOperand(2);
if (!OffsetOp.isImm()) {
report("extract offset must be a constant", MI);
break;
}
unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
if (SrcSize == DstSize)
report("extract source must be larger than result", MI);
if (DstSize + OffsetOp.getImm() > SrcSize)
report("extract reads past end of register", MI);
break;
}
GlobalISel: Verify g_insert llvm-svn: 354342
2019-02-19 17:10:16 +01:00
case TargetOpcode::G_INSERT: {
const MachineOperand &SrcOp = MI->getOperand(2);
if (!SrcOp.isReg()) {
report("insert source must be a register", MI);
break;
}
const MachineOperand &OffsetOp = MI->getOperand(3);
if (!OffsetOp.isImm()) {
report("insert offset must be a constant", MI);
break;
}
unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
if (DstSize <= SrcSize)
report("inserted size must be smaller than total register", MI);
if (SrcSize + OffsetOp.getImm() > DstSize)
report("insert writes past end of register", MI);
break;
}
[GlobalISel] Add a G_JUMP_TABLE opcode. This opcode generates a pointer to the address of the jump table specified by the source operand, which is a jump table index. It will be used in conjunction with an upcoming G_BRJT opcode to support jump table codegen with GlobalISel. Differential Revision: https://reviews.llvm.org/D63111 llvm-svn: 363096
2019-06-11 21:58:06 +02:00
case TargetOpcode::G_JUMP_TABLE: {
if (!MI->getOperand(1).isJTI())
report("G_JUMP_TABLE source operand must be a jump table index", MI);
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
if (!DstTy.isPointer())
report("G_JUMP_TABLE dest operand must have a pointer type", MI);
break;
}
[GlobalISel] Add a G_BRJT opcode. This is a branch opcode that takes a jump table pointer, jump table index and an index into the table to do an indirect branch. We pass both the table pointer and JTI to allow targets like ARM64 to more easily use the existing jump table compression optimization without having to walk up the block to find a paired G_JUMP_TABLE. Differential Revision: https://reviews.llvm.org/D63159 llvm-svn: 363434
2019-06-14 19:55:48 +02:00
case TargetOpcode::G_BRJT: {
if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
report("G_BRJT src operand 0 must be a pointer type", MI);
if (!MI->getOperand(1).isJTI())
report("G_BRJT src operand 1 must be a jump table index", MI);
const auto &IdxOp = MI->getOperand(2);
if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
report("G_BRJT src operand 2 must be a scalar reg type", MI);
break;
}
GlobalISel: Verify intrinsics I keep using the wrong instruction when manually writing tests. This really needs to check the number of operands, but I don't see an easy way to do that right now. llvm-svn: 363579
2019-06-17 19:01:32 +02:00
case TargetOpcode::G_INTRINSIC:
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
// TODO: Should verify number of def and use operands, but the current
// interface requires passing in IR types for mangling.
const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
if (!IntrIDOp.isIntrinsicID()) {
report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
break;
}
bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
unsigned IntrID = IntrIDOp.getIntrinsicID();
if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
AttributeList Attrs
= Intrinsic::getAttributes(MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
bool DeclHasSideEffects = !Attrs.hasFnAttribute(Attribute::ReadNone);
if (NoSideEffects && DeclHasSideEffects) {
report("G_INTRINSIC used with intrinsic that accesses memory", MI);
break;
}
if (!NoSideEffects && !DeclHasSideEffects) {
report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
break;
}
}
Add an operand to memory intrinsics to denote the "tail" marker. We need to propagate this information from the IR in order to be able to safely do tail call optimizations on the intrinsics during legalization. Assuming it's safe to do tail call opt without checking for the marker isn't safe because the mem libcall may use allocas from the caller. This adds an extra immediate operand to the end of the intrinsics and fixes the legalizer to handle it. Differential Revision: https://reviews.llvm.org/D68151 llvm-svn: 373140
2019-09-28 07:33:21 +02:00
switch (IntrID) {
case Intrinsic::memcpy:
if (MI->getNumOperands() != 5)
report("Expected memcpy intrinsic to have 5 operands", MI);
break;
case Intrinsic::memmove:
if (MI->getNumOperands() != 5)
report("Expected memmove intrinsic to have 5 operands", MI);
break;
case Intrinsic::memset:
if (MI->getNumOperands() != 5)
report("Expected memset intrinsic to have 5 operands", MI);
break;
}
[globalisel] Add G_SEXT_INREG Summary: Targets often have instructions that can sign-extend certain cases faster than the equivalent shift-left/arithmetic-shift-right. Such cases can be identified by matching a shift-left/shift-right pair but there are some issues with this in the context of combines. For example, suppose you can sign-extend 8-bit up to 32-bit with a target extend instruction. %1:_(s32) = G_SHL %0:_(s32), i32 24 # (I've inlined the G_CONSTANT for brevity) %2:_(s32) = G_ASHR %1:_(s32), i32 24 %3:_(s32) = G_ASHR %2:_(s32), i32 1 would reasonably combine to: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 25 which no longer matches the special case. If your shifts and extend are equal cost, this would break even as a pair of shifts but if your shift is more expensive than the extend then it's cheaper as: %2:_(s32) = G_SEXT_INREG %0:_(s32), i32 8 %3:_(s32) = G_ASHR %2:_(s32), i32 1 It's possible to match the shift-pair in ISel and emit an extend and ashr. However, this is far from the only way to break this shift pair and make it hard to match the extends. Another example is that with the right known-zeros, this: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 24 %3:_(s32) = G_MUL %2:_(s32), i32 2 can become: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 23 All upstream targets have been configured to lower it to the current G_SHL,G_ASHR pair but will likely want to make it legal in some cases to handle their faster cases. To follow-up: Provide a way to legalize based on the constant. At the moment, I'm thinking that the best way to achieve this is to provide the MI in LegalityQuery but that opens the door to breaking core principles of the legalizer (legality is not context sensitive). That said, it's worth noting that looking at other instructions and acting on that information doesn't violate this principle in itself. It's only a violation if, at the end of legalization, a pass that checks legality without being able to see the context would say an instruction might not be legal. That's a fairly subtle distinction so to give a concrete example, saying %2 in: %1 = G_CONSTANT 16 %2 = G_SEXT_INREG %0, %1 is legal is in violation of that principle if the legality of %2 depends on %1 being constant and/or being 16. However, legalizing to either: %2 = G_SEXT_INREG %0, 16 or: %1 = G_CONSTANT 16 %2:_(s32) = G_SHL %0, %1 %3:_(s32) = G_ASHR %2, %1 depending on whether %1 is constant and 16 does not violate that principle since both outputs are genuinely legal. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, rovka, kristof.beyls, javed.absar, hiraditya, jrtc27, atanasyan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61289 llvm-svn: 368487
2019-08-09 23:11:20 +02:00
break;
}
case TargetOpcode::G_SEXT_INREG: {
if (!MI->getOperand(2).isImm()) {
report("G_SEXT_INREG expects an immediate operand #2", MI);
break;
}
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
verifyVectorElementMatch(DstTy, SrcTy, MI);
GlobalISel: Verify intrinsics I keep using the wrong instruction when manually writing tests. This really needs to check the number of operands, but I don't see an easy way to do that right now. llvm-svn: 363579
2019-06-17 19:01:32 +02:00
[globalisel] Add G_SEXT_INREG Summary: Targets often have instructions that can sign-extend certain cases faster than the equivalent shift-left/arithmetic-shift-right. Such cases can be identified by matching a shift-left/shift-right pair but there are some issues with this in the context of combines. For example, suppose you can sign-extend 8-bit up to 32-bit with a target extend instruction. %1:_(s32) = G_SHL %0:_(s32), i32 24 # (I've inlined the G_CONSTANT for brevity) %2:_(s32) = G_ASHR %1:_(s32), i32 24 %3:_(s32) = G_ASHR %2:_(s32), i32 1 would reasonably combine to: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 25 which no longer matches the special case. If your shifts and extend are equal cost, this would break even as a pair of shifts but if your shift is more expensive than the extend then it's cheaper as: %2:_(s32) = G_SEXT_INREG %0:_(s32), i32 8 %3:_(s32) = G_ASHR %2:_(s32), i32 1 It's possible to match the shift-pair in ISel and emit an extend and ashr. However, this is far from the only way to break this shift pair and make it hard to match the extends. Another example is that with the right known-zeros, this: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 24 %3:_(s32) = G_MUL %2:_(s32), i32 2 can become: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 23 All upstream targets have been configured to lower it to the current G_SHL,G_ASHR pair but will likely want to make it legal in some cases to handle their faster cases. To follow-up: Provide a way to legalize based on the constant. At the moment, I'm thinking that the best way to achieve this is to provide the MI in LegalityQuery but that opens the door to breaking core principles of the legalizer (legality is not context sensitive). That said, it's worth noting that looking at other instructions and acting on that information doesn't violate this principle in itself. It's only a violation if, at the end of legalization, a pass that checks legality without being able to see the context would say an instruction might not be legal. That's a fairly subtle distinction so to give a concrete example, saying %2 in: %1 = G_CONSTANT 16 %2 = G_SEXT_INREG %0, %1 is legal is in violation of that principle if the legality of %2 depends on %1 being constant and/or being 16. However, legalizing to either: %2 = G_SEXT_INREG %0, 16 or: %1 = G_CONSTANT 16 %2:_(s32) = G_SHL %0, %1 %3:_(s32) = G_ASHR %2, %1 depending on whether %1 is constant and 16 does not violate that principle since both outputs are genuinely legal. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, rovka, kristof.beyls, javed.absar, hiraditya, jrtc27, atanasyan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61289 llvm-svn: 368487
2019-08-09 23:11:20 +02:00
int64_t Imm = MI->getOperand(2).getImm();
if (Imm <= 0)
report("G_SEXT_INREG size must be >= 1", MI);
if (Imm >= SrcTy.getScalarSizeInBits())
report("G_SEXT_INREG size must be less than source bit width", MI);
GlobalISel: Verify intrinsics I keep using the wrong instruction when manually writing tests. This really needs to check the number of operands, but I don't see an easy way to do that right now. llvm-svn: 363579
2019-06-17 19:01:32 +02:00
break;
}
GlobalISel: Change representation of shuffle masks Currently shufflemasks get emitted as any other constant, and you end up with a bunch of virtual registers of G_CONSTANT with a G_BUILD_VECTOR. The AArch64 selector then asserts on anything that doesn't fit this pattern. This isn't an ideal representation, and should avoid legalization and have fewer opportunities for a representational error. Rather than invent a new shuffle mask operand type, similar to what ShuffleVectorSDNode does, just track the original IR Constant mask operand. I don't completely like the idea of adding another link to the IR, but MIR is already quite dependent on IR constants already, and this will allow sharing the shuffle mask utility functions with the IR. llvm-svn: 368704
2019-08-13 17:34:38 +02:00
case TargetOpcode::G_SHUFFLE_VECTOR: {
const MachineOperand &MaskOp = MI->getOperand(3);
if (!MaskOp.isShuffleMask()) {
report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
break;
}
GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR llvm-svn: 368705
2019-08-13 17:52:21 +02:00
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
if (Src0Ty != Src1Ty)
report("Source operands must be the same type", MI);
if (Src0Ty.getScalarType() != DstTy.getScalarType())
report("G_SHUFFLE_VECTOR cannot change element type", MI);
// Don't check that all operands are vector because scalars are used in
// place of 1 element vectors.
int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
[GlobalISel] Change representation of shuffle masks in MachineOperand. We're planning to remove the shufflemask operand from ShuffleVectorInst (D72467); fix GlobalISel so it doesn't depend on that Constant. The change to prelegalizercombiner-shuffle-vector.mir happens because the input contains a literal "-1" in the mask (so the parser/verifier weren't really handling it properly). We now treat it as equivalent to "undef" in all contexts. Differential Revision: https://reviews.llvm.org/D72663
2020-01-14 00:32:45 +01:00
ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR llvm-svn: 368705
2019-08-13 17:52:21 +02:00
if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
report("Wrong result type for shufflemask", MI);
for (int Idx : MaskIdxes) {
if (Idx < 0)
continue;
if (Idx >= 2 * SrcNumElts)
report("Out of bounds shuffle index", MI);
}
GlobalISel: Change representation of shuffle masks Currently shufflemasks get emitted as any other constant, and you end up with a bunch of virtual registers of G_CONSTANT with a G_BUILD_VECTOR. The AArch64 selector then asserts on anything that doesn't fit this pattern. This isn't an ideal representation, and should avoid legalization and have fewer opportunities for a representational error. Rather than invent a new shuffle mask operand type, similar to what ShuffleVectorSDNode does, just track the original IR Constant mask operand. I don't completely like the idea of adding another link to the IR, but MIR is already quite dependent on IR constants already, and this will allow sharing the shuffle mask utility functions with the IR. llvm-svn: 368704
2019-08-13 17:34:38 +02:00
break;
}
[GlobalISel] Introduce a G_DYN_STACKALLOC opcode to represent dynamic allocas. This just adds the opcode and verifier, it will be used to replace existing dynamic alloca handling in a subsequent patch. Differential Revision: https://reviews.llvm.org/D66677 llvm-svn: 369833
2019-08-24 04:25:56 +02:00
case TargetOpcode::G_DYN_STACKALLOC: {
const MachineOperand &DstOp = MI->getOperand(0);
const MachineOperand &AllocOp = MI->getOperand(1);
const MachineOperand &AlignOp = MI->getOperand(2);
if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
report("dst operand 0 must be a pointer type", MI);
break;
}
if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
report("src operand 1 must be a scalar reg type", MI);
break;
}
if (!AlignOp.isImm()) {
report("src operand 2 must be an immediate type", MI);
break;
}
break;
}
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
default:
break;
}
}
void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
const MCInstrDesc &MCID = MI->getDesc();
if (MI->getNumOperands() < MCID.getNumOperands()) {
report("Too few operands", MI);
errs() << MCID.getNumOperands() << " operands expected, but "
<< MI->getNumOperands() << " given.\n";
}
if (MI->isPHI()) {
if (MF->getProperties().hasProperty(
MachineFunctionProperties::Property::NoPHIs))
report("Found PHI instruction with NoPHIs property set", MI);
if (FirstNonPHI)
report("Found PHI instruction after non-PHI", MI);
} else if (FirstNonPHI == nullptr)
FirstNonPHI = MI;
// Check the tied operands.
if (MI->isInlineAsm())
verifyInlineAsm(MI);
// Check the MachineMemOperands for basic consistency.
for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
E = MI->memoperands_end();
I != E; ++I) {
if ((*I)->isLoad() && !MI->mayLoad())
report("Missing mayLoad flag", MI);
if ((*I)->isStore() && !MI->mayStore())
report("Missing mayStore flag", MI);
}
// Debug values must not have a slot index.
// Other instructions must have one, unless they are inside a bundle.
if (LiveInts) {
bool mapped = !LiveInts->isNotInMIMap(*MI);
if (MI->isDebugInstr()) {
if (mapped)
report("Debug instruction has a slot index", MI);
} else if (MI->isInsideBundle()) {
if (mapped)
report("Instruction inside bundle has a slot index", MI);
} else {
if (!mapped)
report("Missing slot index", MI);
}
}
if (isPreISelGenericOpcode(MCID.getOpcode())) {
verifyPreISelGenericInstruction(MI);
return;
}
StringRef ErrorInfo;
if (!TII->verifyInstruction(*MI, ErrorInfo))
report(ErrorInfo.data(), MI);
// Verify properties of various specific instruction types
switch (MI->getOpcode()) {
[GISel]: Verify COPIES involving generic registers. Add verification for copies involving generic registers if they are compatible - ie if it is a generic copy, then the types are the same, and if a COPY b/w generic and target virtual register, then the sizes should be the same. Only checks if there are no sub registers involved for now. https://reviews.llvm.org/D37775 llvm-svn: 324696
2018-02-09 02:27:23 +01:00
case TargetOpcode::COPY: {
if (foundErrors)
break;
const MachineOperand &DstOp = MI->getOperand(0);
const MachineOperand &SrcOp = MI->getOperand(1);
LLT DstTy = MRI->getType(DstOp.getReg());
LLT SrcTy = MRI->getType(SrcOp.getReg());
if (SrcTy.isValid() && DstTy.isValid()) {
// If both types are valid, check that the types are the same.
if (SrcTy != DstTy) {
report("Copy Instruction is illegal with mismatching types", MI);
errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
}
}
if (SrcTy.isValid() || DstTy.isValid()) {
// If one of them have valid types, let's just check they have the same
// size.
unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
assert(SrcSize && "Expecting size here");
assert(DstSize && "Expecting size here");
if (SrcSize != DstSize)
if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
report("Copy Instruction is illegal with mismatching sizes", MI);
errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
<< "\n";
}
}
break;
}
Add placeholder for more extensive verification of psuedo ops This initial patch doesn't actually do much useful. It's just to show where the new code goes. Once this is in, I'll extend the verification logic to check more useful properties. For those curious, the more complicated version of this patch already found one very suspicious thing. Differential Revision: https://reviews.llvm.org/D33819 llvm-svn: 304564
2017-06-02 18:36:37 +02:00
case TargetOpcode::STATEPOINT:
if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
!MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
!MI->getOperand(StatepointOpers::NCallArgsPos).isImm())
report("meta operands to STATEPOINT not constant!", MI);
break;
Verify a couple more fields in STATEPOINT instructions While doing so, clarify the comments and update them to reflect current reality. Note: I'm going to let this sit for a week or so before adding further verification. I want to give this time to cycle through bots and merge it into our downstream tree before pushing this further. llvm-svn: 304565
2017-06-02 19:02:33 +02:00
auto VerifyStackMapConstant = [&](unsigned Offset) {
if (!MI->getOperand(Offset).isImm() ||
Remove trailing space sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h} llvm-svn: 338293
2018-07-30 21:41:25 +02:00
MI->getOperand(Offset).getImm() != StackMaps::ConstantOp ||
!MI->getOperand(Offset + 1).isImm())
Verify a couple more fields in STATEPOINT instructions While doing so, clarify the comments and update them to reflect current reality. Note: I'm going to let this sit for a week or so before adding further verification. I want to give this time to cycle through bots and merge it into our downstream tree before pushing this further. llvm-svn: 304565
2017-06-02 19:02:33 +02:00
report("stack map constant to STATEPOINT not well formed!", MI);
};
const unsigned VarStart = StatepointOpers(MI).getVarIdx();
VerifyStackMapConstant(VarStart + StatepointOpers::CCOffset);
VerifyStackMapConstant(VarStart + StatepointOpers::FlagsOffset);
VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
// TODO: verify we have properly encoded deopt arguments
MachineVerifier: Move verification of G_* instructions to function llvm-svn: 353111
2019-02-05 00:29:11 +01:00
break;
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
void
Whitespace and formatting. llvm-svn: 83285
2009-10-04 20:18:39 +02:00
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
const MachineInstr *MI = MO->getParent();
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-28 21:10:37 +02:00
const MCInstrDesc &MCID = MI->getDesc();
MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction. The PATCHPOINT instructions have a single optional defined register operand, but the machine verifier can't verify the optional defined register operands. This commit makes sure that the machine verifier won't report an error when a PATCHPOINT instruction doesn't have its optional defined register operand. This change will allow us to enable the machine verifier for the code generation tests for the patchpoint intrinsics. Reviewers: Juergen Ributzka llvm-svn: 244513
2015-08-10 23:47:36 +02:00
unsigned NumDefs = MCID.getNumDefs();
if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
Verify that explicit definitions in the TargetInstrDesc are matched by explicit register define operands. llvm-svn: 71933
2009-05-16 09:25:20 +02:00
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-28 21:10:37 +02:00
// The first MCID.NumDefs operands must be explicit register defines
MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction. The PATCHPOINT instructions have a single optional defined register operand, but the machine verifier can't verify the optional defined register operands. This commit makes sure that the machine verifier won't report an error when a PATCHPOINT instruction doesn't have its optional defined register operand. This change will allow us to enable the machine verifier for the code generation tests for the patchpoint intrinsics. Reviewers: Juergen Ributzka llvm-svn: 244513
2015-08-10 23:47:36 +02:00
if (MONum < NumDefs) {
Fix undefined behavior: don't perform array indexing through a potentially null pointer. llvm-svn: 161919
2012-08-15 03:39:31 +02:00
const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
Verify that explicit definitions in the TargetInstrDesc are matched by explicit register define operands. llvm-svn: 71933
2009-05-16 09:25:20 +02:00
if (!MO->isReg())
report("Explicit definition must be a register", MO, MONum);
Optional def can be either a def or a use (of reg0). llvm-svn: 157640
2012-05-29 21:40:44 +02:00
else if (!MO->isDef() && !MCOI.isOptionalDef())
Verify that explicit definitions in the TargetInstrDesc are matched by explicit register define operands. llvm-svn: 71933
2009-05-16 09:25:20 +02:00
report("Explicit definition marked as use", MO, MONum);
else if (MO->isImplicit())
report("Explicit definition marked as implicit", MO, MONum);
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-28 21:10:37 +02:00
} else if (MONum < MCID.getNumOperands()) {
Fix undefined behavior: don't perform array indexing through a potentially null pointer. llvm-svn: 161919
2012-08-15 03:39:31 +02:00
const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
Only avoid the check if we're the last operand before the variable operands in a variadic instruction. llvm-svn: 119446
2010-11-17 01:55:36 +01:00
// Don't check if it's the last operand in a variadic instruction. See,
[MachineVerifier] Improve checks of target instructions operands. While working with a patch for instruction selection, the splitting of a large immediate ended up begin treated incorrectly by the backend. Where a register operand should have been created, it instead became an immediate. To my surprise the machine verifier failed to report this, which at the time would have been helpful. This patch improves the verifier so that it will report this type of error. This patch XFAILs CodeGen/SPARC/fp128.ll, which has been reported at https://bugs.llvm.org/show_bug.cgi?id=44091 Review: thegameg, arsenm, fhahn https://reviews.llvm.org/D63973
2019-11-01 10:14:22 +01:00
// e.g., LDM_RET in the arm back end. Check non-variadic operands only.
bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
if (!IsOptional) {
if (MO->isReg()) {
if (MO->isDef() && !MCOI.isOptionalDef())
report("Explicit operand marked as def", MO, MONum);
if (MO->isImplicit())
report("Explicit operand marked as implicit", MO, MONum);
}
// Check that an instruction has register operands only as expected.
if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
!MO->isReg() && !MO->isFI())
report("Expected a register operand.", MO, MONum);
if ((MCOI.OperandType == MCOI::OPERAND_IMMEDIATE ||
MCOI.OperandType == MCOI::OPERAND_PCREL) && MO->isReg())
report("Expected a non-register operand.", MO, MONum);
Fix verification of explicit operands. The machine code verifier did not check for explicit operands correctly. It used MachineInstr::getNumExplicitOperands, but that method may cheat and use the declared count in the TargetInstrDesc. Now we check the explicit operands one at a time in visitMachineOperand. llvm-svn: 82652
2009-09-23 22:57:55 +02:00
}
Verify the tied operand flags. WHen running with -verify-machineinstrs, check that tied operands come in matching use/def pairs, and that they are consistent with MCInstrDesc when it applies. llvm-svn: 162816
2012-08-29 02:38:03 +02:00
Move tie checks into MachineVerifier::visitMachineOperand. llvm-svn: 163152
2012-09-04 20:38:28 +02:00
int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
if (TiedTo != -1) {
Verify the tied operand flags. WHen running with -verify-machineinstrs, check that tied operands come in matching use/def pairs, and that they are consistent with MCInstrDesc when it applies. llvm-svn: 162816
2012-08-29 02:38:03 +02:00
if (!MO->isReg())
report("Tied use must be a register", MO, MONum);
else if (!MO->isTied())
report("Operand should be tied", MO, MONum);
Move tie checks into MachineVerifier::visitMachineOperand. llvm-svn: 163152
2012-09-04 20:38:28 +02:00
else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
report("Tied def doesn't match MCInstrDesc", MO, MONum);
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
else if (Register::isPhysicalRegister(MO->getReg())) {
[MachineVerifier] Add check that tied physregs aren't different. Summary: Added MachineVerifier code to check register ties more thoroughly, especially so that physical registers that are tied are the same. This may help e.g. when creating MIR files. Original patch by Jesper Antonsson Reviewers: stoklund, sanjoy, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, llvm-commits Differential Revision: https://reviews.llvm.org/D34394 llvm-svn: 307259
2017-07-06 15:18:21 +02:00
const MachineOperand &MOTied = MI->getOperand(TiedTo);
if (!MOTied.isReg())
report("Tied counterpart must be a register", &MOTied, TiedTo);
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
else if (Register::isPhysicalRegister(MOTied.getReg()) &&
[MachineVerifier] Add check that tied physregs aren't different. Summary: Added MachineVerifier code to check register ties more thoroughly, especially so that physical registers that are tied are the same. This may help e.g. when creating MIR files. Original patch by Jesper Antonsson Reviewers: stoklund, sanjoy, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, llvm-commits Differential Revision: https://reviews.llvm.org/D34394 llvm-svn: 307259
2017-07-06 15:18:21 +02:00
MO->getReg() != MOTied.getReg())
report("Tied physical registers must match.", &MOTied, TiedTo);
}
Verify the tied operand flags. WHen running with -verify-machineinstrs, check that tied operands come in matching use/def pairs, and that they are consistent with MCInstrDesc when it applies. llvm-svn: 162816
2012-08-29 02:38:03 +02:00
} else if (MO->isReg() && MO->isTied())
report("Explicit operand should not be tied", MO, MONum);
Fix verification of explicit operands. The machine code verifier did not check for explicit operands correctly. It used MachineInstr::getNumExplicitOperands, but that method may cheat and use the declared count in the TargetInstrDesc. Now we check the explicit operands one at a time in visitMachineOperand. llvm-svn: 82652
2009-09-23 22:57:55 +02:00
} else {
Allow explicit %reg0 operands beyond what the .td file describes. ARM uses these to indicate predicates. llvm-svn: 91922
2009-12-22 22:48:20 +01:00
// ARM adds %reg0 operands to indicate predicates. We'll allow that.
Add bundle aware API for querying instruction properties and switch the code generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
2011-12-07 08:15:52 +01:00
if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
Fix verification of explicit operands. The machine code verifier did not check for explicit operands correctly. It used MachineInstr::getNumExplicitOperands, but that method may cheat and use the declared count in the TargetInstrDesc. Now we check the explicit operands one at a time in visitMachineOperand. llvm-svn: 82652
2009-09-23 22:57:55 +02:00
report("Extra explicit operand on non-variadic instruction", MO, MONum);
Verify that explicit definitions in the TargetInstrDesc are matched by explicit register define operands. llvm-svn: 71933
2009-05-16 09:25:20 +02:00
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
switch (MO->getType()) {
case MachineOperand::MO_Register: {
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM Summary: This clang-tidy check is looking for unsigned integer variables whose initializer starts with an implicit cast from llvm::Register and changes the type of the variable to llvm::Register (dropping the llvm:: where possible). Partial reverts in: X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned& MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register PPCFastISel.cpp - No Register::operator-=() PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned& MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor Manual fixups in: ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned& HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register. PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned& Depends on D65919 Reviewers: arsenm, bogner, craig.topper, RKSimon Reviewed By: arsenm Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65962 llvm-svn: 369041
2019-08-15 21:22:08 +02:00
const Register Reg = MO->getReg();
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
if (!Reg)
return;
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
if (MRI->tracksLiveness() && !MI->isDebugValue())
checkLiveness(MO, MONum);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
Move tie checks into MachineVerifier::visitMachineOperand. llvm-svn: 163152
2012-09-04 20:38:28 +02:00
// Verify the consistency of tied operands.
if (MO->isTied()) {
unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
if (!OtherMO.isReg())
report("Must be tied to a register", MO, MONum);
if (!OtherMO.isTied())
report("Missing tie flags on tied operand", MO, MONum);
if (MI->findTiedOperandIdx(OtherIdx) != MONum)
report("Inconsistent tie links", MO, MONum);
if (MONum < MCID.getNumDefs()) {
if (OtherIdx < MCID.getNumOperands()) {
if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
report("Explicit def tied to explicit use without tie constraint",
MO, MONum);
} else {
if (!OtherMO.isImplicit())
report("Explicit def should be tied to implicit use", MO, MONum);
}
}
}
Verify two-address constraints more carefully. Include <undef> operands and virtual registers after leaving SSA form. llvm-svn: 160734
2012-07-25 18:49:11 +02:00
// Verify two-address constraints after leaving SSA form.
unsigned DefIdx;
if (!MRI->isSSA() && MO->isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
Reg != MI->getOperand(DefIdx).getReg())
report("Two-address instruction operands must be identical", MO, MONum);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
// Check register classes.
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
unsigned SubIdx = MO->getSubReg();
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isPhysicalRegister(Reg)) {
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
if (SubIdx) {
report("Illegal subregister index for physical register", MO, MONum);
return;
}
if (MONum < MCID.getNumOperands()) {
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
2012-05-08 00:10:26 +02:00
if (const TargetRegisterClass *DRC =
TII->getRegClass(MCID, MONum, TRI, *MF)) {
Fix sub-register operand verification. PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. llvm-svn: 141220
2011-10-06 00:12:57 +02:00
if (!DRC->contains(Reg)) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
report("Illegal physical register for instruction", MO, MONum);
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-11-30 17:12:24 +01:00
errs() << printReg(Reg, TRI) << " is not a "
<< TRI->getRegClassName(DRC) << " register.\n";
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
}
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
}
[MachineVerifier] Add check that renamable operands aren't reserved registers. Summary: Reviewers: qcolombet, MatzeB Subscribers: arsenm, sdardis, nhaehnle, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D42449 llvm-svn: 323676
2018-01-29 19:57:07 +01:00
if (MO->isRenamable()) {
[MachineOperand][Target] MachineOperand::isRenamable semantics changes Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
2018-02-23 19:25:08 +01:00
if (MRI->isReserved(Reg)) {
[MachineVerifier] Add check that renamable operands aren't reserved registers. Summary: Reviewers: qcolombet, MatzeB Subscribers: arsenm, sdardis, nhaehnle, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D42449 llvm-svn: 323676
2018-01-29 19:57:07 +01:00
report("isRenamable set on reserved register", MO, MONum);
[MachineOperand][Target] MachineOperand::isRenamable semantics changes Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
2018-02-23 19:25:08 +01:00
return;
}
[MachineOperand][MIR] Add isRenamable to MachineOperand. Summary: Add isRenamable() predicate to MachineOperand. This predicate can be used by machine passes after register allocation to determine whether it is safe to rename a given register operand. Register operands that aren't marked as renamable may be required to be assigned their current register to satisfy constraints that are not captured by the machine IR (e.g. ABI or ISA constraints). Reviewers: qcolombet, MatzeB, hfinkel Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39400 llvm-svn: 320503
2017-12-12 18:53:59 +01:00
}
[DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property Summary: In some cases, these operands lacked the IsDebug property, which is meant to signal that they should not affect codegen. This patch adds a check for this property in the MachineVerifier and adds it where it was missing. This includes refactorings to use MachineInstrBuilder construction functions instead of manually setting up the intrinsic everywhere. Patch by: JesperAntonsson Reviewers: aprantl, rnk, echristo, javed.absar Reviewed By: aprantl Subscribers: qcolombet, sdardis, nemanjai, JDevlieghere, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D48319 llvm-svn: 335214
2018-06-21 12:03:34 +02:00
if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) {
report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum);
return;
}
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
} else {
// Virtual register.
const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
if (!RC) {
// This is a generic virtual register.
// If we're post-Select, we can't have gvregs anymore.
if (isFunctionSelected) {
report("Generic virtual register invalid in a Selected function",
MO, MONum);
return;
}
[GlobalISel] Verify Selected MF property. After instruction selection, there should be no pre-isel generic instructions remaining, nor should generic virtual registers be used. Verify that. llvm-svn: 277483
2016-08-02 18:49:22 +02:00
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
// The gvreg must have a type and it must not have a SubIdx.
LLT Ty = MRI->getType(Reg);
if (!Ty.isValid()) {
report("Generic virtual register must have a valid type", MO,
MONum);
return;
}
[GlobalISel] Verify RegBankSelected MF property. RegBankSelected functions shouldn't have any generic virtual register not assigned to a bank. Verify that. llvm-svn: 277476
2016-08-02 18:17:15 +02:00
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
[GlobalISel] Verify RegBankSelected MF property. RegBankSelected functions shouldn't have any generic virtual register not assigned to a bank. Verify that. llvm-svn: 277476
2016-08-02 18:17:15 +02:00
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
// If we're post-RegBankSelect, the gvreg must have a bank.
if (!RegBank && isFunctionRegBankSelected) {
report("Generic virtual register must have a bank in a "
"RegBankSelected function",
MO, MONum);
return;
}
[GlobalISel] Verify RegBankSelected MF property. RegBankSelected functions shouldn't have any generic virtual register not assigned to a bank. Verify that. llvm-svn: 277476
2016-08-02 18:17:15 +02:00
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
// Make sure the register fits into its register bank if any.
if (RegBank && Ty.isValid() &&
RegBank->getSize() < Ty.getSizeInBits()) {
report("Register bank is too small for virtual register", MO,
MONum);
errs() << "Register bank " << RegBank->getName() << " too small("
<< RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
<< "-bits\n";
return;
}
if (SubIdx) {
GlobalISel: Fix verifier crashing on non-register operands Also correct the wording of error on subregisters. llvm-svn: 353128
2019-02-05 01:53:22 +01:00
report("Generic virtual register does not allow subregister index", MO,
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
MONum);
return;
}
[MachineVerifier] Check that even generic vregs comply to regclass constraints. We used to not check generic vregs, but that is actually a mistake given nothing in the GlobalISel pipeline is going to fix the constraints on target specific instructions. Therefore, the target has to have them right from the start. llvm-svn: 290380
2016-12-22 22:56:39 +01:00
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
// If this is a target specific instruction and this operand
// has register class constraint, the virtual register must
// comply to it.
if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
MONum < MCID.getNumOperands() &&
TII->getRegClass(MCID, MONum, TRI, *MF)) {
report("Virtual register does not match instruction constraint", MO,
MONum);
errs() << "Expect register class "
<< TRI->getRegClassName(
TII->getRegClass(MCID, MONum, TRI, *MF))
<< " but got nothing\n";
return;
}
[MachineVerifier] Check that even generic vregs comply to regclass constraints. We used to not check generic vregs, but that is actually a mistake given nothing in the GlobalISel pipeline is going to fix the constraints on target specific instructions. Therefore, the target has to have them right from the start. llvm-svn: 290380
2016-12-22 22:56:39 +01:00
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
break;
}
if (SubIdx) {
const TargetRegisterClass *SRC =
TRI->getSubClassWithSubReg(RC, SubIdx);
if (!SRC) {
report("Invalid subregister index for virtual register", MO, MONum);
errs() << "Register class " << TRI->getRegClassName(RC)
<< " does not support subreg index " << SubIdx << "\n";
return;
[MachineVerifier] Teach how to check some of the properties of generic virtual registers. Generic virtual registers: - May not have a register class - May not have a register bank - If they do not have a register class they must have a size - If they have a register bank, the size of the register bank must be greater or equal to the size of the virtual register (basically check that the virtual register will fit into that register class) llvm-svn: 265798
2016-04-08 18:35:22 +02:00
}
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
if (RC != SRC) {
report("Invalid register class for subregister index", MO, MONum);
errs() << "Register class " << TRI->getRegClassName(RC)
<< " does not fully support subreg index " << SubIdx << "\n";
return;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
MachineVerifier: Improve register operand checks This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
2017-11-28 04:54:20 +01:00
}
if (MONum < MCID.getNumOperands()) {
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
2012-05-08 00:10:26 +02:00
if (const TargetRegisterClass *DRC =
TII->getRegClass(MCID, MONum, TRI, *MF)) {
Fix sub-register operand verification. PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. llvm-svn: 141220
2011-10-06 00:12:57 +02:00
if (SubIdx) {
const TargetRegisterClass *SuperRC =
Have TargetRegisterInfo::getLargestLegalSuperClass take a MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
2015-03-11 00:46:01 +01:00
TRI->getLargestLegalSuperClass(RC, *MF);
Fix sub-register operand verification. PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. llvm-svn: 141220
2011-10-06 00:12:57 +02:00
if (!SuperRC) {
report("No largest legal super class exists.", MO, MONum);
return;
}
DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
if (!DRC) {
report("No matching super-reg register class.", MO, MONum);
return;
}
}
Use TRI::has{Sub,Super}ClassEq() where possible. No functional change. llvm-svn: 132455
2011-06-02 07:43:46 +02:00
if (!RC->hasSuperClassEq(DRC)) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
report("Illegal virtual register for instruction", MO, MONum);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "Expected a " << TRI->getRegClassName(DRC)
Move register class name strings to a single array in MCRegisterInfo to reduce static table size and number of relocation entries. Indices into the table are stored in each MCRegisterClass instead of a pointer. A new method, getRegClassName, is added to MCRegisterInfo and TargetRegisterInfo to lookup the string in the table. llvm-svn: 222118
2014-11-17 06:50:14 +01:00
<< " register, but got a " << TRI->getRegClassName(RC)
<< " register\n";
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
}
}
}
break;
}
Verify that phi instructions refer to MBBs in the CFG. The machine code verifier no longer tolerates phi instructions with noop operands. All MBBs on a phi instruction must be in the CFG. llvm-svn: 82448
2009-09-21 09:19:08 +02:00
Handle regmasks in the machine code verifier. llvm-svn: 151607
2012-02-28 02:42:41 +01:00
case MachineOperand::MO_RegisterMask:
regMasks.push_back(MO->getRegMask());
break;
Verify that phi instructions refer to MBBs in the CFG. The machine code verifier no longer tolerates phi instructions with noop operands. All MBBs on a phi instruction must be in the CFG. llvm-svn: 82448
2009-09-21 09:19:08 +02:00
case MachineOperand::MO_MachineBasicBlock:
move target-independent opcodes out of TargetInstrInfo into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
2010-02-09 20:54:29 +01:00
if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
report("PHI operand is not in the CFG", MO, MONum);
Verify that phi instructions refer to MBBs in the CFG. The machine code verifier no longer tolerates phi instructions with noop operands. All MBBs on a phi instruction must be in the CFG. llvm-svn: 82448
2009-09-21 09:19:08 +02:00
break;
Add basic LiveStacks verification. When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
2010-11-01 20:49:52 +01:00
case MachineOperand::MO_FrameIndex:
if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
2016-02-27 07:40:41 +01:00
LiveInts && !LiveInts->isNotInMIMap(*MI)) {
[MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves. Since the verifier will give false reports if it incorrectly thinks MI is loading or storing using an FI, it is necessary to scan memoperands and find out how the FI is used in the instruction. This should be relatively rare. Needed to make CodeGen/SystemZ/spill-01.ll pass, which now runs with this flag. Reviewed by Quentin Colombet. llvm-svn: 251620
2015-10-29 09:28:35 +01:00
int FI = MO->getIndex();
LiveInterval &LI = LiveStks->getInterval(FI);
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
2016-02-27 07:40:41 +01:00
SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
Let MachineVerifier be aware of mem-to-mem instructions. A mem-to-mem instruction (that both loads and stores), which store to an FI, cannot pass the verifier since it thinks it is loading from the FI. For the mem-to-mem instruction, do a looser check in visitMachineOperand() and only check liveness at the reg-slot while analyzing a frame index operand. Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs, which now runs with this flag. Reviewed by Evan Cheng and Quentin Colombet. llvm-svn: 250885
2015-10-21 09:39:47 +02:00
bool stores = MI->mayStore();
[MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves. Since the verifier will give false reports if it incorrectly thinks MI is loading or storing using an FI, it is necessary to scan memoperands and find out how the FI is used in the instruction. This should be relatively rare. Needed to make CodeGen/SystemZ/spill-01.ll pass, which now runs with this flag. Reviewed by Quentin Colombet. llvm-svn: 251620
2015-10-29 09:28:35 +01:00
bool loads = MI->mayLoad();
// For a memory-to-memory move, we need to check if the frame
// index is used for storing or loading, by inspecting the
// memory operands.
if (stores && loads) {
for (auto *MMO : MI->memoperands()) {
const PseudoSourceValue *PSV = MMO->getPseudoValue();
if (PSV == nullptr) continue;
const FixedStackPseudoSourceValue *Value =
dyn_cast<FixedStackPseudoSourceValue>(PSV);
if (Value == nullptr) continue;
if (Value->getFrameIndex() != FI) continue;
if (MMO->isStore())
loads = false;
else
stores = false;
break;
}
if (loads == stores)
report("Missing fixed stack memoperand.", MI);
}
if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
Add basic LiveStacks verification. When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
2010-11-01 20:49:52 +01:00
report("Instruction loads from dead spill slot", MO, MONum);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "Live stack: " << LI << '\n';
Add basic LiveStacks verification. When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
2010-11-01 20:49:52 +01:00
}
Let MachineVerifier be aware of mem-to-mem instructions. A mem-to-mem instruction (that both loads and stores), which store to an FI, cannot pass the verifier since it thinks it is loading from the FI. For the mem-to-mem instruction, do a looser check in visitMachineOperand() and only check liveness at the reg-slot while analyzing a frame index operand. Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs, which now runs with this flag. Reviewed by Evan Cheng and Quentin Colombet. llvm-svn: 250885
2015-10-21 09:39:47 +02:00
if (stores && !LI.liveAt(Idx.getRegSlot())) {
Add basic LiveStacks verification. When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
2010-11-01 20:49:52 +01:00
report("Instruction stores to dead spill slot", MO, MONum);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "Live stack: " << LI << '\n';
Add basic LiveStacks verification. When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
2010-11-01 20:49:52 +01:00
}
}
break;
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
default:
break;
}
}
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
LaneBitmask LaneMask) {
LiveQueryResult LRQ = LR.Query(UseIdx);
// Check if we have a segment at the use, note however that we only need one
// live subregister range, the others may be dead.
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
if (!LRQ.valueIn() && LaneMask.none()) {
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report("No live segment at use", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
report_context(UseIdx);
}
if (MO->isKill() && !LRQ.isKill()) {
report("Live range continues after kill flag", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if (LaneMask.any())
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report_context_lanemask(LaneMask);
report_context(UseIdx);
}
}
void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
[MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs Summary: Consider an instruction that has multiple defs of the same vreg, but defining different subregs: %7.sub1:rc, dead %7.sub2:rc = inst Calling checkLivenessAtDef for the live interval associated with %7 incorrectly reported "live range continues after a dead def". The live range for %7 has a dead def at the slot index for "inst" even if the live range continues (given that there are later uses of %7.sub1). This patch adjusts MachineVerifier::checkLivenessAtDef to allow dead subregister definitions, unless we are checking a subrange (when tracking subregister liveness). A limitation is that we do not detect the situation when the live range continues past an instruction that defines the full virtual register by multiple dead subreg defines. I also removed some dead code related to physical register in checkLivenessAtDef. Wwe only call that method for virtual registers, so I added an assertion instead. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52237 llvm-svn: 342618
2018-09-20 08:59:18 +02:00
bool SubRangeCheck, LaneBitmask LaneMask) {
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
assert(VNI && "NULL valno is not allowed");
if (VNI->def != DefIdx) {
report("Inconsistent valno->def", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if (LaneMask.any())
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report_context_lanemask(LaneMask);
report_context(*VNI);
report_context(DefIdx);
}
} else {
report("No live segment at def", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if (LaneMask.any())
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report_context_lanemask(LaneMask);
report_context(DefIdx);
}
// Check that, if the dead def flag is present, LiveInts agree.
if (MO->isDead()) {
LiveQueryResult LRQ = LR.Query(DefIdx);
if (!LRQ.isDeadDef()) {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
assert(Register::isVirtualRegister(VRegOrUnit) &&
[MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs Summary: Consider an instruction that has multiple defs of the same vreg, but defining different subregs: %7.sub1:rc, dead %7.sub2:rc = inst Calling checkLivenessAtDef for the live interval associated with %7 incorrectly reported "live range continues after a dead def". The live range for %7 has a dead def at the slot index for "inst" even if the live range continues (given that there are later uses of %7.sub1). This patch adjusts MachineVerifier::checkLivenessAtDef to allow dead subregister definitions, unless we are checking a subrange (when tracking subregister liveness). A limitation is that we do not detect the situation when the live range continues past an instruction that defines the full virtual register by multiple dead subreg defines. I also removed some dead code related to physical register in checkLivenessAtDef. Wwe only call that method for virtual registers, so I added an assertion instead. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52237 llvm-svn: 342618
2018-09-20 08:59:18 +02:00
"Expecting a virtual register.");
// A dead subreg def only tells us that the specific subreg is dead. There
// could be other non-dead defs of other subregs, or we could have other
// parts of the register being live through the instruction. So unless we
// are checking liveness for a subrange it is ok for the live range to
// continue, given that we have a dead def of a subregister.
if (SubRangeCheck || MO->getSubReg() == 0) {
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report("Live range continues after dead def flag", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if (LaneMask.any())
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report_context_lanemask(LaneMask);
}
}
}
}
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
const MachineInstr *MI = MO->getParent();
const unsigned Reg = MO->getReg();
// Both use and def operands can read a register.
if (MO->readsReg()) {
Verify two-address constraints more carefully. Include <undef> operands and virtual registers after leaving SSA form. llvm-svn: 160734
2012-07-25 18:49:11 +02:00
if (MO->isKill())
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
addRegWithSubRegs(regsKilled, Reg);
// Check that LiveVars knows this kill.
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (LiveVars && Register::isVirtualRegister(Reg) && MO->isKill()) {
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
Use the range variant of find instead of unpacking begin/end If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
2016-08-12 00:21:41 +02:00
if (!is_contained(VI.Kills, MI))
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
report("Kill missing from LiveVariables", MO, MONum);
}
// Check LiveInts liveness and kill.
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
2016-02-27 07:40:41 +01:00
if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
Also verify RegUnit intervals at uses. llvm-svn: 161147
2012-08-02 01:52:40 +02:00
// Check the cached regunit intervals.
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isPhysicalRegister(Reg) && !isReserved(Reg)) {
Also verify RegUnit intervals at uses. llvm-svn: 161147
2012-08-02 01:52:40 +02:00
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
LiveIntervalAnalysis: Fix alias regunit reserved definition A register in CodeGen can be marked as reserved: In that case we consider the register always live and do not use (or rather ignore) kill/dead/undef operand flags. LiveIntervalAnalysis however tracks liveness per register unit (not per register). We already needed adjustments for this in r292871 to deal with super/sub registers. However I did not look at aliased register there. Looking at ARM: FPSCR (regunits FPSCR, FPSCR~FPSCR_NZCV) aliases with FPSCR_NZCV (regunits FPSCR_NZCV, FPSCR~FPSCR_NZCV) hence they share a register unit (FPSCR~FPSCR_NZCV) that represents the aliased parts of the registers. This shared register unit was previously considered non-reserved, however given that we uses of the reserved FPSCR potentially violate some rules (like uses without defs) we should make FPSCR~FPSCR_NZCV reserved too and stop tracking liveness for it. This patch: - Defines a register unit as reserved when: At least for one root register, the root register and all its super registers are reserved. - Adjust LiveIntervals::computeRegUnitRange() for new reserved definition. - Add MachineRegisterInfo::isReservedRegUnit() to have a canonical way of testing. - Stop computing LiveRanges for reserved register units in HMEditor even with UpdateFlags enabled. - Skip verification of uses of reserved reg units in the machine verifier (this usually didn't happen because there would be no cached liverange but there is no guarantee for that and I would run into this case before the HMEditor tweak, so may as well fix the verifier too). Note that this should only affect ARMs FPSCR/FPSCR_NZCV registers today; aliased registers are rarely used, the only other cases are hexagons P0-P3/P3_0 and C8/USR pairs which are not mixing reserved/non-reserved registers in an alias. Differential Revision: https://reviews.llvm.org/D37356 llvm-svn: 312348
2017-09-01 20:36:26 +02:00
if (MRI->isReservedRegUnit(*Units))
continue;
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
}
Also verify RegUnit intervals at uses. llvm-svn: 161147
2012-08-02 01:52:40 +02:00
}
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isVirtualRegister(Reg)) {
Also verify RegUnit intervals at uses. llvm-svn: 161147
2012-08-02 01:52:40 +02:00
if (LiveInts->hasInterval(Reg)) {
// This is a virtual register interval.
const LiveInterval &LI = LiveInts->getInterval(Reg);
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
if (LI.hasSubRanges() && !MO->isDef()) {
unsigned SubRegIdx = MO->getSubReg();
LaneBitmask MOMask = SubRegIdx != 0
? TRI->getSubRegIndexLaneMask(SubRegIdx)
: MRI->getMaxLaneMaskForVReg(Reg);
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
LaneBitmask LiveInMask;
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
for (const LiveInterval::SubRange &SR : LI.subranges()) {
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
if ((MOMask & SR.LaneMask).none())
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
continue;
checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
LiveQueryResult LRQ = SR.Query(UseIdx);
if (LRQ.valueIn())
LiveInMask |= SR.LaneMask;
}
// At least parts of the register has to be live at the use.
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
if ((LiveInMask & MOMask).none()) {
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report("No live subrange at use", MO, MONum);
report_context(LI);
report_context(UseIdx);
}
Also verify RegUnit intervals at uses. llvm-svn: 161147
2012-08-02 01:52:40 +02:00
}
} else {
report("Virtual register has no live interval", MO, MONum);
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
}
}
}
// Use of a dead register.
if (!regsLive.count(Reg)) {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isPhysicalRegister(Reg)) {
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
// Reserved registers may be used even when 'dead'.
MachineVerifier: Allow physreg use if just a subreg is defined. We can't mark partially undefined registers, so we have to allow reading a register in the machine verifier if just parts of a register are defined. llvm-svn: 223896
2014-12-10 02:13:13 +01:00
bool Bad = !isReserved(Reg);
// We are fine if just any subregister has a defined value.
if (Bad) {
[MCRegInfo] Add forward sub and super register iterators. (NFC) This patch adds forward iterators mc_difflist_iterator, mc_subreg_iterator and mc_superreg_iterator, based on the existing DiffListIterator. Those are used to provide iterator ranges over sub- and super-register from TRI, which are slightly more convenient than the existing MCSubRegIterator/MCSuperRegIterator. Unfortunately, it duplicates a bit of functionality, but the new iterators are a bit more convenient (and can be used with various existing iterator utilities) and should probably replace the old iterators in the future. This patch updates some existing users. Reviewers: evandro, qcolombet, paquette, MatzeB, arsenm Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D70565
2019-12-05 10:16:08 +01:00
for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
if (regsLive.count(SubReg)) {
MachineVerifier: Allow physreg use if just a subreg is defined. We can't mark partially undefined registers, so we have to allow reading a register in the machine verifier if just parts of a register are defined. llvm-svn: 223896
2014-12-10 02:13:13 +01:00
Bad = false;
break;
}
}
}
MachineVerifier: Allow undef reads if a matching superreg is defined. Summary: Some pseudo instruction expansions break down a wide register use into multiple uses of smaller sub registers. If the super register was partially undefined the broken down sub registers may be completely undefined now leading to MachineVerifier complaints. Unfortunately liveness information to add the required dead flags is not easily (cheaply) available when expanding pseudo instructions. This commit changes the verifier to be quiet if there is an additional implicit use of a super register. Pseudo instruction expanders can use this to mark cases where partially defined values get potentially broken into completely undefined ones. Differential Revision: http://reviews.llvm.org/D6973 llvm-svn: 226047
2015-01-14 23:25:14 +01:00
// If there is an additional implicit-use of a super register we stop
// here. By definition we are fine if the super register is not
// (completely) dead, if the complete super register is dead we will
// get a report for its operand.
if (Bad) {
for (const MachineOperand &MOP : MI->uses()) {
MachineVerifier: Fix assert on implicit virtreg use If the liveness of a physical register was invalid, this was attempting to iterate the subregisters of all register uses of the instruction, which would assert when it encountered an implicit virtual register operand. llvm-svn: 340763
2018-08-27 19:40:09 +02:00
if (!MOP.isReg() || !MOP.isImplicit())
MachineVerifier: Allow undef reads if a matching superreg is defined. Summary: Some pseudo instruction expansions break down a wide register use into multiple uses of smaller sub registers. If the super register was partially undefined the broken down sub registers may be completely undefined now leading to MachineVerifier complaints. Unfortunately liveness information to add the required dead flags is not easily (cheaply) available when expanding pseudo instructions. This commit changes the verifier to be quiet if there is an additional implicit use of a super register. Pseudo instruction expanders can use this to mark cases where partially defined values get potentially broken into completely undefined ones. Differential Revision: http://reviews.llvm.org/D6973 llvm-svn: 226047
2015-01-14 23:25:14 +01:00
continue;
MachineVerifier: Fix assert on implicit virtreg use If the liveness of a physical register was invalid, this was attempting to iterate the subregisters of all register uses of the instruction, which would assert when it encountered an implicit virtual register operand. llvm-svn: 340763
2018-08-27 19:40:09 +02:00
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (!Register::isPhysicalRegister(MOP.getReg()))
MachineVerifier: Allow undef reads if a matching superreg is defined. Summary: Some pseudo instruction expansions break down a wide register use into multiple uses of smaller sub registers. If the super register was partially undefined the broken down sub registers may be completely undefined now leading to MachineVerifier complaints. Unfortunately liveness information to add the required dead flags is not easily (cheaply) available when expanding pseudo instructions. This commit changes the verifier to be quiet if there is an additional implicit use of a super register. Pseudo instruction expanders can use this to mark cases where partially defined values get potentially broken into completely undefined ones. Differential Revision: http://reviews.llvm.org/D6973 llvm-svn: 226047
2015-01-14 23:25:14 +01:00
continue;
MachineVerifier: Fix assert on implicit virtreg use If the liveness of a physical register was invalid, this was attempting to iterate the subregisters of all register uses of the instruction, which would assert when it encountered an implicit virtual register operand. llvm-svn: 340763
2018-08-27 19:40:09 +02:00
[MCRegInfo] Add forward sub and super register iterators. (NFC) This patch adds forward iterators mc_difflist_iterator, mc_subreg_iterator and mc_superreg_iterator, based on the existing DiffListIterator. Those are used to provide iterator ranges over sub- and super-register from TRI, which are slightly more convenient than the existing MCSubRegIterator/MCSuperRegIterator. Unfortunately, it duplicates a bit of functionality, but the new iterators are a bit more convenient (and can be used with various existing iterator utilities) and should probably replace the old iterators in the future. This patch updates some existing users. Reviewers: evandro, qcolombet, paquette, MatzeB, arsenm Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D70565
2019-12-05 10:16:08 +01:00
for (const MCPhysReg &SubReg : TRI->subregs(MOP.getReg())) {
if (SubReg == Reg) {
MachineVerifier: Allow undef reads if a matching superreg is defined. Summary: Some pseudo instruction expansions break down a wide register use into multiple uses of smaller sub registers. If the super register was partially undefined the broken down sub registers may be completely undefined now leading to MachineVerifier complaints. Unfortunately liveness information to add the required dead flags is not easily (cheaply) available when expanding pseudo instructions. This commit changes the verifier to be quiet if there is an additional implicit use of a super register. Pseudo instruction expanders can use this to mark cases where partially defined values get potentially broken into completely undefined ones. Differential Revision: http://reviews.llvm.org/D6973 llvm-svn: 226047
2015-01-14 23:25:14 +01:00
Bad = false;
break;
}
}
}
}
MachineVerifier: Allow physreg use if just a subreg is defined. We can't mark partially undefined registers, so we have to allow reading a register in the machine verifier if just parts of a register are defined. llvm-svn: 223896
2014-12-10 02:13:13 +01:00
if (Bad)
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
report("Using an undefined physical register", MO, MONum);
Fix crash in machine verifier when trying to print the def of a register which has no def llvm-svn: 160531
2012-07-20 01:40:38 +02:00
} else if (MRI->def_empty(Reg)) {
report("Reading virtual register without a def", MO, MONum);
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
} else {
BBInfo &MInfo = MBBInfoMap[MI->getParent()];
// We don't know which virtual registers are live in, so only complain
// if vreg was killed in this MBB. Otherwise keep track of vregs that
// must be live in. PHI instructions are handled separately.
if (MInfo.regsKilled.count(Reg))
report("Using a killed virtual register", MO, MONum);
else if (!MI->isPHI())
MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
}
}
}
if (MO->isDef()) {
// Register defined.
// TODO: verify that earlyclobber ops are not used.
if (MO->isDead())
addRegWithSubRegs(regsDead, Reg);
else
addRegWithSubRegs(regsDefined, Reg);
// Verify SSA form.
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (MRI->isSSA() && Register::isVirtualRegister(Reg) &&
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev. Remove the old functions. llvm-svn: 202636
2014-03-02 13:27:27 +01:00
std::next(MRI->def_begin(Reg)) != MRI->def_end())
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
report("Multiple virtual register defs in SSA form", MO, MONum);
Rename LiveRange to LiveInterval::Segment The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. llvm-svn: 192392
2013-10-10 23:28:43 +02:00
// Check LiveInts for a live segment, but only for virtual registers.
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
2016-02-27 07:40:41 +01:00
if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
Also verify the def index for early clobbers. llvm-svn: 159039
2012-06-23 00:23:58 +02:00
DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isVirtualRegister(Reg)) {
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
if (LiveInts->hasInterval(Reg)) {
const LiveInterval &LI = LiveInts->getInterval(Reg);
checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
if (LI.hasSubRanges()) {
unsigned SubRegIdx = MO->getSubReg();
LaneBitmask MOMask = SubRegIdx != 0
? TRI->getSubRegIndexLaneMask(SubRegIdx)
: MRI->getMaxLaneMaskForVReg(Reg);
for (const LiveInterval::SubRange &SR : LI.subranges()) {
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
if ((SR.LaneMask & MOMask).none())
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
continue;
[MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs Summary: Consider an instruction that has multiple defs of the same vreg, but defining different subregs: %7.sub1:rc, dead %7.sub2:rc = inst Calling checkLivenessAtDef for the live interval associated with %7 incorrectly reported "live range continues after a dead def". The live range for %7 has a dead def at the slot index for "inst" even if the live range continues (given that there are later uses of %7.sub1). This patch adjusts MachineVerifier::checkLivenessAtDef to allow dead subregister definitions, unless we are checking a subrange (when tracking subregister liveness). A limitation is that we do not detect the situation when the live range continues past an instruction that defines the full virtual register by multiple dead subreg defines. I also removed some dead code related to physical register in checkLivenessAtDef. Wwe only call that method for virtual registers, so I added an assertion instead. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52237 llvm-svn: 342618
2018-09-20 08:59:18 +02:00
checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
}
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
}
} else {
MachineVerifier: Check that defs/uses are live in subregisters as well. llvm-svn: 259552
2016-02-02 21:04:51 +01:00
report("Virtual register has no Live interval", MO, MONum);
Skip liveness verification when MRI->tracksLiveness() is false. Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. llvm-svn: 153596
2012-03-28 22:47:35 +02:00
}
}
}
}
}
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
Properly verify liveness with bundled machine instructions. Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. llvm-svn: 158116
2012-06-07 00:34:30 +02:00
// This function gets called after visiting all instructions in a bundle. The
// argument points to the bundle header.
// Normal stand-alone instructions are also considered 'bundles', and this
// function is called for all of them.
void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
BBInfo &MInfo = MBBInfoMap[MI->getParent()];
set_union(MInfo.regsKilled, regsKilled);
Remove double-def checking from MachineVerifier, so a register does not have to be killed before being redefined. These checks are usually disabled, and usually fail when enabled. We de facto allow live registers to be redefined without a kill, the corresponding assertions in RegScavenger were removed long ago. llvm-svn: 110362
2010-08-05 20:59:59 +02:00
set_subtract(regsLive, regsKilled); regsKilled.clear();
Handle regmasks in the machine code verifier. llvm-svn: 151607
2012-02-28 02:42:41 +01:00
// Kill any masked registers.
while (!regMasks.empty()) {
const uint32_t *Mask = regMasks.pop_back_val();
for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isPhysicalRegister(*I) &&
Handle regmasks in the machine code verifier. llvm-svn: 151607
2012-02-28 02:42:41 +01:00
MachineOperand::clobbersPhysReg(Mask, *I))
regsDead.push_back(*I);
}
Remove double-def checking from MachineVerifier, so a register does not have to be killed before being redefined. These checks are usually disabled, and usually fail when enabled. We de facto allow live registers to be redefined without a kill, the corresponding assertions in RegScavenger were removed long ago. llvm-svn: 110362
2010-08-05 20:59:59 +02:00
set_subtract(regsLive, regsDead); regsDead.clear();
set_union(regsLive, regsDefined); regsDefined.clear();
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
void
Whitespace and formatting. llvm-svn: 83285
2009-10-04 20:18:39 +02:00
MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
MBBInfoMap[MBB].regsLiveOut = regsLive;
regsLive.clear();
Verify slot index ordering. The slot indexes must be monotonically increasing through the function. llvm-svn: 123324
2011-01-12 22:27:48 +01:00
if (Indexes) {
SlotIndex stop = Indexes->getMBBEndIdx(MBB);
if (!(stop > lastIndex)) {
report("Block ends before last instruction index", MBB);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "Block ends at " << stop
Verify slot index ordering. The slot indexes must be monotonically increasing through the function. llvm-svn: 123324
2011-01-12 22:27:48 +01:00
<< " last instruction was at " << lastIndex << '\n';
}
lastIndex = stop;
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
// Calculate the largest possible vregsPassed sets. These are the registers that
// can pass through an MBB live, but may not be live every time. It is assumed
// that all vregsPassed sets are empty before the call.
Remove livein checks from machine code verifier. A phi operand that is implicitly defined in a predecessor becomes an undefined register after phi elimination. This causes a lot of false positives when the verifier is checking if live-in registers are live-out from all predecessors. Removing the verifier checks seems like a better solution than insisting on IMPLICIT_DEF instructions in predecessor blocks. llvm-svn: 92769
2010-01-05 21:59:36 +01:00
void MachineVerifier::calcRegsPassed() {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
// First push live-out regs to successors' vregsPassed. Remember the MBBs that
// have any vregsPassed.
Use SmallPtrSet instead of DenseSet. llvm-svn: 152457
2012-03-10 01:36:04 +01:00
SmallPtrSet<const MachineBasicBlock*, 8> todo;
Convert several loops over MachineFunction basic blocks to range-based loops llvm-svn: 207683
2014-04-30 20:29:51 +02:00
for (const auto &MBB : *MF) {
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
BBInfo &MInfo = MBBInfoMap[&MBB];
if (!MInfo.reachable)
continue;
for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
BBInfo &SInfo = MBBInfoMap[*SuI];
if (SInfo.addPassed(MInfo.regsLiveOut))
todo.insert(*SuI);
}
}
// Iteratively push vregsPassed to successors. This will converge to the same
// final state regardless of DenseSet iteration order.
while (!todo.empty()) {
const MachineBasicBlock *MBB = *todo.begin();
todo.erase(MBB);
BBInfo &MInfo = MBBInfoMap[MBB];
for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
if (*SuI == MBB)
continue;
BBInfo &SInfo = MBBInfoMap[*SuI];
if (SInfo.addPassed(MInfo.vregsPassed))
todo.insert(*SuI);
}
}
}
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
// Calculate the set of virtual registers that must be passed through each basic
// block in order to satisfy the requirements of successor blocks. This is very
Remove livein checks from machine code verifier. A phi operand that is implicitly defined in a predecessor becomes an undefined register after phi elimination. This causes a lot of false positives when the verifier is checking if live-in registers are live-out from all predecessors. Removing the verifier checks seems like a better solution than insisting on IMPLICIT_DEF instructions in predecessor blocks. llvm-svn: 92769
2010-01-05 21:59:36 +01:00
// similar to calcRegsPassed, only backwards.
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
void MachineVerifier::calcRegsRequired() {
// First push live-in regs to predecessors' vregsRequired.
Use SmallPtrSet instead of DenseSet. llvm-svn: 152457
2012-03-10 01:36:04 +01:00
SmallPtrSet<const MachineBasicBlock*, 8> todo;
Convert several loops over MachineFunction basic blocks to range-based loops llvm-svn: 207683
2014-04-30 20:29:51 +02:00
for (const auto &MBB : *MF) {
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
BBInfo &MInfo = MBBInfoMap[&MBB];
for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
BBInfo &PInfo = MBBInfoMap[*PrI];
if (PInfo.addRequired(MInfo.vregsLiveIn))
todo.insert(*PrI);
}
}
// Iteratively push vregsRequired to predecessors. This will converge to the
// same final state regardless of DenseSet iteration order.
while (!todo.empty()) {
const MachineBasicBlock *MBB = *todo.begin();
todo.erase(MBB);
BBInfo &MInfo = MBBInfoMap[MBB];
for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
if (*PrI == MBB)
continue;
BBInfo &SInfo = MBBInfoMap[*PrI];
if (SInfo.addRequired(MInfo.vregsRequired))
todo.insert(*PrI);
}
}
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
// Check PHI instructions at the beginning of MBB. It is assumed that
Remove livein checks from machine code verifier. A phi operand that is implicitly defined in a predecessor becomes an undefined register after phi elimination. This causes a lot of false positives when the verifier is checking if live-in registers are live-out from all predecessors. Removing the verifier checks seems like a better solution than insisting on IMPLICIT_DEF instructions in predecessor blocks. llvm-svn: 92769
2010-01-05 21:59:36 +01:00
// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
BBInfo &MInfo = MBBInfoMap[&MBB];
Use SmallPtrSet instead of DenseSet. llvm-svn: 152457
2012-03-10 01:36:04 +01:00
SmallPtrSet<const MachineBasicBlock*, 8> seen;
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
for (const MachineInstr &Phi : MBB) {
if (!Phi.isPHI())
Convert more loops to range-based equivalents llvm-svn: 207714
2014-05-01 00:17:38 +02:00
break;
Use SmallPtrSet instead of DenseSet. llvm-svn: 152457
2012-03-10 01:36:04 +01:00
seen.clear();
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
const MachineOperand &MODef = Phi.getOperand(0);
if (!MODef.isReg() || !MODef.isDef()) {
report("Expected first PHI operand to be a register def", &MODef, 0);
continue;
}
if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
MODef.isEarlyClobber() || MODef.isDebug())
report("Unexpected flag on PHI operand", &MODef, 0);
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM Summary: This clang-tidy check is looking for unsigned integer variables whose initializer starts with an implicit cast from llvm::Register and changes the type of the variable to llvm::Register (dropping the llvm:: where possible). Partial reverts in: X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned& MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register PPCFastISel.cpp - No Register::operator-=() PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned& MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor Manual fixups in: ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned& HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register. PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned& Depends on D65919 Reviewers: arsenm, bogner, craig.topper, RKSimon Reviewed By: arsenm Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65962 llvm-svn: 369041
2019-08-15 21:22:08 +02:00
Register DefReg = MODef.getReg();
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (!Register::isVirtualRegister(DefReg))
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
report("Expected first PHI operand to be a virtual register", &MODef, 0);
for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
const MachineOperand &MO0 = Phi.getOperand(I);
if (!MO0.isReg()) {
report("Expected PHI operand to be a register", &MO0, I);
continue;
}
if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
MO0.isDebug() || MO0.isTied())
report("Unexpected flag on PHI operand", &MO0, I);
const MachineOperand &MO1 = Phi.getOperand(I + 1);
if (!MO1.isMBB()) {
report("Expected PHI operand to be a basic block", &MO1, I + 1);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
continue;
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
}
const MachineBasicBlock &Pre = *MO1.getMBB();
if (!Pre.isSuccessor(&MBB)) {
report("PHI input is not a predecessor block", &MO1, I + 1);
continue;
}
if (MInfo.reachable) {
seen.insert(&Pre);
BBInfo &PrInfo = MBBInfoMap[&Pre];
MachineVerifier: undef phi arg doesn't need to be live-out from predecessor Differential Revision: https://reviews.llvm.org/D40756 llvm-svn: 319674
2017-12-04 19:57:48 +01:00
if (!MO0.isUndef() && PrInfo.reachable &&
!PrInfo.isLiveOut(MO0.getReg()))
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
report("PHI operand is not live-out from predecessor", &MO0, I);
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
// Did we see all predecessors?
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
if (MInfo.reachable) {
for (MachineBasicBlock *Pred : MBB.predecessors()) {
if (!seen.count(Pred)) {
report("Missing PHI operand", &Phi);
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 18:18:51 +01:00
errs() << printMBBReference(*Pred)
<< " is a predecessor according to the CFG.\n";
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
}
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
}
}
}
Whitespace and formatting. llvm-svn: 83285
2009-10-04 20:18:39 +02:00
void MachineVerifier::visitMachineFunctionAfter() {
Remove livein checks from machine code verifier. A phi operand that is implicitly defined in a predecessor becomes an undefined register after phi elimination. This causes a lot of false positives when the verifier is checking if live-in registers are live-out from all predecessors. Removing the verifier checks seems like a better solution than insisting on IMPLICIT_DEF instructions in predecessor blocks. llvm-svn: 92769
2010-01-05 21:59:36 +01:00
calcRegsPassed();
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
Revert "[PHIEliminate] Move dbg values after phi and label" Testing compiler-rt, a new assertion failure occurs when building the GwpAsanTestObjects object. I'm uploading a reproducer to D70597. This reverts commit 75188b01e9af3a89639d84be912f84610d6885ba.
2020-01-16 15:01:27 +01:00
for (const MachineBasicBlock &MBB : *MF)
MachineVerifier: Improve PHI operand checking Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
2017-11-28 04:54:19 +01:00
checkPHIOps(MBB);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
// Now check liveness info if available
Add SSA verification to MachineVerifier. Somehow we never verified SSA dominance before. llvm-svn: 152458
2012-03-10 01:36:06 +01:00
calcRegsRequired();
Check for extra kill flags on live-out virtual registers. This would previously get reported as the misleading "Virtual register def doesn't dominate all uses." llvm-svn: 159460
2012-06-29 23:00:00 +02:00
// Check for killed virtual registers that should be live out.
Convert several loops over MachineFunction basic blocks to range-based loops llvm-svn: 207683
2014-04-30 20:29:51 +02:00
for (const auto &MBB : *MF) {
BBInfo &MInfo = MBBInfoMap[&MBB];
Check for extra kill flags on live-out virtual registers. This would previously get reported as the misleading "Virtual register def doesn't dominate all uses." llvm-svn: 159460
2012-06-29 23:00:00 +02:00
for (RegSet::iterator
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
++I)
if (MInfo.regsKilled.count(*I)) {
Convert several loops over MachineFunction basic blocks to range-based loops llvm-svn: 207683
2014-04-30 20:29:51 +02:00
report("Virtual register killed in block, but needed live out.", &MBB);
[CodeGen] Rename functions PrintReg* to printReg* LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
2017-11-28 13:42:37 +01:00
errs() << "Virtual register " << printReg(*I)
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-11-30 17:12:24 +01:00
<< " is used after the block.\n";
Check for extra kill flags on live-out virtual registers. This would previously get reported as the misleading "Virtual register def doesn't dominate all uses." llvm-svn: 159460
2012-06-29 23:00:00 +02:00
}
}
Enforce stricter liveness rules for PHIs. Verify that all paths from the entry block to a virtual register read pass through a def. Enable this check even when MRI->isSSA() is false. Verify that the live range of a virtual register is live out of all predecessor blocks, even for PHI-values. This requires that PHIElimination sometimes inserts IMPLICIT_DEF instruction in predecessor blocks. llvm-svn: 159150
2012-06-25 20:18:27 +02:00
if (!MF->empty()) {
Add SSA verification to MachineVerifier. Somehow we never verified SSA dominance before. llvm-svn: 152458
2012-03-10 01:36:06 +01:00
BBInfo &MInfo = MBBInfoMap[&MF->front()];
for (RegSet::iterator
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
MachineVerifier: Fix error reporting. Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
2016-05-11 23:31:39 +02:00
++I) {
report("Virtual register defs don't dominate all uses.", MF);
report_context_vreg(*I);
}
Add SSA verification to MachineVerifier. Somehow we never verified SSA dominance before. llvm-svn: 152458
2012-03-10 01:36:06 +01:00
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
if (LiveVars)
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
verifyLiveVariables();
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
if (LiveInts)
verifyLiveIntervals();
[MachineFunction] Base support for call site info tracking Add an attribute into the MachineFunction that tracks call site info. ([8/13] Introduce the debug entry values.) Co-authored-by: Ananth Sowda <asowda@cisco.com> Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com> Co-authored-by: Ivan Baev <ibaev@cisco.com> Differential Revision: https://reviews.llvm.org/D61061 llvm-svn: 364506
2019-06-27 09:48:06 +02:00
Recommit "[MachineVerifier] Improve verification of live-in lists." MachineVerifier::visitMachineFunctionAfter() is extended to check the live-through case for live-in lists. This is only done for registers without aliases and that are neither allocatable or reserved, such as the SystemZ::CC register. The MachineVerifier earlier only catched the case of a live-in use without an entry in the live-in list (as "using an undefined physical register"). A comment in LivePhysRegs.h has been added stating a guarantee that addLiveOuts() can be trusted for a full register both before and after register allocation. Review: Quentin Colombet Differential Revision: https://reviews.llvm.org/D68267
2019-11-19 12:34:49 +01:00
// Check live-in list of each MBB. If a register is live into MBB, check
// that the register is in regsLiveOut of each predecessor block. Since
// this must come from a definition in the predecesssor or its live-in
// list, this will catch a live-through case where the predecessor does not
// have the register in its live-in list. This currently only checks
// registers that have no aliases, are not allocatable and are not
// reserved, which could mean a condition code register for instance.
if (MRI->tracksLiveness())
for (const auto &MBB : *MF)
for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
MCPhysReg LiveInReg = P.PhysReg;
bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
continue;
for (const MachineBasicBlock *Pred : MBB.predecessors()) {
BBInfo &PInfo = MBBInfoMap[Pred];
if (!PInfo.regsLiveOut.count(LiveInReg)) {
report("Live in register not found to be live out from predecessor.",
&MBB);
errs() << TRI->getName(LiveInReg)
<< " not found to be live out from "
<< printMBBReference(*Pred) << "\n";
}
}
}
[MachineFunction] Base support for call site info tracking Add an attribute into the MachineFunction that tracks call site info. ([8/13] Introduce the debug entry values.) Co-authored-by: Ananth Sowda <asowda@cisco.com> Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com> Co-authored-by: Ivan Baev <ibaev@cisco.com> Differential Revision: https://reviews.llvm.org/D61061 llvm-svn: 364506
2019-06-27 09:48:06 +02:00
for (auto CSInfo : MF->getCallSitesInfo())
if (!CSInfo.first->isCall())
report("Call site info referencing instruction that is not call", MF);
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. llvm-svn: 71918
2009-05-16 02:33:53 +02:00
}
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
void MachineVerifier::verifyLiveVariables() {
assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
Fix a MachineVerifier loop that probably didn't mean to skip the last two virtual registers. llvm-svn: 123100
2011-01-09 00:11:02 +01:00
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
unsigned Reg = Register::index2VirtReg(i);
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
Convert several loops over MachineFunction basic blocks to range-based loops llvm-svn: 207683
2014-04-30 20:29:51 +02:00
for (const auto &MBB : *MF) {
BBInfo &MInfo = MBBInfoMap[&MBB];
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
// Our vregsRequired should be identical to LiveVariables' AliveBlocks
if (MInfo.vregsRequired.count(Reg)) {
Convert several loops over MachineFunction basic blocks to range-based loops llvm-svn: 207683
2014-04-30 20:29:51 +02:00
if (!VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", &MBB);
[CodeGen] Rename functions PrintReg* to printReg* LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
2017-11-28 13:42:37 +01:00
errs() << "Virtual register " << printReg(Reg)
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-11-30 17:12:24 +01:00
<< " must be live through the block.\n";
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
}
} else {
Convert several loops over MachineFunction basic blocks to range-based loops llvm-svn: 207683
2014-04-30 20:29:51 +02:00
if (VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", &MBB);
[CodeGen] Rename functions PrintReg* to printReg* LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
2017-11-28 13:42:37 +01:00
errs() << "Virtual register " << printReg(Reg)
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-11-30 17:12:24 +01:00
<< " is not needed live through the block.\n";
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. llvm-svn: 89241
2009-11-18 21:36:57 +01:00
}
}
}
}
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
void MachineVerifier::verifyLiveIntervals() {
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
Fix some more LiveInterval enumerations. Deterministically enumerate the virtual registers instead. llvm-svn: 158872
2012-06-21 01:23:59 +02:00
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
unsigned Reg = Register::index2VirtReg(i);
Skip unused registers when verifying LiveIntervals. llvm-svn: 115874
2010-10-07 01:54:35 +02:00
// Spilling and splitting may leave unused registers around. Skip them.
Fix some more LiveInterval enumerations. Deterministically enumerate the virtual registers instead. llvm-svn: 158872
2012-06-21 01:23:59 +02:00
if (MRI->reg_nodbg_empty(Reg))
Skip unused registers when verifying LiveIntervals. llvm-svn: 115874
2010-10-07 01:54:35 +02:00
continue;
Fix some more LiveInterval enumerations. Deterministically enumerate the virtual registers instead. llvm-svn: 158872
2012-06-21 01:23:59 +02:00
if (!LiveInts->hasInterval(Reg)) {
report("Missing live interval for virtual register", MF);
[CodeGen] Rename functions PrintReg* to printReg* LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
2017-11-28 13:42:37 +01:00
errs() << printReg(Reg, TRI) << " still has defs or uses\n";
One day, physical register live ranges will be sensible. llvm-svn: 117602
2010-10-28 22:44:22 +02:00
continue;
Fix some more LiveInterval enumerations. Deterministically enumerate the virtual registers instead. llvm-svn: 158872
2012-06-21 01:23:59 +02:00
}
One day, physical register live ranges will be sensible. llvm-svn: 117602
2010-10-28 22:44:22 +02:00
Fix some more LiveInterval enumerations. Deterministically enumerate the virtual registers instead. llvm-svn: 158872
2012-06-21 01:23:59 +02:00
const LiveInterval &LI = LiveInts->getInterval(Reg);
assert(Reg == LI.reg && "Invalid reg to interval mapping");
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
verifyLiveInterval(LI);
}
Verify regunit intervals along with virtreg intervals. Don't cause regunit intervals to be computed just to verify them. Only check the already cached intervals. llvm-svn: 161183
2012-08-02 18:36:50 +02:00
// Verify all the cached regunit intervals.
for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
Represent RegUnit liveness with LiveRange instance Previously LiveInterval has been used, but having a spill weight and register number is unnecessary for a register unit. llvm-svn: 192397
2013-10-10 23:29:02 +02:00
if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
verifyLiveRange(*LR, i);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
LiveInterval: Add support to track liveness of subregisters. This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
2014-12-10 02:12:10 +01:00
const VNInfo *VNI, unsigned Reg,
TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC llvm-svn: 248623
2015-09-25 23:51:14 +02:00
LaneBitmask LaneMask) {
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (VNI->isUnused())
return;
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (!DefVNI) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Value not live at VNInfo def and not marked unused", MF);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
return;
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (DefVNI != VNI) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Live segment at def has different VNInfo", MF);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
return;
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
if (!MBB) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Invalid VNInfo definition index", MF);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
return;
}
Add more verification of LiveIntervals. llvm-svn: 117170
2010-10-23 00:48:58 +02:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (VNI->isPHIDef()) {
if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("PHIDef VNInfo is not defined at MBB start", MBB);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
return;
}
Teach MachineVerifier that early clobber defs begin at USE slots and other defs begin at DEF slots. Fixes the second half of PR8813. llvm-svn: 122225
2010-12-20 04:15:20 +01:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// Non-PHI def.
const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
if (!MI) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("No instruction at VNInfo def index", MBB);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
return;
}
Update machine code verifier. After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. llvm-svn: 151531
2012-02-27 19:24:30 +01:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (Reg != 0) {
bool hasDef = false;
bool isEarlyClobber = false;
WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC Update APIs in MachineInstrBundle.h to take and return MachineInstr& instead of MachineInstr* when the instruction cannot be null. Besides being a nice cleanup, this is tacking toward a fix for PR26753. llvm-svn: 262141
2016-02-27 18:05:33 +01:00
for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (!MOI->isReg() || !MOI->isDef())
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
continue;
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isVirtualRegister(Reg)) {
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (MOI->getReg() != Reg)
continue;
} else {
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (!Register::isPhysicalRegister(MOI->getReg()) ||
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
!TRI->hasRegUnit(MOI->getReg(), Reg))
continue;
}
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if (LaneMask.any() &&
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
(TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
LiveInterval: Add support to track liveness of subregisters. This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
2014-12-10 02:12:10 +01:00
continue;
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
hasDef = true;
if (MOI->isEarlyClobber())
isEarlyClobber = true;
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
Teach MachineVerifier that early clobber defs begin at USE slots and other defs begin at DEF slots. Fixes the second half of PR8813. llvm-svn: 122225
2010-12-20 04:15:20 +01:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (!hasDef) {
report("Defining instruction does not modify register", MI);
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
}
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
// Early clobber defs begin at USE slots, but other defs must begin at
// DEF slots.
if (isEarlyClobber) {
if (!VNI->def.isEarlyClobber()) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Early clobber def must be at an early-clobber slot", MBB);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
}
} else if (!VNI->def.isRegister()) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Non-PHI, non-early clobber def must be at a register slot", MBB);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
}
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
const LiveRange::const_iterator I,
TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC llvm-svn: 248623
2015-09-25 23:51:14 +02:00
unsigned Reg, LaneBitmask LaneMask)
{
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
const LiveRange::Segment &S = *I;
const VNInfo *VNI = S.valno;
Rename LiveRange to LiveInterval::Segment The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. llvm-svn: 192392
2013-10-10 23:28:43 +02:00
assert(VNI && "Live segment has no valno");
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Foreign valno in live segment", MF);
report_context(LR, Reg, LaneMask);
report_context(S);
report_context(*VNI);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (VNI->isUnused()) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Live segment valno is marked unused", MF);
report_context(LR, Reg, LaneMask);
report_context(S);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (!MBB) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Bad start of live segment, no basic block", MF);
report_context(LR, Reg, LaneMask);
report_context(S);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
return;
}
SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (S.start != MBBStartIdx && S.start != VNI->def) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Live segment must begin at MBB entry or valno def", MBB);
report_context(LR, Reg, LaneMask);
report_context(S);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
const MachineBasicBlock *EndMBB =
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
LiveInts->getMBBFromIndex(S.end.getPrevSlot());
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (!EndMBB) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Bad end of live segment, no basic block", MF);
report_context(LR, Reg, LaneMask);
report_context(S);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
return;
}
Verify LiveIntervals against the CFG, ensuring that live-in values are live-out of all predecessors. llvm-svn: 117191
2010-10-23 02:49:09 +02:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// No more checks for live-out segments.
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (S.end == LiveInts->getMBBEndIdx(EndMBB))
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
return;
Verify regunit intervals along with virtreg intervals. Don't cause regunit intervals to be computed just to verify them. Only check the already cached intervals. llvm-svn: 161183
2012-08-02 18:36:50 +02:00
// RegUnit intervals are allowed dead phis.
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
S.start == VNI->def && S.end == VNI->def.getDeadSlot())
Verify regunit intervals along with virtreg intervals. Don't cause regunit intervals to be computed just to verify them. Only check the already cached intervals. llvm-svn: 161183
2012-08-02 18:36:50 +02:00
return;
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// The live segment is ending inside EndMBB
const MachineInstr *MI =
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (!MI) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Live segment doesn't end at a valid instruction", EndMBB);
report_context(LR, Reg, LaneMask);
report_context(S);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
return;
}
Update machine code verifier. After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. llvm-svn: 151531
2012-02-27 19:24:30 +01:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// The block slot must refer to a basic block boundary.
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (S.end.isBlock()) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Live segment ends at B slot of an instruction", EndMBB);
report_context(LR, Reg, LaneMask);
report_context(S);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
Update machine code verifier. After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. llvm-svn: 151531
2012-02-27 19:24:30 +01:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (S.end.isDead()) {
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// Segment ends on the dead slot.
// That means there must be a dead def.
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (!SlotIndex::isSameInstr(S.start, S.end)) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Live segment ending at dead slot spans instructions", EndMBB);
report_context(LR, Reg, LaneMask);
report_context(S);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
}
// A live segment can only end at an early-clobber slot if it is being
// redefined by an early-clobber def.
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (S.end.isEarlyClobber()) {
if (I+1 == LR.end() || (I+1)->start != S.end) {
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
report("Live segment ending at early clobber slot must be "
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
"redefined by an EC def in the same instruction", EndMBB);
report_context(LR, Reg, LaneMask);
report_context(S);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
}
// The following checks only apply to virtual registers. Physreg liveness
// is too weird to check.
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (Register::isVirtualRegister(Reg)) {
Rename LiveRange to LiveInterval::Segment The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. llvm-svn: 192392
2013-10-10 23:28:43 +02:00
// A live segment can end with either a redefinition, a kill flag on a
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// use, or a dead flag on a def.
bool hasRead = false;
MachineVerifier: Allow LiveInterval segments to end at a partial write. In the subregister liveness tracking case we do not create implicit reads on partial register writes anymore, still we need to produce a new SSA value for partial writes so the live segment has to end. llvm-svn: 223895
2014-12-10 02:13:11 +01:00
bool hasSubRegDef = false;
MachineVerifier: On dead-def live segments, check that corresponding machine operand has a dead flag llvm-svn: 264769
2016-03-29 21:07:43 +02:00
bool hasDeadDef = false;
WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC Update APIs in MachineInstrBundle.h to take and return MachineInstr& instead of MachineInstr* when the instruction cannot be null. Besides being a nice cleanup, this is tacking toward a fix for PR26753. llvm-svn: 262141
2016-02-27 18:05:33 +01:00
for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (!MOI->isReg() || MOI->getReg() != Reg)
Update machine code verifier. After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. llvm-svn: 151531
2012-02-27 19:24:30 +01:00
continue;
Create subranges for new intervals resulting from live interval splitting The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
2016-08-24 15:37:55 +02:00
unsigned Sub = MOI->getSubReg();
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
: LaneBitmask::getAll();
MachineVerifier: On dead-def live segments, check that corresponding machine operand has a dead flag llvm-svn: 264769
2016-03-29 21:07:43 +02:00
if (MOI->isDef()) {
Create subranges for new intervals resulting from live interval splitting The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
2016-08-24 15:37:55 +02:00
if (Sub != 0) {
MachineVerifier: On dead-def live segments, check that corresponding machine operand has a dead flag llvm-svn: 264769
2016-03-29 21:07:43 +02:00
hasSubRegDef = true;
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' llvm-svn: 320022
2017-12-07 11:40:31 +01:00
// An operand %0:sub0 reads %0:sub1..n. Invert the lane
Create subranges for new intervals resulting from live interval splitting The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
2016-08-24 15:37:55 +02:00
// mask for subregister defs. Read-undef defs will be handled by
// readsReg below.
Do not use MRI::getMaxLaneMaskForVReg as a mask covering whole register MRI::getMaxLaneMaskForVReg does not always cover the whole register. For example, on X86 the upper 16 bits of EAX cannot be accessed via any subregister. Consequently, there is no lane mask that only covers that part of EAX. The getMaxLaneMaskForVReg will return the union of the lane masks for all subregisters, and in case of EAX, that union will not cover the upper 16 bits. This fixes https://llvm.org/bugs/show_bug.cgi?id=29132 llvm-svn: 279969
2016-08-29 15:15:35 +02:00
SLM = ~SLM;
Create subranges for new intervals resulting from live interval splitting The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
2016-08-24 15:37:55 +02:00
}
MachineVerifier: On dead-def live segments, check that corresponding machine operand has a dead flag llvm-svn: 264769
2016-03-29 21:07:43 +02:00
if (MOI->isDead())
hasDeadDef = true;
}
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if (LaneMask.any() && (LaneMask & SLM).none())
Create subranges for new intervals resulting from live interval splitting The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
2016-08-24 15:37:55 +02:00
continue;
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (MOI->readsReg())
hasRead = true;
}
MachineVerifier: On dead-def live segments, check that corresponding machine operand has a dead flag llvm-svn: 264769
2016-03-29 21:07:43 +02:00
if (S.end.isDead()) {
// Make sure that the corresponding machine operand for a "dead" live
// range has the dead flag. We cannot perform this check for subregister
// liveranges as partially dead values are allowed.
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
if (LaneMask.none() && !hasDeadDef) {
MachineVerifier: On dead-def live segments, check that corresponding machine operand has a dead flag llvm-svn: 264769
2016-03-29 21:07:43 +02:00
report("Instruction ending live segment on dead slot has no dead flag",
MI);
report_context(LR, Reg, LaneMask);
report_context(S);
}
} else {
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (!hasRead) {
MachineVerifier: Allow LiveInterval segments to end at a partial write. In the subregister liveness tracking case we do not create implicit reads on partial register writes anymore, still we need to produce a new SSA value for partial writes so the live segment has to end. llvm-svn: 223895
2014-12-10 02:13:11 +01:00
// When tracking subregister liveness, the main range must start new
// values on partial register writes, even if there is no read.
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
Do not track subregister liveness when it brings no benefits Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
2015-03-19 01:21:58 +01:00
!hasSubRegDef) {
MachineVerifier: Allow LiveInterval segments to end at a partial write. In the subregister liveness tracking case we do not create implicit reads on partial register writes anymore, still we need to produce a new SSA value for partial writes so the live segment has to end. llvm-svn: 223895
2014-12-10 02:13:11 +01:00
report("Instruction ending live segment doesn't read the register",
MI);
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report_context(LR, Reg, LaneMask);
report_context(S);
MachineVerifier: Allow LiveInterval segments to end at a partial write. In the subregister liveness tracking case we do not create implicit reads on partial register writes anymore, still we need to produce a new SSA value for partial writes so the live segment has to end. llvm-svn: 223895
2014-12-10 02:13:11 +01:00
}
Update machine code verifier. After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. llvm-svn: 151531
2012-02-27 19:24:30 +01:00
}
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
}
}
Update machine code verifier. After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. llvm-svn: 151531
2012-02-27 19:24:30 +01:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// Now check all the basic blocks in this live segment.
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
MachineFunction::const_iterator MFI = MBB->getIterator();
Rename LiveRange to LiveInterval::Segment The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. llvm-svn: 192392
2013-10-10 23:28:43 +02:00
// Is this live segment the beginning of a non-PHIDef VN?
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
if (S.start == VNI->def && !VNI->isPHIDef()) {
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// Not live-in to any blocks.
if (MBB == EndMBB)
return;
// Skip this block.
++MFI;
}
[MachineVerifier] Check if predecessor is jointly dominated by undefs Each use of a value should be jointly dominated by the union of defs and undefs. It can happen that it will only be jointly dominated by undefs, and that is still legal. Make sure that the verifier is aware of that. llvm-svn: 339924
2018-08-16 21:13:28 +02:00
SmallVector<SlotIndex, 4> Undefs;
if (LaneMask.any()) {
LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
}
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
while (true) {
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
assert(LiveInts->isLiveInToMBB(LR, &*MFI));
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// We don't know how to track physregs into a landing pad.
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (&*MFI == EndMBB)
break;
++MFI;
continue;
}
Verify LiveIntervals against the CFG, ensuring that live-in values are live-out of all predecessors. llvm-svn: 117191
2010-10-23 02:49:09 +02:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// Is VNI a PHI-def in the current block?
bool IsPHI = VNI->isPHIDef() &&
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
VNI->def == LiveInts->getMBBStartIdx(&*MFI);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// Check that VNI is live-out of all predecessors.
for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
PE = MFI->pred_end(); PI != PE; ++PI) {
SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
RegAllocPBQP: Do not assign reserved physical register (0) RegAllocPBQP: Since getRawAllocationOrder() may return a collection that includes reserved physical registers, iterate to find an un-reserved physical register. (1) VirtRegMap: Enforce the invariant: "no reserved physical registers" in assignVirt2Phys(). Previously, this was checked only after the fact in VirtRegRewriter::rewrite. (2) MachineVerifier: updated the test per MatzeB's review. (3) +testcase Patch by Nick Johnson<Nicholas.Paul.Johnson@deshawresearch.com>! Differential Revision: https://reviews.llvm.org/D33947 llvm-svn: 305016
2017-06-08 23:30:54 +02:00
// All predecessors must have a live-out value. However for a phi
// instruction with subregister intervals
// only one of the subregisters (not necessarily the current one) needs to
// be defined.
[MachineVerifier] Check if predecessor is jointly dominated by undefs Each use of a value should be jointly dominated by the union of defs and undefs. It can happen that it will only be jointly dominated by undefs, and that is still legal. Make sure that the verifier is aware of that. llvm-svn: 339924
2018-08-16 21:13:28 +02:00
if (!PVNI && (LaneMask.none() || !IsPHI)) {
if (LiveRangeCalc::isJointlyDominated(*PI, Undefs, *Indexes))
continue;
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Register not marked live out of predecessor", *PI);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 18:18:51 +01:00
errs() << " live into " << printMBBReference(*MFI) << '@'
<< LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
<< PEnd << '\n';
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
continue;
Verify LiveIntervals against the CFG, ensuring that live-in values are live-out of all predecessors. llvm-svn: 117191
2010-10-23 02:49:09 +02:00
}
Simplify some code in MachineVerifier that was doing the correct thing, but not in the most obvious way. llvm-svn: 122610
2010-12-29 00:45:38 +01:00
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// Only PHI-defs can take different predecessor values.
if (!IsPHI && PVNI != VNI) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Different value live out of predecessor", *PI);
report_context(LR, Reg, LaneMask);
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 18:18:51 +01:00
errs() << "Valno #" << PVNI->id << " live out of "
<< printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
<< VNI->id << " live into " << printMBBReference(*MFI) << '@'
CodeGen: Continue removing ilist iterator implicit conversions llvm-svn: 249884
2015-10-09 21:40:45 +02:00
<< LiveInts->getMBBStartIdx(&*MFI) << '\n';
Verify LiveIntervals against the CFG, ensuring that live-in values are live-out of all predecessors. llvm-svn: 117191
2010-10-23 02:49:09 +02:00
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
}
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
if (&*MFI == EndMBB)
break;
++MFI;
}
}
Verify that live intervals are connected. If there are multiple connected components, each should get its own virtual register. llvm-svn: 117407
2010-10-27 00:36:07 +02:00
LiveInterval: Add support to track liveness of subregisters. This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
2014-12-10 02:12:10 +01:00
void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC llvm-svn: 248623
2015-09-25 23:51:14 +02:00
LaneBitmask LaneMask) {
LiveInterval: Use more range based for loops for value numbers and segments. llvm-svn: 223978
2014-12-11 00:07:54 +01:00
for (const VNInfo *VNI : LR.valnos)
verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
LiveInterval: Add support to track liveness of subregisters. This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
2014-12-10 02:12:10 +01:00
verifyLiveRangeSegment(LR, I, Reg, LaneMask);
Change MachineVerifier to work on LiveRange + LiveInterval llvm-svn: 192395
2013-10-10 23:28:54 +02:00
}
void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
LiveInterval: Add support to track liveness of subregisters. This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
2014-12-10 02:12:10 +01:00
unsigned Reg = LI.reg;
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-02 01:27:28 +02:00
assert(Register::isVirtualRegister(Reg));
MachineVerifier: slightly simplify code that is only called with vregs llvm-svn: 233216
2015-03-25 22:18:22 +01:00
verifyLiveRange(LI, Reg);
Extract LaneBitmask into a separate type Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-15 15:36:06 +01:00
LaneBitmask Mask;
TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC llvm-svn: 248623
2015-09-25 23:51:14 +02:00
LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
MachineVerifier: slightly simplify code that is only called with vregs llvm-svn: 233216
2015-03-25 22:18:22 +01:00
for (const LiveInterval::SubRange &SR : LI.subranges()) {
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if ((Mask & SR.LaneMask).any()) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Lane masks of sub ranges overlap in live interval", MF);
report_context(LI);
}
Implement LaneBitmask::any(), use it to replace !none(), NFCI llvm-svn: 289974
2016-12-16 20:11:56 +01:00
if ((SR.LaneMask & ~MaxMask).any()) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Subrange lanemask is invalid", MF);
report_context(LI);
}
if (SR.empty()) {
report("Subrange must not be empty", MF);
report_context(SR, LI.reg, SR.LaneMask);
}
MachineVerifier: slightly simplify code that is only called with vregs llvm-svn: 233216
2015-03-25 22:18:22 +01:00
Mask |= SR.LaneMask;
verifyLiveRange(SR, LI.reg, SR.LaneMask);
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
if (!LI.covers(SR)) {
report("A Subrange is not covered by the main range", MF);
report_context(LI);
}
LiveInterval: Add support to track liveness of subregisters. This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
2014-12-10 02:12:10 +01:00
}
Extract some methods from verifyLiveIntervals. No functional change. llvm-svn: 161149
2012-08-02 02:20:20 +02:00
// Check the LI only has one connected component.
MachineVerifier: slightly simplify code that is only called with vregs llvm-svn: 233216
2015-03-25 22:18:22 +01:00
ConnectedVNInfoEqClasses ConEQ(*LiveInts);
LiveInterval: A LiveRange is enough for ConnectedVNInfoEqClasses::Classify() llvm-svn: 257129
2016-01-08 02:16:35 +01:00
unsigned NumComp = ConEQ.Classify(LI);
MachineVerifier: slightly simplify code that is only called with vregs llvm-svn: 233216
2015-03-25 22:18:22 +01:00
if (NumComp > 1) {
MachineVerifier: Streamline live interval related error reporting Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
2015-11-10 00:59:33 +01:00
report("Multiple connected components in live interval", MF);
report_context(LI);
MachineVerifier: slightly simplify code that is only called with vregs llvm-svn: 233216
2015-03-25 22:18:22 +01:00
for (unsigned comp = 0; comp != NumComp; ++comp) {
errs() << comp << ": valnos";
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
E = LI.vni_end(); I!=E; ++I)
if (comp == ConEQ.getEqClass(*I))
errs() << ' ' << (*I)->id;
errs() << '\n';
Verify that live intervals are connected. If there are multiple connected components, each should get its own virtual register. llvm-svn: 117407
2010-10-27 00:36:07 +02:00
}
Add more verification of LiveIntervals. llvm-svn: 110454
2010-08-06 20:04:19 +02:00
}
}
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
namespace {
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
// FrameSetup and FrameDestroy can have zero adjustment, so using a single
// integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
// value is zero.
// We use a bool plus an integer to capture the stack state.
struct StackStateOfBB {
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
StackStateOfBB() = default;
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
ExitIsSetup(ExitSetup) {}
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
// Can be negative, which means we are setting up a frame.
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
int EntryValue = 0;
int ExitValue = 0;
bool EntryIsSetup = false;
bool ExitIsSetup = false;
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
};
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
} // end anonymous namespace
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
/// by a FrameDestroy <n>, stack adjustments are identical on all
/// CFG edges to a merge point, and frame is destroyed at end of a return block.
void MachineVerifier::verifyStackFrame() {
MachineInstr: Change return value of getOpcode() to unsigned. This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
2015-05-18 22:27:55 +02:00
unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
Do not run frame verification if target does not use frame instructions llvm-svn: 300807
2017-04-20 03:34:04 +02:00
if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
return;
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
SmallVector<StackStateOfBB, 8> SPState;
SPState.resize(MF->getNumBlockIDs());
Modify df_iterator to support post-order actions Summary: This makes a change to the state used to maintain visited information for depth first iterator. We know assume a method "completed(...)" which is called after all children of a node have been visited. In all existing cases, this method does nothing so this patch has no functional changes. It will however allow a client to distinguish back from cross edges in a DFS tree. Reviewers: nadav, mehdi_amini, dberlin Subscribers: MatzeB, mzolotukhin, twoh, freik, llvm-commits Differential Revision: https://reviews.llvm.org/D25191 llvm-svn: 283391
2016-10-05 23:36:16 +02:00
df_iterator_default_set<const MachineBasicBlock*> Reachable;
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
// Visit the MBBs in DFS order.
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). llvm-svn: 312971
2017-09-12 01:00:48 +02:00
for (df_ext_iterator<const MachineFunction *,
df_iterator_default_set<const MachineBasicBlock *>>
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
DFI != DFE; ++DFI) {
const MachineBasicBlock *MBB = *DFI;
StackStateOfBB BBState;
// Check the exit state of the DFS stack predecessor.
if (DFI.getPathLength() >= 2) {
const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
assert(Reachable.count(StackPred) &&
"DFS stack predecessor is already visited.\n");
BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
BBState.ExitValue = BBState.EntryValue;
BBState.ExitIsSetup = BBState.EntryIsSetup;
}
// Update stack state by checking contents of MBB.
Convert more loops to range-based equivalents llvm-svn: 207714
2014-05-01 00:17:38 +02:00
for (const auto &I : *MBB) {
if (I.getOpcode() == FrameSetupOpcode) {
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
if (BBState.ExitIsSetup)
Convert more loops to range-based equivalents llvm-svn: 207714
2014-05-01 00:17:38 +02:00
report("FrameSetup is after another FrameSetup", &I);
Add extra operand to CALLSEQ_START to keep frame part set up previously Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
2017-05-09 15:35:13 +02:00
BBState.ExitValue -= TII->getFrameTotalSize(I);
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
BBState.ExitIsSetup = true;
}
Convert more loops to range-based equivalents llvm-svn: 207714
2014-05-01 00:17:38 +02:00
if (I.getOpcode() == FrameDestroyOpcode) {
Add extra operand to CALLSEQ_START to keep frame part set up previously Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
2017-05-09 15:35:13 +02:00
int Size = TII->getFrameTotalSize(I);
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
if (!BBState.ExitIsSetup)
Convert more loops to range-based equivalents llvm-svn: 207714
2014-05-01 00:17:38 +02:00
report("FrameDestroy is not after a FrameSetup", &I);
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
BBState.ExitValue;
if (BBState.ExitIsSetup && AbsSPAdj != Size) {
Convert more loops to range-based equivalents llvm-svn: 207714
2014-05-01 00:17:38 +02:00
report("FrameDestroy <n> is after FrameSetup <m>", &I);
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
2015-02-04 01:02:59 +01:00
errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
<< AbsSPAdj << ">.\n";
}
BBState.ExitValue += Size;
BBState.ExitIsSetup = false;
}
}
SPState[MBB->getNumber()] = BBState;
// Make sure the exit state of any predecessor is consistent with the entry
// state.
for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
E = MBB->pred_end(); I != E; ++I) {
if (Reachable.count(*I) &&
(SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
report("The exit stack state of a predecessor is inconsistent.", MBB);
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 18:18:51 +01:00
errs() << "Predecessor " << printMBBReference(*(*I))
<< " has exit state (" << SPState[(*I)->getNumber()].ExitValue
<< ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
<< printMBBReference(*MBB) << " has entry state ("
<< BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
}
}
// Make sure the entry state of any successor is consistent with the exit
// state.
for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
E = MBB->succ_end(); I != E; ++I) {
if (Reachable.count(*I) &&
(SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
report("The entry stack state of a successor is inconsistent.", MBB);
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 18:18:51 +01:00
errs() << "Successor " << printMBBReference(*(*I))
<< " has entry state (" << SPState[(*I)->getNumber()].EntryValue
<< ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
<< printMBBReference(*MBB) << " has exit state ("
<< BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
Machine Verifier: verify FrameSetup and FrameDestroy 1> on every path through the CFG, a FrameSetup <n> is always followed by a FrameDestroy <n> and a FrameDestroy is always followed by a FrameSetup. 2> stack adjustments are identical on all CFG edges to a merge point. 3> frame is destroyed at end of a return block. PR16393 llvm-svn: 186350
2013-07-15 23:26:31 +02:00
}
}
// Make sure a basic block with return ends with zero stack adjustment.
if (!MBB->empty() && MBB->back().isReturn()) {
if (BBState.ExitIsSetup)
report("A return block ends with a FrameSetup.", MBB);
if (BBState.ExitValue)
report("A return block ends with a nonzero stack adjustment.", MBB);
}
}
}
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