Jim Grosbach
d0db6c9f0e
Add FIXMEs.
...
llvm-svn: 120824
2010-12-03 18:37:17 +00:00
Bill Wendling
b7df584ef7
Don't overwrite the opcode passed into the T1Special pattern.
...
llvm-svn: 120782
2010-12-03 02:02:58 +00:00
Bill Wendling
c4858cb4c3
Add Thumb encoding for some more instructions.
...
llvm-svn: 120780
2010-12-03 01:55:47 +00:00
Bill Wendling
b7635b1ed3
Formatting. It's all the rage!
...
llvm-svn: 120533
2010-12-01 02:36:55 +00:00
Bill Wendling
8861fb7484
More refactoring. This time the T1pI pattern.
...
llvm-svn: 120532
2010-12-01 02:28:08 +00:00
Bill Wendling
ccfea264ff
s/T1pIEncode/T1pILdStEncode/g
...
s/T1pIEncodeImm/T1pILdStEncodeImm/g
llvm-svn: 120524
2010-12-01 01:38:08 +00:00
Bill Wendling
517dd72f06
Renaming variables to coincide with documentation. No functionality change.
...
llvm-svn: 120522
2010-12-01 01:32:02 +00:00
Bill Wendling
8ebed2442e
Refactor T1sI and T1sIt encodings into helper classes.
...
llvm-svn: 120518
2010-12-01 01:20:15 +00:00
Bill Wendling
60d0e1a06c
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
...
statements.
llvm-svn: 120512
2010-12-01 00:48:44 +00:00
Bill Wendling
6a48b15c80
Rename operands to match ARM documentation. No functionality change.
...
llvm-svn: 120500
2010-11-30 23:54:45 +00:00
Bill Wendling
e85934f8a5
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00
Bill Wendling
ae920bcc50
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
...
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
llvm-svn: 120408
2010-11-30 07:44:32 +00:00
Bill Wendling
a3cc011fc5
Minor cleanups. No functional change.
...
llvm-svn: 120372
2010-11-30 00:50:22 +00:00
Bill Wendling
6bcbf9bd7c
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
...
able to match this yet.
llvm-svn: 120369
2010-11-30 00:34:08 +00:00
Bill Wendling
7cbe5a236c
Add some encoding for the adr instruction. Labels still need to be finished.
...
llvm-svn: 120365
2010-11-30 00:18:30 +00:00
Bill Wendling
9859e95ca2
Predicate encoding should be withing {}s. And general cleanup.
...
llvm-svn: 120361
2010-11-30 00:08:20 +00:00
Bill Wendling
6b680b11e8
Predicate encoding should be withing {}s.
...
llvm-svn: 120360
2010-11-30 00:05:25 +00:00
Evan Cheng
78baa6f30d
Mark Darwin call instructions as using "r7" to prevent the frame-register
...
assignment instructions from being moved below / above calls.
rdar://8690640
llvm-svn: 120339
2010-11-29 22:43:27 +00:00
Bill Wendling
c2693dcc02
Thumb encodings for conditional moves.
...
llvm-svn: 120334
2010-11-29 22:37:46 +00:00
Bill Wendling
15e68b7a35
Refactor some of the "disassembly-only" instructions into a base class. This
...
reduces some code duplication.
llvm-svn: 120326
2010-11-29 22:15:03 +00:00
Jim Grosbach
3e84f9d6cb
ARM Pseudo-ize tBR_JTr.
...
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
Bill Wendling
c0055893db
Add more Thumb encodings.
...
llvm-svn: 120279
2010-11-29 01:07:48 +00:00
Bill Wendling
b54752da15
More Thumb encodings.
...
llvm-svn: 120278
2010-11-29 01:00:43 +00:00
Bill Wendling
8f0b624061
Add Thumb encodings for REV instructions.
...
llvm-svn: 120277
2010-11-29 00:42:50 +00:00
Bill Wendling
d233cab1eb
Add more Thumb encodings.
...
llvm-svn: 120272
2010-11-29 00:18:15 +00:00
Bill Wendling
c5ab347eb6
More Thumb encodings.
...
llvm-svn: 119940
2010-11-21 11:49:36 +00:00
Bill Wendling
3cce558ede
- Give "trap" the correct encoding, at least according to Darwin's assembler.
...
- Add comments saying where the encodings for other instructions came from.
llvm-svn: 119936
2010-11-21 10:55:23 +00:00
Bill Wendling
834a3bfb92
A few more thumb instruction MC encodings.
...
llvm-svn: 119913
2010-11-20 22:52:33 +00:00
Bill Wendling
00481555e0
Add more Thumb add instruction encodings.
...
llvm-svn: 119883
2010-11-20 01:18:47 +00:00
Bill Wendling
4fb2131b0a
Add Thumb encodings for some add instructions.
...
llvm-svn: 119882
2010-11-20 01:00:29 +00:00
Bill Wendling
cd27d03d93
Add more encodings for Thumb instructions.
...
llvm-svn: 119881
2010-11-20 00:53:35 +00:00
Bill Wendling
c568ce5bda
Encodings for the compare instructions.
...
llvm-svn: 119868
2010-11-19 23:14:32 +00:00
Bill Wendling
65402c3a76
Add encodings for some of the thumb ADD instructions. Tests will come once the
...
asm parser can handle them.
llvm-svn: 119860
2010-11-19 22:37:33 +00:00
Bill Wendling
29f262163a
Revert accidental commit.
...
llvm-svn: 119850
2010-11-19 22:06:18 +00:00
Bill Wendling
e2f19dfde3
Change long binary encodings to use hex instead. It's more readable. Also
...
initialize missing bit.
llvm-svn: 119849
2010-11-19 22:02:18 +00:00
Bill Wendling
50a1812023
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
...
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
llvm-svn: 119774
2010-11-19 01:33:10 +00:00
Jim Grosbach
2f9a2efb3c
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
Evan Cheng
ce610bd6b3
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
...
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
Bill Wendling
b450d320ec
Encode the multi-load/store instructions with their respective modes ('ia',
...
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
Bill Wendling
49dd03e223
Comment out the defms until they're activated.
...
llvm-svn: 119000
2010-11-13 11:20:05 +00:00
Bill Wendling
fadcb3cded
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
...
llvm-svn: 118999
2010-11-13 10:57:02 +00:00
Bill Wendling
184bc1368d
Convert the modes to lower case.
...
llvm-svn: 118998
2010-11-13 10:43:34 +00:00
Bill Wendling
aa9ca6fcca
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
Jim Grosbach
c10d3f3d4b
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
Jim Grosbach
53d2661c60
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
...
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
llvm-svn: 117931
2010-11-01 17:08:58 +00:00
Chris Lattner
9da275f86b
reject instructions that contain a \n in their asmstring. Mark
...
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
2010-11-01 00:46:16 +00:00
Chris Lattner
5d088218e5
two changes: make the asmmatcher generator ignore ARM pseudos properly,
...
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
Chris Lattner
01acd65875
reapply r117858 with apparent editor malfunction fixed (somehow I
...
got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
Chris Lattner
8132a182e7
revert r117858 while I check out a failure I missed.
...
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
Chris Lattner
70b05a5b88
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
...
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
Jim Grosbach
4c7da8acbc
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
Evan Cheng
6fbb6dea7c
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
Jim Grosbach
619f1c1cc5
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
Jim Grosbach
2bf1c488de
Nuke a few more unused asm strings
...
llvm-svn: 115193
2010-09-30 19:53:58 +00:00
Jim Grosbach
52b5709c99
The asm strings are never used at all, so just nuke 'em entirely.
...
llvm-svn: 115160
2010-09-30 16:56:53 +00:00
Jim Grosbach
ad67153eb3
Go ahead and jump!
...
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
Evan Cheng
fa5d40dbff
ARM instruction itinerary fixes:
...
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
Evan Cheng
7eb08b1ad9
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
...
llvm-svn: 115010
2010-09-29 00:49:25 +00:00
Evan Cheng
7fffe3cf58
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
...
llvm-svn: 115008
2010-09-29 00:27:46 +00:00
Owen Anderson
4fc55c0e02
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
Owen Anderson
15c6948d29
Add isConditionalMove bits to X86 and ARM instructions.
...
llvm-svn: 114703
2010-09-23 22:57:01 +00:00
Jim Grosbach
bcafcce601
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
...
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
Gabor Greif
a9a9743d0d
set isCompare for another three Thumb1 instructions
...
llvm-svn: 113867
2010-09-14 22:00:50 +00:00
Gabor Greif
32fefaf320
set comparable for a bunch of Thumb instructions
...
llvm-svn: 113849
2010-09-14 20:47:43 +00:00
Evan Cheng
b79a03a3ca
For each instruction itinerary class, specify the number of micro-ops each
...
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
Jim Grosbach
b40371d3bf
grammar tweak
...
llvm-svn: 113289
2010-09-07 21:30:25 +00:00
Jim Grosbach
674b25ce31
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
...
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
llvm-svn: 112503
2010-08-30 19:49:58 +00:00
Evan Cheng
784a286b92
Delete some unused instructions.
...
llvm-svn: 110710
2010-08-10 19:36:22 +00:00
Bob Wilson
58c8a5da9e
Move newlines before inline jumptables from the asm strings in .td files to
...
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
llvm-svn: 109948
2010-07-31 06:28:10 +00:00
Jim Grosbach
bc31f7a24b
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
Jim Grosbach
f3bd81ce11
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Jim Grosbach
f4442c2ca2
Cosmetic cleanup. No functional change.
...
llvm-svn: 104974
2010-05-28 17:51:20 +00:00
Jim Grosbach
2eb2c2d257
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
...
llvm-svn: 104967
2010-05-28 17:37:40 +00:00
Jim Grosbach
b004e2cf0f
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
Jim Grosbach
95c228acb0
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
llvm-svn: 104661
2010-05-26 01:22:21 +00:00
Jim Grosbach
b6cc69c655
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
...
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
Evan Cheng
6f52107b12
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
Evan Cheng
0aa58d5b69
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
Evan Cheng
23fb523b44
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
...
llvm-svn: 104102
2010-05-19 01:52:25 +00:00
Bob Wilson
a748ca62cc
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
...
Obvious in retrospect but not fun to debug.
llvm-svn: 103969
2010-05-17 20:31:13 +00:00
Anton Korobeynikov
a63555c10d
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
Anton Korobeynikov
4f8b48d8c6
"trap" pseudo-op turned out to be apple-local.
...
Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
Evan Cheng
11130a0a22
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
...
llvm-svn: 103459
2010-05-11 07:26:32 +00:00
Chris Lattner
896b393fab
set SDNPVariadic on nodes throughout the rest of the targets that
...
need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
Bob Wilson
279818d473
Remove the writeback flag from ARM's address mode 4. Now that we have separate
...
instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
Bob Wilson
0e8a3d7a13
Change ARM ld/st multiple instructions to have variant instructions for
...
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
Johnny Chen
db62f78f10
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
...
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
llvm-svn: 98172
2010-03-10 18:59:38 +00:00
Johnny Chen
c903faa636
Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
...
MULS <Rdm>, <Rn>, <Rdm>
according to A8.6.105 MUL Encoding T1.
llvm-svn: 97675
2010-03-03 23:15:43 +00:00
Johnny Chen
88f05c26a5
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
...
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
llvm-svn: 97573
2010-03-02 18:14:57 +00:00
Dan Gohman
99c6bcbc13
The mayHaveSideEffects flag is no longer used.
...
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
Johnny Chen
30a910f458
Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
...
WFI, SEV, SETEND.
llvm-svn: 97149
2010-02-25 17:51:03 +00:00
Johnny Chen
bbe3592817
Added tNOP for disassembly only.
...
llvm-svn: 97105
2010-02-25 03:28:51 +00:00
Johnny Chen
13b9bd479f
Added tSVC and tTRAP for disassembly only.
...
llvm-svn: 97098
2010-02-25 02:21:11 +00:00
Jim Grosbach
c4ab116a90
Updated version of r96634 (which was reverted due to failing 176.gcc and
...
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
llvm-svn: 96822
2010-02-22 23:10:38 +00:00
Jim Grosbach
2acf602672
80 column cleanup
...
llvm-svn: 96393
2010-02-16 21:23:02 +00:00
Jim Grosbach
0c678d7b17
Remove trailing whitespace
...
llvm-svn: 96388
2010-02-16 21:07:46 +00:00
Johnny Chen
c6ca0de853
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
...
llvm-svn: 95884
2010-02-11 18:12:29 +00:00
Jim Grosbach
bdc0ff13db
Radar 7417921
...
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
llvm-svn: 95686
2010-02-09 19:51:37 +00:00
Jim Grosbach
a7e098af3b
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
Jim Grosbach
e96f9c1cab
Adjust setjmp instruction sequence to not need 32-bit alignment padding
...
llvm-svn: 94627
2010-01-27 00:07:20 +00:00
Jim Grosbach
231a0d01a9
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
...
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
llvm-svn: 94119
2010-01-22 00:08:13 +00:00
Johnny Chen
a5f79a6b93
The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in
...
the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch). Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.
llvm-svn: 93759
2010-01-18 20:15:56 +00:00
Johnny Chen
a5f2e84b0c
Added 16-bit Thumb Load/Store immediate instructions with encoding bits so that
...
the disassembler can properly decode Load/Store register/immediate instructions.
llvm-svn: 93471
2010-01-14 22:42:17 +00:00
Johnny Chen
08c211683b
Fixed a couple of places for Thumb MOV where encoding bits are underspecified.
...
llvm-svn: 93349
2010-01-13 21:00:26 +00:00
Jakob Stoklund Olesen
2d819b93a2
Remove the JustSP single-register regclass.
...
It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.
llvm-svn: 93280
2010-01-13 00:43:06 +00:00
Jakob Stoklund Olesen
9d1c8ecf05
Add a SPR register class to the ARM target.
...
Certain Thumb instructions require only SP (e.g. tSTRspi).
llvm-svn: 91944
2009-12-22 23:54:44 +00:00
Johnny Chen
04b3259f9d
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
...
llvm-svn: 91571
2009-12-16 23:36:52 +00:00
Johnny Chen
7339b74117
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
...
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
Johnny Chen
8ef481b5d7
Added encoding bits for the Thumb ISA. Initial checkin.
...
llvm-svn: 91434
2009-12-15 17:24:14 +00:00
Jim Grosbach
5541b5f793
Thumb1 exception handling setjmp
...
llvm-svn: 90246
2009-12-01 18:10:36 +00:00
Evan Cheng
9f57c4916e
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
Evan Cheng
987b8c3d9a
More consistent thumb1 asm printing.
...
llvm-svn: 89328
2009-11-19 06:57:41 +00:00
Evan Cheng
6e3e66375a
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
Evan Cheng
22121f4c69
The .n suffix must go after the predicate.
...
llvm-svn: 86019
2009-11-04 07:38:48 +00:00
Evan Cheng
1a06b12330
Use ldr.n to workaround a darwin assembler bug.
...
llvm-svn: 85980
2009-11-04 00:00:39 +00:00
Bob Wilson
97331f70ca
For Thumb indirect branches, use "mov pc, reg" which does not switch
...
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
llvm-svn: 85874
2009-11-03 06:29:56 +00:00
Bob Wilson
3144715b53
Put BlockAddresses into ARM constant pools.
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llvm-svn: 85824
2009-11-02 20:59:23 +00:00
Evan Cheng
de16fff3e8
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
Bob Wilson
95064e348a
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
Dan Gohman
3393a4c997
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
Bob Wilson
af37728221
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
...
opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
Evan Cheng
f30e5556ba
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
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llvm-svn: 85184
2009-10-27 00:08:59 +00:00
Evan Cheng
241092d89f
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
Evan Cheng
4dd7d7156e
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
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llvm-svn: 83191
2009-10-01 01:33:39 +00:00
Jim Grosbach
2d057f09e8
Add "isBarrier = 1" to return instructions.
...
Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
Evan Cheng
6c89bc0472
Remove comments which don't add much to .s readibility.
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llvm-svn: 81306
2009-09-09 01:38:23 +00:00
David Goodwin
0dd9e9edb4
Calls clobber FPSCR.
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llvm-svn: 80956
2009-09-03 22:12:28 +00:00
Evan Cheng
493eee1fc7
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
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llvm-svn: 80615
2009-08-31 20:14:07 +00:00
Evan Cheng
d53546a6cd
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
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llvm-svn: 80350
2009-08-28 06:59:37 +00:00
Evan Cheng
2d5d3700e9
v4, v5 does not support sxtb / sxth.
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llvm-svn: 80322
2009-08-28 00:31:43 +00:00
Bob Wilson
9482015a0a
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
Evan Cheng
86546fb692
Fix an obvious copy-n-paste bug.
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llvm-svn: 79535
2009-08-20 17:01:04 +00:00
David Goodwin
d57f44783c
Update Cortex-A8 instruction itineraries for integer instructions.
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llvm-svn: 79436
2009-08-19 18:00:44 +00:00
Evan Cheng
d4d2a3d0a6
Fix revsh pattern.
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llvm-svn: 79318
2009-08-18 05:43:23 +00:00
Evan Cheng
7d8caa143b
Also shrink immediate branches; also more assembler workarounds.
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llvm-svn: 79014
2009-08-14 18:31:44 +00:00
Evan Cheng
45d6a21e21
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
David Goodwin
dd797db6bd
Finalize itineraries for cortex-a8 integer multiply
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llvm-svn: 78908
2009-08-13 15:51:13 +00:00
David Goodwin
90e7f9873c
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
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llvm-svn: 78827
2009-08-12 18:31:53 +00:00
Evan Cheng
c369ccbe83
Shrink Thumb2 movcc instructions.
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llvm-svn: 78790
2009-08-12 05:17:19 +00:00
Evan Cheng
410447e028
80 col violation.
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llvm-svn: 78778
2009-08-12 02:03:03 +00:00
Evan Cheng
a29ee9f509
Shrinkify Thumb2 r = add sp, imm.
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llvm-svn: 78745
2009-08-11 23:00:31 +00:00
Evan Cheng
783028063e
Shrinkify Thumb2 load / store multiple instructions.
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llvm-svn: 78717
2009-08-11 21:11:32 +00:00
Owen Anderson
48f2f0ae72
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
Owen Anderson
b4bce99769
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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llvm-svn: 78610
2009-08-10 22:56:29 +00:00
Evan Cheng
ad380aa97a
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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llvm-svn: 78550
2009-08-10 02:37:24 +00:00
Anton Korobeynikov
44fa9f179c
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
Evan Cheng
fb833354b6
tADDhirr should target GPR, not tGPR.
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llvm-svn: 78454
2009-08-08 03:19:44 +00:00
Evan Cheng
5af3c8154b
tBfar is bl, which clobbers LR.
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llvm-svn: 78370
2009-08-07 05:45:07 +00:00
Evan Cheng
48b49cf5b9
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
David Goodwin
3aafcc1dd2
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
Evan Cheng
e366789b50
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
Evan Cheng
5ef6928dff
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
...
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
Evan Cheng
90a1ca6e17
Make sure Thumb2 uses the right call instructions.
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llvm-svn: 77507
2009-07-29 21:26:42 +00:00
Evan Cheng
c8d3891c87
- Fix an obvious copy and paste error.
...
- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
Evan Cheng
cf483eb0c0
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
...
llvm-svn: 77364
2009-07-28 20:53:24 +00:00
David Goodwin
6ff3fd8021
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
...
llvm-svn: 77242
2009-07-27 19:59:26 +00:00
Evan Cheng
a6737e21cf
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
...
llvm-svn: 77172
2009-07-26 23:59:01 +00:00
Evan Cheng
8997f6bfc1
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
...
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
llvm-svn: 76889
2009-07-23 18:26:03 +00:00
Evan Cheng
4a77f28c47
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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llvm-svn: 76803
2009-07-22 22:03:29 +00:00
Evan Cheng
34576850e1
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
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llvm-svn: 76729
2009-07-22 06:46:53 +00:00
Evan Cheng
4fdb43a89d
Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.
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llvm-svn: 76728
2009-07-22 06:37:28 +00:00
Evan Cheng
192fc19379
Do not select tSXTB / tSXTH in thumb2 mode.
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llvm-svn: 76600
2009-07-21 18:15:26 +00:00
Evan Cheng
490d2cc5a4
Fix tSUBspi operand definition. It reads and writes sp, which is a high register.
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llvm-svn: 76155
2009-07-17 05:43:12 +00:00
Evan Cheng
b8666f7abc
1. In Thumb mode, select tBx instead of ARM variants.
...
2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
llvm-svn: 75585
2009-07-14 01:49:27 +00:00
Evan Cheng
03d981d91b
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
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llvm-svn: 75360
2009-07-11 07:08:13 +00:00
Evan Cheng
268b47b1fb
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
...
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
Evan Cheng
74f5327e53
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
...
llvm-svn: 75219
2009-07-10 02:09:04 +00:00
Evan Cheng
24f2aefc87
Add a thumb2 pass to insert IT blocks.
...
llvm-svn: 75218
2009-07-10 01:54:42 +00:00
Evan Cheng
1b15e9611e
Added Thumb IT instruction.
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llvm-svn: 75198
2009-07-09 23:43:36 +00:00
David Goodwin
49fbd8d6b7
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
David Goodwin
5bdef4b3f7
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
David Goodwin
5545d82866
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
Evan Cheng
2a527c3419
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
David Goodwin
9e1280adf3
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
...
llvm-svn: 74423
2009-06-29 15:33:01 +00:00
Evan Cheng
093adf3ff9
Implement Thumb2 ldr.
...
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
Evan Cheng
817712377a
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
Evan Cheng
e45355b804
tst is also commutable.
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llvm-svn: 74236
2009-06-26 00:19:07 +00:00
David Goodwin
a0ed5f6847
Add Def/Use of CPSR for Thumb-1 instructions.
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llvm-svn: 74219
2009-06-25 22:49:55 +00:00
David Goodwin
c72bad36d7
Test commit
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llvm-svn: 74185
2009-06-25 17:52:32 +00:00
Evan Cheng
8e61610960
Some reorg and additional comments.
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llvm-svn: 74152
2009-06-25 01:05:06 +00:00
Evan Cheng
e8c58ee743
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
Evan Cheng
1333ee8eb6
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
...
llvm-svn: 73985
2009-06-23 19:38:13 +00:00
Bob Wilson
48de87abcb
Add explicit types for shift count constants. This is in preparation for
...
another change that makes the types ambiguous (at least as far as tablegen
is concerned).
llvm-svn: 73909
2009-06-22 22:08:29 +00:00
Eli Friedman
003abaa60d
Mark a few Thumb instructions commutable; just happened to spot this
...
while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
llvm-svn: 73746
2009-06-19 01:43:08 +00:00
Evan Cheng
2f784781aa
Mark some pattern-less instructions as neverHasSideEffects.
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llvm-svn: 73252
2009-06-12 20:46:18 +00:00
Jim Grosbach
4861b683a8
correct register class for tADDspi to GPR since the register will always be SP
...
llvm-svn: 71602
2009-05-12 22:30:18 +00:00
Jim Grosbach
e2b20a3526
PR2985 / <rdar://problem/6584986>
...
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
llvm-svn: 68545
2009-04-07 20:34:09 +00:00
Jim Grosbach
93b0fc3ba8
remove trailing whitespace
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llvm-svn: 67874
2009-03-27 23:06:27 +00:00
Dan Gohman
5dad0993a9
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
...
llvm-svn: 60487
2008-12-03 18:15:48 +00:00
Dan Gohman
89660301e3
Rename ConstantSDNode::getValue to getZExtValue, for consistency
...
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Evan Cheng
f90bc9a050
More refactoring.
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llvm-svn: 55528
2008-08-29 06:41:12 +00:00
Chris Lattner
41717f6989
This commit changes:
...
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner
9b4f2b2316
get def use info more correct.
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llvm-svn: 45821
2008-01-10 05:12:37 +00:00
Evan Cheng
9de4f35e9f
Only mark instructions that load a single value without extension as isSimpleLoad = 1.
...
llvm-svn: 45727
2008-01-07 23:56:57 +00:00
Chris Lattner
14310afe42
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
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llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner
5489888580
rename isStore -> mayStore to more accurately reflect what it captures.
...
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
Chris Lattner
2bb919b542
remove explicit isStore flags that are now inferrable.
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llvm-svn: 45653
2008-01-06 05:55:01 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Bill Wendling
cc75435ebf
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
...
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
Evan Cheng
b43255bc68
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
...
llvm-svn: 41863
2007-09-11 19:55:27 +00:00