Eric Christopher
0e12efbed1
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
...
followed by a conditional and imm8.
llvm-svn: 132179
2011-05-27 03:50:53 +00:00
Cameron Zwarich
9c871755b6
Mark tBX as an indirect branch rather than a return.
...
llvm-svn: 132107
2011-05-26 03:41:12 +00:00
Cameron Zwarich
9c19995747
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
...
llvm-svn: 132086
2011-05-25 21:53:50 +00:00
Cameron Zwarich
4f47b296d8
Move some code to a more logical place.
...
llvm-svn: 132043
2011-05-25 04:45:29 +00:00
Cameron Zwarich
5a32e53e3f
Change the order of tBX's operands so that the predicate operands come after the
...
target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007 >
llvm-svn: 132041
2011-05-25 04:45:23 +00:00
Cameron Zwarich
08753a605b
Rename tBX_Rm to tBX.
...
llvm-svn: 132040
2011-05-25 04:45:20 +00:00
Cameron Zwarich
d9707488bb
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
...
reflect their actual meaning and match the ARM instructions.
llvm-svn: 132039
2011-05-25 04:45:14 +00:00
Owen Anderson
50766bc2f2
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
...
llvm-svn: 131189
2011-05-11 17:00:48 +00:00
Jakob Stoklund Olesen
da28d31f03
Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers.
...
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.
LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.
llvm-svn: 130801
2011-05-03 22:31:24 +00:00
Bruno Cardoso Lopes
c818d784a2
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
...
it's possible.
llvm-svn: 130764
2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes
9dd575e4a9
Add a few ARM coprocessor intrinsics. Testcases included
...
llvm-svn: 130763
2011-05-03 17:29:22 +00:00
Eric Christopher
bea4df9acc
Let the immediate leaf pattern take transforms and switch the signed
...
immediate patterns in arm to using the pattern.
Handles rdar://9299434
llvm-svn: 130386
2011-04-28 05:49:04 +00:00
Johnny Chen
dfac31bc1b
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
...
print out ldr, not ldr.n.
rdar://problem/9267772
llvm-svn: 130008
2011-04-22 19:12:43 +00:00
Chris Lattner
0304b82f80
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Evan Cheng
d01345fcc4
Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
...
llvm-svn: 129548
2011-04-14 23:27:44 +00:00
Johnny Chen
443a6902bf
Thumb disassembler was erroneously rejecting "blx sp" instruction.
...
rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
Bruno Cardoso Lopes
c8d8dc9869
Change MRC and MRC2 instructions to model the output register properly
...
llvm-svn: 128085
2011-03-22 15:06:24 +00:00
Bruno Cardoso Lopes
e65a98b127
Fix encoding and add parsing support for the arm/thumb CPS instruction:
...
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
Bruno Cardoso Lopes
5f06c0aa3b
Add cdp/cdp2 instructions for thumb/thumb2
...
llvm-svn: 123929
2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
f377d1721e
Add mcr* and mr*c support to thumb targets
...
llvm-svn: 123917
2011-01-20 16:35:57 +00:00
Chris Lattner
01e8c46349
Flag -> Glue, the ongoing saga
...
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Bill Wendling
856080c8a1
Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
...
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
llvm-svn: 122303
2010-12-21 01:57:15 +00:00
Jim Grosbach
ce773319e4
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
...
llvm-svn: 121990
2010-12-16 19:11:16 +00:00
Bill Wendling
448cd7f1bb
Add encodings for Thumb1 Spill and Restore pseudos.
...
llvm-svn: 121929
2010-12-16 00:38:41 +00:00
Jim Grosbach
84c2b29b58
Thumb1 had two patterns for the same load-from-constant-pool instruction.
...
Canonicalize on tLDRpci and remove tLDRcp.
llvm-svn: 121920
2010-12-15 23:52:36 +00:00
Bill Wendling
ed6c88ead9
Whitespace cleanups.
...
llvm-svn: 121914
2010-12-15 23:31:24 +00:00
Bill Wendling
2764f25c78
Add some missing patterns now that tLDRB and tLDRH are split into reg and
...
immediate versions.
llvm-svn: 121819
2010-12-15 00:58:57 +00:00
Bill Wendling
ab3d22ba7f
Comments and cleaning.
...
llvm-svn: 121809
2010-12-14 23:42:48 +00:00
Jim Grosbach
1e943cc60d
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
...
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
Bill Wendling
7e589d4753
Multiclassify the LDR/STR encoding patterns. The only functionality difference
...
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
llvm-svn: 121794
2010-12-14 22:10:49 +00:00
Bill Wendling
4fe39bae17
Use the integer scheduling intrinsic for integer loads and stores.
...
llvm-svn: 121765
2010-12-14 12:33:05 +00:00
Bill Wendling
61720b79f9
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
Owen Anderson
aaf97da84b
Fix encoding of Thumb1 LDRB and STRB.
...
llvm-svn: 121581
2010-12-10 22:11:13 +00:00
Jim Grosbach
a378c43eae
Thumb unconditional branch binary encoding. rdar://8754994
...
llvm-svn: 121496
2010-12-10 18:21:33 +00:00
Jim Grosbach
905301a7d8
Thumb conditional branch binary encodings. rdar://8745367
...
llvm-svn: 121493
2010-12-10 17:13:40 +00:00
Bill Wendling
f8eaf8a243
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
...
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
2010-12-09 21:49:07 +00:00
Jim Grosbach
9b3730fc77
Rename the encoder method for t_cbtarget to match.
...
llvm-svn: 121399
2010-12-09 19:04:53 +00:00
Jim Grosbach
57d420438a
Thumb needs a few different encoding schemes for branch targets. Rename
...
t_brtarget to be more specific.
llvm-svn: 121398
2010-12-09 19:01:46 +00:00
Bill Wendling
cd8fdfd65f
The BLX instruction is encoded differently than the BL, because why not? In
...
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
Bill Wendling
9756f7c7b0
Support the "target" encodings for the CB[N]Z instructions.
...
llvm-svn: 121308
2010-12-08 23:01:43 +00:00
Bill Wendling
dac1f24d98
Add support for loading from a constant pool.
...
llvm-svn: 121226
2010-12-08 01:57:09 +00:00
Jim Grosbach
77b631549c
Binary encoding for ARM tLDRspi and tSTRspi.
...
llvm-svn: 121186
2010-12-07 21:50:47 +00:00
Jim Grosbach
1aa6a676cf
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
...
possible. They were duplicates for everything exception the source pattern
before.
llvm-svn: 121179
2010-12-07 20:41:06 +00:00
Jim Grosbach
c99517ecc6
Encode the literal field for tCMPzi instruction.
...
llvm-svn: 121153
2010-12-07 17:48:24 +00:00
Jim Grosbach
2d361b9318
Add fixup for Thumb1 BL/BLX instructions.
...
llvm-svn: 121072
2010-12-06 23:57:07 +00:00
Jim Grosbach
4c10ffa7c3
Encode condition code for Thumb1 conditional branch instruction.
...
llvm-svn: 120865
2010-12-04 00:20:40 +00:00
Bill Wendling
7e27f17312
Use correct variable names to match the patterns.
...
llvm-svn: 120857
2010-12-03 23:44:24 +00:00
Jim Grosbach
3b5c857f01
Match pattern operand names to expected encoding field names. This corrects the
...
operand encoding ordering of the instruction.
llvm-svn: 120852
2010-12-03 23:21:25 +00:00
Jim Grosbach
dbefb3e7e5
Remove incorrect BL target encoding (it's similar to, but not the same as the
...
ARM instruction). Add encoding of bits 13 and 11.
llvm-svn: 120849
2010-12-03 22:33:42 +00:00
Jim Grosbach
25da270139
No need to declare EncoderMethod property anymore; just assign to it.
...
llvm-svn: 120831
2010-12-03 19:31:00 +00:00
Jim Grosbach
d0db6c9f0e
Add FIXMEs.
...
llvm-svn: 120824
2010-12-03 18:37:17 +00:00
Bill Wendling
b7df584ef7
Don't overwrite the opcode passed into the T1Special pattern.
...
llvm-svn: 120782
2010-12-03 02:02:58 +00:00
Bill Wendling
c4858cb4c3
Add Thumb encoding for some more instructions.
...
llvm-svn: 120780
2010-12-03 01:55:47 +00:00
Bill Wendling
b7635b1ed3
Formatting. It's all the rage!
...
llvm-svn: 120533
2010-12-01 02:36:55 +00:00
Bill Wendling
8861fb7484
More refactoring. This time the T1pI pattern.
...
llvm-svn: 120532
2010-12-01 02:28:08 +00:00
Bill Wendling
ccfea264ff
s/T1pIEncode/T1pILdStEncode/g
...
s/T1pIEncodeImm/T1pILdStEncodeImm/g
llvm-svn: 120524
2010-12-01 01:38:08 +00:00
Bill Wendling
517dd72f06
Renaming variables to coincide with documentation. No functionality change.
...
llvm-svn: 120522
2010-12-01 01:32:02 +00:00
Bill Wendling
8ebed2442e
Refactor T1sI and T1sIt encodings into helper classes.
...
llvm-svn: 120518
2010-12-01 01:20:15 +00:00
Bill Wendling
60d0e1a06c
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
...
statements.
llvm-svn: 120512
2010-12-01 00:48:44 +00:00
Bill Wendling
6a48b15c80
Rename operands to match ARM documentation. No functionality change.
...
llvm-svn: 120500
2010-11-30 23:54:45 +00:00
Bill Wendling
e85934f8a5
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00
Bill Wendling
ae920bcc50
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
...
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
llvm-svn: 120408
2010-11-30 07:44:32 +00:00
Bill Wendling
a3cc011fc5
Minor cleanups. No functional change.
...
llvm-svn: 120372
2010-11-30 00:50:22 +00:00
Bill Wendling
6bcbf9bd7c
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
...
able to match this yet.
llvm-svn: 120369
2010-11-30 00:34:08 +00:00
Bill Wendling
7cbe5a236c
Add some encoding for the adr instruction. Labels still need to be finished.
...
llvm-svn: 120365
2010-11-30 00:18:30 +00:00
Bill Wendling
9859e95ca2
Predicate encoding should be withing {}s. And general cleanup.
...
llvm-svn: 120361
2010-11-30 00:08:20 +00:00
Bill Wendling
6b680b11e8
Predicate encoding should be withing {}s.
...
llvm-svn: 120360
2010-11-30 00:05:25 +00:00
Evan Cheng
78baa6f30d
Mark Darwin call instructions as using "r7" to prevent the frame-register
...
assignment instructions from being moved below / above calls.
rdar://8690640
llvm-svn: 120339
2010-11-29 22:43:27 +00:00
Bill Wendling
c2693dcc02
Thumb encodings for conditional moves.
...
llvm-svn: 120334
2010-11-29 22:37:46 +00:00
Bill Wendling
15e68b7a35
Refactor some of the "disassembly-only" instructions into a base class. This
...
reduces some code duplication.
llvm-svn: 120326
2010-11-29 22:15:03 +00:00
Jim Grosbach
3e84f9d6cb
ARM Pseudo-ize tBR_JTr.
...
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
Bill Wendling
c0055893db
Add more Thumb encodings.
...
llvm-svn: 120279
2010-11-29 01:07:48 +00:00
Bill Wendling
b54752da15
More Thumb encodings.
...
llvm-svn: 120278
2010-11-29 01:00:43 +00:00
Bill Wendling
8f0b624061
Add Thumb encodings for REV instructions.
...
llvm-svn: 120277
2010-11-29 00:42:50 +00:00
Bill Wendling
d233cab1eb
Add more Thumb encodings.
...
llvm-svn: 120272
2010-11-29 00:18:15 +00:00
Bill Wendling
c5ab347eb6
More Thumb encodings.
...
llvm-svn: 119940
2010-11-21 11:49:36 +00:00
Bill Wendling
3cce558ede
- Give "trap" the correct encoding, at least according to Darwin's assembler.
...
- Add comments saying where the encodings for other instructions came from.
llvm-svn: 119936
2010-11-21 10:55:23 +00:00
Bill Wendling
834a3bfb92
A few more thumb instruction MC encodings.
...
llvm-svn: 119913
2010-11-20 22:52:33 +00:00
Bill Wendling
00481555e0
Add more Thumb add instruction encodings.
...
llvm-svn: 119883
2010-11-20 01:18:47 +00:00
Bill Wendling
4fb2131b0a
Add Thumb encodings for some add instructions.
...
llvm-svn: 119882
2010-11-20 01:00:29 +00:00
Bill Wendling
cd27d03d93
Add more encodings for Thumb instructions.
...
llvm-svn: 119881
2010-11-20 00:53:35 +00:00
Bill Wendling
c568ce5bda
Encodings for the compare instructions.
...
llvm-svn: 119868
2010-11-19 23:14:32 +00:00
Bill Wendling
65402c3a76
Add encodings for some of the thumb ADD instructions. Tests will come once the
...
asm parser can handle them.
llvm-svn: 119860
2010-11-19 22:37:33 +00:00
Bill Wendling
29f262163a
Revert accidental commit.
...
llvm-svn: 119850
2010-11-19 22:06:18 +00:00
Bill Wendling
e2f19dfde3
Change long binary encodings to use hex instead. It's more readable. Also
...
initialize missing bit.
llvm-svn: 119849
2010-11-19 22:02:18 +00:00
Bill Wendling
50a1812023
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
...
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
llvm-svn: 119774
2010-11-19 01:33:10 +00:00
Jim Grosbach
2f9a2efb3c
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
Evan Cheng
ce610bd6b3
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
...
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
Bill Wendling
b450d320ec
Encode the multi-load/store instructions with their respective modes ('ia',
...
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
Bill Wendling
49dd03e223
Comment out the defms until they're activated.
...
llvm-svn: 119000
2010-11-13 11:20:05 +00:00
Bill Wendling
fadcb3cded
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
...
llvm-svn: 118999
2010-11-13 10:57:02 +00:00
Bill Wendling
184bc1368d
Convert the modes to lower case.
...
llvm-svn: 118998
2010-11-13 10:43:34 +00:00
Bill Wendling
aa9ca6fcca
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
Jim Grosbach
c10d3f3d4b
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
Jim Grosbach
53d2661c60
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
...
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
llvm-svn: 117931
2010-11-01 17:08:58 +00:00
Chris Lattner
9da275f86b
reject instructions that contain a \n in their asmstring. Mark
...
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
2010-11-01 00:46:16 +00:00
Chris Lattner
5d088218e5
two changes: make the asmmatcher generator ignore ARM pseudos properly,
...
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
Chris Lattner
01acd65875
reapply r117858 with apparent editor malfunction fixed (somehow I
...
got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
Chris Lattner
8132a182e7
revert r117858 while I check out a failure I missed.
...
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
Chris Lattner
70b05a5b88
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
...
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
Jim Grosbach
4c7da8acbc
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
Evan Cheng
6fbb6dea7c
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
Jim Grosbach
619f1c1cc5
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
Jim Grosbach
2bf1c488de
Nuke a few more unused asm strings
...
llvm-svn: 115193
2010-09-30 19:53:58 +00:00
Jim Grosbach
52b5709c99
The asm strings are never used at all, so just nuke 'em entirely.
...
llvm-svn: 115160
2010-09-30 16:56:53 +00:00
Jim Grosbach
ad67153eb3
Go ahead and jump!
...
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
Evan Cheng
fa5d40dbff
ARM instruction itinerary fixes:
...
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
Evan Cheng
7eb08b1ad9
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
...
llvm-svn: 115010
2010-09-29 00:49:25 +00:00
Evan Cheng
7fffe3cf58
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
...
llvm-svn: 115008
2010-09-29 00:27:46 +00:00
Owen Anderson
4fc55c0e02
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
Owen Anderson
15c6948d29
Add isConditionalMove bits to X86 and ARM instructions.
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llvm-svn: 114703
2010-09-23 22:57:01 +00:00
Jim Grosbach
bcafcce601
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
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(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
Gabor Greif
a9a9743d0d
set isCompare for another three Thumb1 instructions
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llvm-svn: 113867
2010-09-14 22:00:50 +00:00
Gabor Greif
32fefaf320
set comparable for a bunch of Thumb instructions
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llvm-svn: 113849
2010-09-14 20:47:43 +00:00
Evan Cheng
b79a03a3ca
For each instruction itinerary class, specify the number of micro-ops each
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instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
Jim Grosbach
b40371d3bf
grammar tweak
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llvm-svn: 113289
2010-09-07 21:30:25 +00:00
Jim Grosbach
674b25ce31
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
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help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
llvm-svn: 112503
2010-08-30 19:49:58 +00:00
Evan Cheng
784a286b92
Delete some unused instructions.
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llvm-svn: 110710
2010-08-10 19:36:22 +00:00
Bob Wilson
58c8a5da9e
Move newlines before inline jumptables from the asm strings in .td files to
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the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
llvm-svn: 109948
2010-07-31 06:28:10 +00:00
Jim Grosbach
bc31f7a24b
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
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being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
Jim Grosbach
f3bd81ce11
Clean up 80 column violations. No functional change.
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llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Jim Grosbach
f4442c2ca2
Cosmetic cleanup. No functional change.
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llvm-svn: 104974
2010-05-28 17:51:20 +00:00
Jim Grosbach
2eb2c2d257
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
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llvm-svn: 104967
2010-05-28 17:37:40 +00:00
Jim Grosbach
b004e2cf0f
Update the saved stack pointer in the sjlj function context following either
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an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
Jim Grosbach
95c228acb0
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
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llvm-svn: 104661
2010-05-26 01:22:21 +00:00
Jim Grosbach
b6cc69c655
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
Evan Cheng
6f52107b12
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
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llvm-svn: 104115
2010-05-19 07:28:01 +00:00
Evan Cheng
0aa58d5b69
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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llvm-svn: 104111
2010-05-19 06:07:03 +00:00
Evan Cheng
23fb523b44
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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llvm-svn: 104102
2010-05-19 01:52:25 +00:00
Bob Wilson
a748ca62cc
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
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Obvious in retrospect but not fun to debug.
llvm-svn: 103969
2010-05-17 20:31:13 +00:00
Anton Korobeynikov
a63555c10d
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
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llvm-svn: 103903
2010-05-16 09:15:36 +00:00
Anton Korobeynikov
4f8b48d8c6
"trap" pseudo-op turned out to be apple-local.
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Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
Evan Cheng
11130a0a22
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
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llvm-svn: 103459
2010-05-11 07:26:32 +00:00
Chris Lattner
896b393fab
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
Bob Wilson
279818d473
Remove the writeback flag from ARM's address mode 4. Now that we have separate
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instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
Bob Wilson
0e8a3d7a13
Change ARM ld/st multiple instructions to have variant instructions for
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writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
Johnny Chen
db62f78f10
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
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operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
llvm-svn: 98172
2010-03-10 18:59:38 +00:00
Johnny Chen
c903faa636
Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
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MULS <Rdm>, <Rn>, <Rdm>
according to A8.6.105 MUL Encoding T1.
llvm-svn: 97675
2010-03-03 23:15:43 +00:00
Johnny Chen
88f05c26a5
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
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SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
llvm-svn: 97573
2010-03-02 18:14:57 +00:00
Dan Gohman
99c6bcbc13
The mayHaveSideEffects flag is no longer used.
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llvm-svn: 97348
2010-02-27 23:47:46 +00:00
Johnny Chen
30a910f458
Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
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WFI, SEV, SETEND.
llvm-svn: 97149
2010-02-25 17:51:03 +00:00
Johnny Chen
bbe3592817
Added tNOP for disassembly only.
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llvm-svn: 97105
2010-02-25 03:28:51 +00:00
Johnny Chen
13b9bd479f
Added tSVC and tTRAP for disassembly only.
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llvm-svn: 97098
2010-02-25 02:21:11 +00:00
Jim Grosbach
c4ab116a90
Updated version of r96634 (which was reverted due to failing 176.gcc and
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126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
llvm-svn: 96822
2010-02-22 23:10:38 +00:00
Jim Grosbach
2acf602672
80 column cleanup
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llvm-svn: 96393
2010-02-16 21:23:02 +00:00
Jim Grosbach
0c678d7b17
Remove trailing whitespace
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llvm-svn: 96388
2010-02-16 21:07:46 +00:00
Johnny Chen
c6ca0de853
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
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llvm-svn: 95884
2010-02-11 18:12:29 +00:00
Jim Grosbach
bdc0ff13db
Radar 7417921
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tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
llvm-svn: 95686
2010-02-09 19:51:37 +00:00
Jim Grosbach
a7e098af3b
tighten up eh.setjmp sequence a bit.
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llvm-svn: 95603
2010-02-08 23:22:00 +00:00
Jim Grosbach
e96f9c1cab
Adjust setjmp instruction sequence to not need 32-bit alignment padding
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llvm-svn: 94627
2010-01-27 00:07:20 +00:00