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444 Commits

Author SHA1 Message Date
Chad Rosier
d1968c9ed6 [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

llvm-svn: 145742
 2011-12-03 02:21:57 +00:00
Nick Lewycky
7d0d3c2d58 Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Chad Rosier
b3b2871bbf [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
 2011-12-02 20:25:18 +00:00
Duncan Sands
ec13954efd Silence wrong warnings from GCC about variables possibly being used 
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.

llvm-svn: 145239
 2011-11-28 10:31:27 +00:00
Chad Rosier
70dab03f8e Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. 
llvm-svn: 144959
 2011-11-18 01:17:34 +00:00
Chad Rosier
7d2af13ccb Add TODO comment. 
llvm-svn: 144920
 2011-11-17 21:46:13 +00:00
Chad Rosier
47928b03f3 Dead code. 
llvm-svn: 144888
 2011-11-17 07:24:49 +00:00
Chad Rosier
c9ed1d9072 Don't unconditionally set the kill flag. 
rdar://10456186

llvm-svn: 144872
 2011-11-17 01:16:53 +00:00
Chad Rosier
69f9c432a6 Check to make sure we can select the instruction before trying to put the 
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
 2011-11-16 18:39:44 +00:00
Chad Rosier
17577c9394 Add FIXME comment. 
llvm-svn: 144743
 2011-11-16 00:32:20 +00:00
Jay Foad
7d05fea7f8 Remove some unnecessary includes of PseudoSourceValue.h. 
llvm-svn: 144631
 2011-11-15 07:24:32 +00:00
Chad Rosier
4e05d7f12c Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

llvm-svn: 144585
 2011-11-14 23:04:09 +00:00
Chad Rosier
48b92815e0 Add support for inlining small memcpys. 
rdar://10412592

llvm-svn: 144578
 2011-11-14 22:46:17 +00:00
Chad Rosier
8aa8f14940 Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.

llvm-svn: 144576
 2011-11-14 22:34:48 +00:00
Chad Rosier
65395ac4d0 Add support for Thumb load/stores with negative offsets. 
rdar://10412592

llvm-svn: 144565
 2011-11-14 20:22:27 +00:00
Chad Rosier
0e5094ca87 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592

llvm-svn: 144518
 2011-11-14 04:09:28 +00:00
Chad Rosier
58ab241006 The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
llvm-svn: 144494
 2011-11-13 09:44:21 +00:00
Chad Rosier
8cfccc356e Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
llvm-svn: 144492
 2011-11-13 05:14:43 +00:00
Chad Rosier
0770c4834a Fix comments. 
llvm-svn: 144490
 2011-11-13 04:25:02 +00:00
Chad Rosier
acd199b5a4 Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488
 2011-11-13 02:23:59 +00:00
Chad Rosier
a2a0fbeded Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
llvm-svn: 144426
 2011-11-11 23:31:03 +00:00
Chad Rosier
98f48b009e Rename variables to avoid confusion. No functionallity change intended. 
llvm-svn: 144377
 2011-11-11 06:27:41 +00:00
Chad Rosier
feb72bfc08 Add support for using immediates with select instructions. 
rdar://10412592

llvm-svn: 144376
 2011-11-11 06:20:39 +00:00
Chad Rosier
38f07d3f9c When loading a value, treat an i1 as an i8. 
llvm-svn: 144356
 2011-11-11 02:38:59 +00:00
Chad Rosier
ac92994773 Add support for using MVN to materialize negative constants. 
rdar://10412592

llvm-svn: 144348
 2011-11-11 00:36:21 +00:00
Chad Rosier
7b7dced006 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
 2011-11-10 21:09:49 +00:00
Chad Rosier
69cdae5eb9 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
 2011-11-10 01:30:39 +00:00
Chad Rosier
f47b941510 The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. 
rdar://10418009

llvm-svn: 144213
 2011-11-09 21:30:12 +00:00
Chad Rosier
e32fed6868 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163
 2011-11-09 03:22:02 +00:00
Chad Rosier
24a6e399f8 ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. 
No functional change intended.

llvm-svn: 144122
 2011-11-08 21:12:00 +00:00
Chad Rosier
4b12a5b7fc Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
 2011-11-08 00:03:32 +00:00
Chad Rosier
806ffd8918 Add support for passing i1, i8, and i16 call parameters. Also, be sure to 
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.

llvm-svn: 143821
 2011-11-05 20:16:15 +00:00
Chad Rosier
5e54485e51 Cannot create a result register for non-legal types. 
llvm-svn: 143749
 2011-11-04 23:45:39 +00:00
Chad Rosier
a900a3e2f6 When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit 
in a 16-bit immediate.  However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend.  This prevents us from materializing things
such as 'true' (i.e., i1 1).

llvm-svn: 143743
 2011-11-04 23:09:49 +00:00
Chad Rosier
0143eb6f22 Enable support for materializing i1, i8, and i16 integers via move immediate. 
llvm-svn: 143739
 2011-11-04 22:29:00 +00:00
Chad Rosier
8836fe3bbd Indentation. 
llvm-svn: 143670
 2011-11-04 00:58:10 +00:00
Chad Rosier
21cd759234 Add fast-isel support for returning i1, i8, and i16. 
llvm-svn: 143669
 2011-11-04 00:50:21 +00:00
Chad Rosier
74c4e2c2d9 Add support for sign-extending non-legal types in SelectSIToFP(). 
llvm-svn: 143603
 2011-11-03 02:04:59 +00:00
Chad Rosier
8a613c5ec5 Add support for comparing integer non-legal types. 
llvm-svn: 143559
 2011-11-02 18:08:25 +00:00
Chad Rosier
e94ff7c26e Factor out an EmitIntExt function. No functionality change intended. 
llvm-svn: 143547
 2011-11-02 17:20:24 +00:00
Chad Rosier
f72870096b Factor out a SelectTrunc function. No functionality change intended. 
llvm-svn: 143523
 2011-11-02 00:18:48 +00:00
Chad Rosier
e76ba1b654 A branch predicated on a constant can just FastEmit an unconditional branch. 
llvm-svn: 143086
 2011-10-27 00:21:16 +00:00
Chad Rosier
e3141f4f8b Add a TODO comment. FastISel works by parsing each basic block from the bottom 
up.  Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle.  This creates many more 
opportunities for target specific fast-isel.

llvm-svn: 143079
 2011-10-26 23:34:37 +00:00
Chad Rosier
75378507e3 Factor a little more code into EmitCmp, which should have been done in the first 
place.  No functional change intended.

llvm-svn: 143078
 2011-10-26 23:25:44 +00:00
Chad Rosier
52109646da Use EmitCmp in SelectBranch. No functional change intended. 
llvm-svn: 143076
 2011-10-26 23:17:28 +00:00
Chad Rosier
3f38cb48de Factor out an EmitCmp function that can be used by both SelectCmp and 
SelectBranch.  No functional change intended.

llvm-svn: 143072
 2011-10-26 22:47:55 +00:00
Chad Rosier
ef5ee1892c Add a few FIXME comments. 
llvm-svn: 142299
 2011-10-17 22:54:23 +00:00
Bill Wendling
1d585d7961 Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.

llvm-svn: 140936
 2011-10-01 08:00:54 +00:00
Jim Grosbach
d94ffffc87 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Jim Grosbach
74f96e7f3c Tidy up a few 80 column violations. 
llvm-svn: 139636
 2011-09-13 20:30:37 +00:00
Eli Friedman
383a3c76b2 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Chad Rosier
aa490636db Fixup for functions that return a bool. 
llvm-svn: 138918
 2011-08-31 23:49:05 +00:00
Jim Grosbach
3832c5ac34 [SU]XT[BH] are only available on ARMv6 and up. 
llvm-svn: 138373
 2011-08-23 20:53:08 +00:00
Jim Grosbach
7098677dbc ARM extend instructions simplification. 
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.

llvm-svn: 136225
 2011-07-27 16:47:19 +00:00
Evan Cheng
bff5f78cb5 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. 
llvm-svn: 135636
 2011-07-20 23:34:39 +00:00
Chris Lattner
e1fe7061ce land David Blaikie's patch to de-constify Type, with a few tweaks. 
llvm-svn: 135375
 2011-07-18 04:54:35 +00:00
Evan Cheng
65e7766262 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. 
llvm-svn: 134030
 2011-06-28 21:14:33 +00:00
Evan Cheng
4a169be530 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
 2011-06-28 19:10:37 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Eli Friedman
eae10d6163 Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. 
rdar://9431157

llvm-svn: 132522
 2011-06-03 01:13:19 +00:00
Cameron Zwarich
72e034c331 Fix ARM fast isel to correctly flag memory operands to stores. This fixes 
-verify-machineinstrs failures on several tests.

llvm-svn: 132268
 2011-05-28 20:34:49 +00:00
Eli Friedman
560532051b Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076 
llvm-svn: 132194
 2011-05-27 18:02:04 +00:00
Eli Friedman
93ffb875ad Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent. 
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099
 2011-05-25 23:49:02 +00:00
Eli Friedman
2bdd096540 Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values. 
llvm-svn: 132073
 2011-05-25 19:09:45 +00:00
Jim Grosbach
d7352e9b02 Kill some dead code. 
llvm-svn: 131431
 2011-05-16 22:24:07 +00:00
Eric Christopher
e637bff03a Apparently the check for direct calls is unnecessary. 
llvm-svn: 130716
 2011-05-02 20:16:33 +00:00
Eli Friedman
1940912660 Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns. 
llvm-svn: 130552
 2011-04-29 22:48:03 +00:00
Eric Christopher
5415816eb4 Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but 
if it ever did it needs the def machinery.

llvm-svn: 130549
 2011-04-29 22:07:50 +00:00
Eric Christopher
a6fb14395f Some cleanup and optimize fallthrough more. 
llvm-svn: 130546
 2011-04-29 21:56:31 +00:00
Eli Friedman
7d05eaa3f4 Re-committing r130454, which does not in fact break anything. 
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .

llvm-svn: 130539
 2011-04-29 21:22:56 +00:00
Eric Christopher
ba0cef1b0b Add trunc->branch support, this won't help with clang's i8->i1 truncations 
for bools, but is a start.

llvm-svn: 130534
 2011-04-29 20:02:39 +00:00
Eric Christopher
f7f8f92201 Update comments and checks to match reality. 
llvm-svn: 130464
 2011-04-29 00:07:20 +00:00
Eric Christopher
68cdb30c0d Whitespace. 
llvm-svn: 130463
 2011-04-29 00:03:10 +00:00
Eli Friedman
a93906d0c3 Revert r130454; apparently this doesn't actually work. 
llvm-svn: 130462
 2011-04-28 23:55:14 +00:00
Eli Friedman
9a80f23666 Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. 
rdar://problem/9338332 .

llvm-svn: 130454
 2011-04-28 23:03:25 +00:00
Eric Christopher
2e9c3e61ee Be more layout aware here and swap the successor and branch condition 
if it means we get a fallthrough.

llvm-svn: 130404
 2011-04-28 16:52:09 +00:00
Stuart Hastings
4575e2a398 Correct result when a branch condition is live across a block 
boundary.  <rdar://problem/8933028>

llvm-svn: 129634
 2011-04-16 03:31:26 +00:00
Jay Foad
0d5ca4cf44 Don't include Operator.h from InstrTypes.h. 
llvm-svn: 129271
 2011-04-11 09:35:34 +00:00
Eric Christopher
b04934036a Just use BL all the time. It's safer that way. 
Fixes rdar://9184526

llvm-svn: 128869
 2011-04-05 00:39:26 +00:00
Cameron Zwarich
1b8f91d2c8 Add a ARM-specific SD node for VBSL so that forms with a constant first operand 
can be recognized. This fixes <rdar://problem/9183078>.

llvm-svn: 128584
 2011-03-30 23:01:21 +00:00
Eric Christopher
448c6a5632 Migrate the fix in r128041 to ARM's fastisel support as well. 
Fixes rdar://9169640 

llvm-svn: 128100
 2011-03-22 19:39:17 +00:00
Eric Christopher
80a45901e0 Sometimes isPredicable lies to us and tells us we don't need the operands. 
Go ahead and add them on when we might want to use them and let
later passes remove them.

Fixes rdar://9118569

llvm-svn: 127518
 2011-03-12 01:09:29 +00:00
Eric Christopher
58b95654bc Only use blx for external function calls on thumb, these could be fixed 
up by the dynamic linker, but it's better to use the correct instruction
to begin with.

Fixes rdar://9011034

llvm-svn: 126176
 2011-02-22 01:37:10 +00:00
Eric Christopher
9c446b2711 Use the incoming VT not the VT of where we're trying to store to determine 
if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.

llvm-svn: 124357
 2011-01-27 05:44:56 +00:00
Jeffrey Yasskin
5f5e1f5ef1 Remove unused variables found by gcc-4.6's -Wunused-but-set-variable. 
llvm-svn: 123707
 2011-01-18 00:51:23 +00:00
Evan Cheng
53ec6fc591 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. 
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
 2011-01-17 08:03:18 +00:00
Chris Lattner
d419fe1dfe fix some -Wself-assign warnings. 
llvm-svn: 122893
 2011-01-05 18:41:05 +00:00
Eric Christopher
72ceef0a74 Arm and thumb call instructions are also in different orders. 
Fixes rdar://8782223

llvm-svn: 122313
 2010-12-21 03:50:43 +00:00
Eric Christopher
339499f8f3 Don't handle -arm-long-calls in fast isel for now. 
llvm-svn: 121919
 2010-12-15 23:47:29 +00:00
Eric Christopher
5f7eeae6ba Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.

llvm-svn: 120526
 2010-12-01 01:40:24 +00:00
Eric Christopher
95f0d1fe65 Noticed this on inspection, fix and update some comments. 
llvm-svn: 120447
 2010-11-30 19:14:07 +00:00
Eric Christopher
625238ff3e Update fastisel for the changes in r120272. 
llvm-svn: 120324
 2010-11-29 21:56:23 +00:00
Wesley Peck
d589353ad0 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
llvm-svn: 119990
 2010-11-23 03:31:01 +00:00
Eric Christopher
38b8cfea6a Rewrite address handling to use a structure with all the possible address 
mode variables. Handle frame indexes in load/store and allocas again.

llvm-svn: 119912
 2010-11-20 22:38:27 +00:00
Eric Christopher
5a99947b98 STRH only needs the additional operand, not t2STRH. Also invert conditional 
to match the one from the load emitter above.

llvm-svn: 119911
 2010-11-20 22:01:38 +00:00
Eric Christopher
322b045c95 Don't need to save piecemeal now. 
llvm-svn: 119862
 2010-11-19 22:39:56 +00:00
Eric Christopher
899d8247c8 Update comment. 
llvm-svn: 119861
 2010-11-19 22:37:58 +00:00
Eric Christopher
716f891687 Update comment. 
llvm-svn: 119859
 2010-11-19 22:36:41 +00:00
Eric Christopher
563a0d8b6b Refactor address mode handling into a single struct (ala x86), this 
should give allow a wider range of addressing modes.

No functional change.

llvm-svn: 119856
 2010-11-19 22:30:02 +00:00
Jim Grosbach
be61a90b99 Remove hard tabs. 
llvm-svn: 119810
 2010-11-19 18:01:37 +00:00
Eric Christopher
22b01f0d76 Recommit this change and remove the failing part of the test - it didn't 
pass in the first place and was masked by earlier failures not warning
and aborting the block.

llvm-svn: 119184
 2010-11-15 21:11:06 +00:00
Eric Christopher
f6c7694c29 Temporarily revert this. 
llvm-svn: 118946
 2010-11-12 23:50:48 +00:00
Eric Christopher
b8ee838424 Make this happen for ARM like x86. Don't entirely bail out when 
an address is in a different block, get it into a register and go
from there.

llvm-svn: 118936
 2010-11-12 22:52:32 +00:00
Eric Christopher
1ca7518097 Fix up a few more spots of addrmode2 (or not) changes that were 
missed. Update some comments accordingly.

Fixes rdar://8652289

llvm-svn: 118888
 2010-11-12 09:48:30 +00:00
Jim Grosbach
ce5c2dbeae Trailing whitespace. 
llvm-svn: 118606
 2010-11-09 19:22:26 +00:00
Eric Christopher
3a51a4ada2 Make sure we have movw on the target before using it. 
Fixes 8559.

llvm-svn: 118333
 2010-11-06 07:53:11 +00:00
Duncan Sands
3bf2a701a5 In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
 2010-11-04 10:49:57 +00:00
Eric Christopher
6b586a109e Optimize generated code for integer materialization a bit. 
llvm-svn: 118192
 2010-11-03 20:21:17 +00:00
Duncan Sands
41edf30895 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
 2010-11-03 12:17:33 +00:00
Duncan Sands
f6e5e02c9b Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Eric Christopher
bc79fa1c9e Invert these branches by default, it makes assembly comparisons a little 
easier to read.

llvm-svn: 118148
 2010-11-03 04:29:11 +00:00
Eric Christopher
b817a3e8fe Make sure we're only storing a single bit here. 
llvm-svn: 118126
 2010-11-02 23:59:09 +00:00
Eric Christopher
a376fe69a1 Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.

llvm-svn: 117996
 2010-11-02 01:24:49 +00:00
Eric Christopher
a033f49ed1 Whitespeace 
llvm-svn: 117995
 2010-11-02 01:22:45 +00:00
Eric Christopher
26ddb729bd No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.

llvm-svn: 117994
 2010-11-02 01:21:28 +00:00
Eric Christopher
e012ee8db9 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Eric Christopher
bf7cf2a203 Handle comparison values we already have - this fixes the consumer-typeset 
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
 2010-10-29 21:08:19 +00:00
Jim Grosbach
86ecfda983 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Jim Grosbach
1d5b71b3cc Trailing whitespace 
llvm-svn: 117496
 2010-10-27 21:39:08 +00:00
Jim Grosbach
4d4caf1384 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Eric Christopher
0dab5810aa Move rejection of NEON parameters earlier in fast isel call processing, 
note that we can actually handle some f64 arguments.

llvm-svn: 117209
 2010-10-23 09:37:17 +00:00
Evan Cheng
e5b7a3a09f Silence compiler warnings. 
llvm-svn: 117128
 2010-10-22 18:57:05 +00:00
Eric Christopher
58a6e62c08 Add some basic ret instruction support to arm fast-isel. 
llvm-svn: 117085
 2010-10-22 01:28:00 +00:00
Eric Christopher
59683c9d71 These don't need to be virtual. 
llvm-svn: 117068
 2010-10-21 21:47:51 +00:00
Eric Christopher
7ded7e88c8 Handle storing args to the stack for calls. 
llvm-svn: 117055
 2010-10-21 20:09:54 +00:00
Eric Christopher
b15029ea7e More load/store refactoring, call reg+offset simplification from within 
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051
 2010-10-21 19:40:30 +00:00
Eric Christopher
7989939d87 Custom lower f64 args passed in integer registers. 
llvm-svn: 116977
 2010-10-21 00:01:47 +00:00
Eric Christopher
78c7e84ce5 Fix a TODO by removing some unnecesary copies. 
llvm-svn: 116915
 2010-10-20 08:02:24 +00:00
Eric Christopher
5850afe5f2 Revert r116220 - thus turning arm fast isel back on by default. 
llvm-svn: 116762
 2010-10-18 22:53:53 +00:00
Eric Christopher
e453bd6697 Remove the check for invalid calling conventions. Testing shows that they're 
working just fine.

llvm-svn: 116698
 2010-10-18 06:49:12 +00:00
Eric Christopher
6287738105 Lift arg promotion from the X86 backend. This should be unified at some point. 
llvm-svn: 116694
 2010-10-18 02:17:53 +00:00
Eric Christopher
79c2206640 Now that we handle all allocas via a non-SP reg offset remove all of the 
special case handling for ARM::SP.

llvm-svn: 116688
 2010-10-17 11:08:44 +00:00
Eric Christopher
d99f79f92b Allow more load types to be materialized through the allocas. 
llvm-svn: 116683
 2010-10-17 06:07:26 +00:00
Eric Christopher
5fcaab5d0e Optimize GEP off of intermediate allocas. 
llvm-svn: 116681
 2010-10-17 01:51:42 +00:00
Eric Christopher
20bbcbeceb Fix comment. 
llvm-svn: 116680
 2010-10-17 01:42:53 +00:00
Eric Christopher
d9b4b47b9a Turn on AddOperator folding in GEP. 
llvm-svn: 116679
 2010-10-17 01:41:46 +00:00
Eric Christopher
490f82bc32 Use the i12 immediate versions of the load instructions - they're handled 
more in the post-passes.

llvm-svn: 116678
 2010-10-17 01:40:27 +00:00
Eric Christopher
98c6ce755a Fix some funky formatting that got through. 
llvm-svn: 116653
 2010-10-16 01:10:35 +00:00
Eric Christopher
69eaf30a42 Make sure offset is 0 for load/store register to the stack call. 
llvm-svn: 116640
 2010-10-15 23:07:10 +00:00
Eric Christopher
7f8c3dff07 Fix else if -> if in store machinery. 
llvm-svn: 116628
 2010-10-15 22:32:37 +00:00
Eric Christopher
a875589580 Refactor ARM fast-isel reg + offset to be a base + offset. 
llvm-svn: 116622
 2010-10-15 21:32:12 +00:00
Eric Christopher
b287ab82d7 Expand GEP handling for constant offsets. 
llvm-svn: 116594
 2010-10-15 18:02:07 +00:00
Eric Christopher
9060ac1be3 Handle more complex GEP based loads and add a few TODOs to deal with 
GEP + alloca.

llvm-svn: 116474
 2010-10-14 09:29:41 +00:00
Jim Grosbach
506b966b9d A few 80 column fixes. 
llvm-svn: 116451
 2010-10-13 23:34:31 +00:00
Eric Christopher
19be5bd87c Update comment. 
llvm-svn: 116438
 2010-10-13 21:41:51 +00:00
Eric Christopher
f7ab2cd3df Start handling more global variables. 
llvm-svn: 116401
 2010-10-13 09:11:46 +00:00
Eric Christopher
af5b22e150 Fix thinko in arm fast isel alloca rewrite. 
llvm-svn: 116339
 2010-10-12 21:23:43 +00:00
Eric Christopher
0763cc04c5 Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
 2010-10-12 05:39:06 +00:00
Eric Christopher
8789aa8799 Handle a wider arrangement of loads. 
llvm-svn: 116284
 2010-10-12 00:43:21 +00:00
Eric Christopher
e1574aa60a Use a sane mechanism for that assert. 
llvm-svn: 116249
 2010-10-11 22:01:22 +00:00
Eric Christopher
926a41a84b We're not going to handle dynamic allocas anywhere else. 
llvm-svn: 116240
 2010-10-11 21:37:35 +00:00
Eric Christopher
cac7b248c7 Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232
 2010-10-11 21:20:02 +00:00
Eric Christopher
fa961e31b1 Found a bug turning this on by default. Disable again for now. 
llvm-svn: 116220
 2010-10-11 20:26:21 +00:00
Eric Christopher
ff35a1f090 Fix help text. 
llvm-svn: 116218
 2010-10-11 20:15:02 +00:00
Eric Christopher
b1a93706f7 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217
 2010-10-11 20:05:22 +00:00
Eric Christopher
52c102fef0 Turn on arm fast isel by default. 
llvm-svn: 116212
 2010-10-11 18:48:18 +00:00
Eric Christopher
019eeb9c55 Copy and pasteo. 
llvm-svn: 116198
 2010-10-11 08:40:05 +00:00
Eric Christopher
a412d25090 Whitespace cleanup in ARM fast isel. 
llvm-svn: 116197
 2010-10-11 08:38:55 +00:00
Eric Christopher
c100a052eb Add srem libcall support to ARM fast isel. 
llvm-svn: 116196
 2010-10-11 08:37:26 +00:00
Eric Christopher
af5baa8a0f Add i8 sdiv support for ARM fast isel. 
llvm-svn: 116195
 2010-10-11 08:31:54 +00:00
Eric Christopher
6f65f8a4d3 Implement select handling for ARM fast-isel. 
llvm-svn: 116194
 2010-10-11 08:27:59 +00:00
Eric Christopher
a1d180e00e Fix the store part of this as well. Fixes smg2000. 
llvm-svn: 116123
 2010-10-08 23:52:16 +00:00
Eric Christopher
45a5ff5ca3 Move to thumb2 loads, fixes a problem with incoming registers 
as thumb1.

Fixes lencod.

llvm-svn: 116027
 2010-10-08 01:13:17 +00:00
Eric Christopher
183b18d430 Remember to promote load/store types for stack to register size. 
llvm-svn: 115984
 2010-10-07 21:40:18 +00:00
Eric Christopher
3a068c4252 Use the correct register class for load instructions - fixes 
compilation of MultiSource/Benchmarks/Bullet.

llvm-svn: 115907
 2010-10-07 05:50:44 +00:00
Eric Christopher
b3e9588644 Use the correct register class here. 
llvm-svn: 115906
 2010-10-07 05:39:19 +00:00
Eric Christopher
67ca7a8fe3 Use the thumb2 conditional move instruction. 
llvm-svn: 115905
 2010-10-07 05:31:49 +00:00
Eric Christopher
8b8bce9a5b Remove in-progress assertion, add TODO. 
llvm-svn: 115904
 2010-10-07 05:14:08 +00:00
Eric Christopher
9096fe41cb Comment out fastisel debugging message. 
llvm-svn: 115717
 2010-10-05 23:50:58 +00:00
Eric Christopher
58254f68df Random cleanup and make the intermediate register in fptosi a 
32-bit fp reg, not 64-bit.

Fixes SingleSource.

llvm-svn: 115711
 2010-10-05 23:13:24 +00:00
Eric Christopher
9e303eeb6f Start on lowering global addresses. 
llvm-svn: 115390
 2010-10-02 00:32:44 +00:00
Eric Christopher
c1f6f9a730 Stub out constant GV handling, fixes C++ eh tests. 
llvm-svn: 115375
 2010-10-01 23:24:42 +00:00
Eric Christopher
669452e47f Direct calls only for arm fast isel for now. 
llvm-svn: 115350
 2010-10-01 21:33:12 +00:00
Eric Christopher
7daf669802 Fix thinko on store instructions. Fixes test_indvars failure. 
llvm-svn: 115342
 2010-10-01 20:46:04 +00:00
Eric Christopher
48606deb11 Implement double return values in calls. Fixes 
SingleSource/Regression/C/casts.c.

llvm-svn: 115246
 2010-10-01 00:00:11 +00:00
Eric Christopher
0c94293fb3 Movement and cleanup. 
llvm-svn: 115225
 2010-09-30 22:34:19 +00:00
Eric Christopher
2d33066699 Start of generalized call support for ARM fast isel. 
llvm-svn: 115203
 2010-09-30 20:49:44 +00:00
Eric Christopher
ba01048ae2 Refactor arm fast isel libcall handling so that pieces can be used 
for generic call handling.

llvm-svn: 115105
 2010-09-29 23:11:09 +00:00
Eric Christopher
eb578cf724 Add a convenience variable so I'm not chasing all over looking for 
a context.

llvm-svn: 115094
 2010-09-29 22:24:45 +00:00
Eric Christopher
e81be3c669 Rework comparison handling to set a register on true/false. This avoids 
problems with phi-nodes in blocks that have hard and not virtual registers.

Accordingly update branch handling to compensate.

llvm-svn: 115013
 2010-09-29 01:14:47 +00:00
Eric Christopher
0bde6df6a3 Remove unnecessary set ahead of time. 
llvm-svn: 115011
 2010-09-29 00:50:57 +00:00
Eric Christopher
c9ebc75b88 Remove assert, add comment. 
llvm-svn: 115009
 2010-09-29 00:49:09 +00:00
Eric Christopher
2803dbc225 32-bit constant ints only for now. 
llvm-svn: 115001
 2010-09-28 22:47:54 +00:00
Eric Christopher
3024929d5a Integer materialization needed the same thinko change. 
llvm-svn: 114994
 2010-09-28 21:55:34 +00:00
Eric Christopher
92ed90ad1a Rework builtin handling and call setup. The builtin handling 
now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.

llvm-svn: 114934
 2010-09-28 01:21:42 +00:00
Eric Christopher
fee68ebd81 Fix fp constant loads to have a destination register. 
llvm-svn: 114930
 2010-09-28 00:35:09 +00:00
Eric Christopher
d75d39ce4a Insert missing coherency in comment. Add a quick check for hardware 
divide support also.

llvm-svn: 114813
 2010-09-27 06:08:12 +00:00
Eric Christopher
4f8a73aaa5 Mass rename for Jim. 
llvm-svn: 114812
 2010-09-27 06:02:23 +00:00
Eric Christopher
0c5e912e21 Thumb opcodes for thumb calls. 
llvm-svn: 114263
 2010-09-18 02:32:38 +00:00
Eric Christopher
c9fef312c8 Add addrmode5 fp load support. Swap float/thumb operand adding to handle 
thumb with floating point.

llvm-svn: 114256
 2010-09-18 01:59:37 +00:00
Eric Christopher
b6ce0ab878 Floating point stores have a 3rd addressing mode type. 
llvm-svn: 114254
 2010-09-18 01:23:38 +00:00
Eric Christopher
716614f126 Rework arm fast isel branch and compare code. 
llvm-svn: 114226
 2010-09-17 22:28:18 +00:00
Eric Christopher
c6075a71ad Emit libcalls for SDIV, this requires some call infrastructure 
that needs to be shared a bit more widely around.

llvm-svn: 113886
 2010-09-14 23:03:37 +00:00
Eric Christopher
01d361f9ed Start sketching out ARM fast-isel calls. 
llvm-svn: 113662
 2010-09-10 23:18:12 +00:00
Eric Christopher
1364e542aa For consistency. 
llvm-svn: 113659
 2010-09-10 23:10:30 +00:00
Eric Christopher
54e138031e Fix build error. 
llvm-svn: 113566
 2010-09-10 00:35:09 +00:00
Eric Christopher
92506682eb Update comments, reorganize some code, rename variables to be 
more clear.  No functional change.

llvm-svn: 113565
 2010-09-10 00:34:35 +00:00
Eric Christopher
06f4af2ef4 64-bit fp loads can come straight out of the constant pool, not as 
bad as I'd thought.

llvm-svn: 113561
 2010-09-09 23:50:00 +00:00
Eric Christopher
3c86728bd6 SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move 
some data around and implement a couple of move routines to do this.

llvm-svn: 113546
 2010-09-09 21:44:45 +00:00
Eric Christopher
d5f271d31e New "move to fp reg" routine. Use it. 
llvm-svn: 113537
 2010-09-09 20:49:25 +00:00
Eric Christopher
7208671884 "Strike that, reverse it." -- Mr. Wonka. 
Truncate when truncating, extend when extending.

llvm-svn: 113536
 2010-09-09 20:36:19 +00:00
Eric Christopher
38194e51cc Add FPTrunc, fix some bugs where I forgot to update the value map. 
llvm-svn: 113533
 2010-09-09 20:26:31 +00:00
Eric Christopher
2ba28d3889 Basic FP->Int, Int->FP conversions. 
llvm-svn: 113523
 2010-09-09 18:54:59 +00:00
Eric Christopher
e5bf22fd67 Nuke whitespace and fix some indenting. 
llvm-svn: 113463
 2010-09-09 01:06:51 +00:00
Eric Christopher
8c3a582b5f Handle 64-bit floating point binops as well. 
llvm-svn: 113461
 2010-09-09 01:02:03 +00:00
Eric Christopher
f2f2b06719 Basic 32-bit FP operations. 
llvm-svn: 113459
 2010-09-09 00:53:57 +00:00
Eric Christopher
88c13fcb96 Handle float->double extension. 
llvm-svn: 113455
 2010-09-09 00:26:48 +00:00
Eric Christopher
ebfbac39cf Rewrite TargetMaterializeConstant splitting it out into two functions 
for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.

llvm-svn: 113453
 2010-09-09 00:19:41 +00:00
Eric Christopher
66c62991e0 Very basic compare support. 
llvm-svn: 113440
 2010-09-08 23:13:45 +00:00
Eric Christopher
2a86c17b8d Delete dead code. 
llvm-svn: 113436
 2010-09-08 22:58:35 +00:00
Eric Christopher
bc029c3eb0 Make the loads/stores match the type we really want to store. 
llvm-svn: 113417
 2010-09-08 21:49:50 +00:00
Eric Christopher
4108aae8d3 Rewrite TargetMaterializeConstant. 
llvm-svn: 113387
 2010-09-08 18:56:34 +00:00
Eric Christopher
d8a89e8737 Simple branch instruction support. 
llvm-svn: 112923
 2010-09-03 00:35:47 +00:00
Eric Christopher
3adad3b492 Add basic support for materializing constants (including fp) and 
stores.

llvm-svn: 112912
 2010-09-02 23:43:26 +00:00
Eric Christopher
6c3fa8c78f Clang's -ccc-host-triple was ignoring the arch specifier on my triple, 
I don't need to implement this quite yet - and not for ConstantInt anyhow.

llvm-svn: 112798
 2010-09-02 02:30:46 +00:00
Eric Christopher
cf0b12d117 This should be TargetMaterializeConstant instead. 
llvm-svn: 112795
 2010-09-02 01:48:11 +00:00
Eric Christopher
9dc3582a82 One definition of isThumb is plenty, thanks. 
llvm-svn: 112793
 2010-09-02 01:39:14 +00:00
Eric Christopher
3aa2bb55d8 Rework arm fast-isel load and store handling. Move offset computation 
into the "address selection" routine and handle constant materialization
for stores.

llvm-svn: 112788
 2010-09-02 00:53:56 +00:00
Eric Christopher
abf61f76c9 Some basic store support. 
llvm-svn: 112752
 2010-09-01 22:16:27 +00:00
Eric Christopher
92238b2b5a Add some more load types in. 
llvm-svn: 112721
 2010-09-01 18:01:32 +00:00
Eric Christopher
b2756a8b99 Rewrite slightly so we can expand for floating point types easier. 
llvm-svn: 112568
 2010-08-31 01:28:42 +00:00
Eric Christopher
21b355b522 If we have an unhandled type then assert, we shouldn't get here for 
things we can't handle.

llvm-svn: 112559
 2010-08-30 23:48:26 +00:00
Eric Christopher
1bf07e75ac Do type checks before we bother to do everything else. 
llvm-svn: 112039
 2010-08-25 08:43:57 +00:00
Eric Christopher
9e3831d7a9 Reorganize load mechanisms. Handle types in a little less fixed way. 
Fix some todos.  No functional change.

llvm-svn: 112031
 2010-08-25 07:23:49 +00:00
Eric Christopher
a2d3859ee7 Fix predicate and add a comment. 
llvm-svn: 111981
 2010-08-24 22:34:11 +00:00
Eric Christopher
5477fa47fd Rework braindead conditionals I put in yesterday. 
llvm-svn: 111974
 2010-08-24 22:07:27 +00:00
Eric Christopher
10422f70dc Fix thumb2 mode loads to have the correct operand ordering. Add a todo 
to fix this in the port.

llvm-svn: 111973
 2010-08-24 22:03:02 +00:00
Eric Christopher
c2ed70d52b Update comment. 
llvm-svn: 111887
 2010-08-24 01:10:52 +00:00
Eric Christopher
5f3382bacc Fix the opcode and the operands for the load instruction. 
llvm-svn: 111885
 2010-08-24 01:10:04 +00:00
Eric Christopher
5d1289db95 Add register class hack that needs to go away, but makes it more obvious 
that it needs to go away.  Use loadRegFromStackSlot where possible.

Also, remember to update the value map.

llvm-svn: 111883
 2010-08-24 00:50:47 +00:00
Eric Christopher
696d6ee9d7 Add some more debugging code, make it more obvious that RegOffset is 
getting an address for an object and select some default values.

llvm-svn: 111871
 2010-08-24 00:07:24 +00:00
Eric Christopher
a1652c6ea6 Don't need the extra register here. 
llvm-svn: 111864
 2010-08-23 23:28:04 +00:00
Eric Christopher
2f01adebca Add some more "get address into register" code and a more TODOs/FIXMEs. 
llvm-svn: 111860
 2010-08-23 23:14:31 +00:00
Eric Christopher
7ec47db6b2 Add an ARMFunctionInfo member and use it. 
llvm-svn: 111854
 2010-08-23 22:32:45 +00:00
Eric Christopher
e0d09e27f8 Start getting ARM loads/address computation going. 
llvm-svn: 111850
 2010-08-23 21:44:12 +00:00
Eric Christopher
e082792357 Fix loop conditionals (MO.isDef() asserts that it's a reg) and 
move some constraints around.

llvm-svn: 111594
 2010-08-20 00:36:24 +00:00
Eric Christopher
df3a3f5e3e Add a couple of random comments. 
llvm-svn: 111592
 2010-08-20 00:20:31 +00:00
Eric Christopher
8f9362166c Silence warning. 
llvm-svn: 111518
 2010-08-19 15:35:27 +00:00
Eric Christopher
b80df4f04e Add an AddOptionalDefs method and use it. 
llvm-svn: 111489
 2010-08-19 00:37:05 +00:00
Eric Christopher
9a8050c4e1 Copy over some overridden MI wrappers for ARM fast-isel. This is where 
we're adding predicates and optional defs to the MachineInstrs.

llvm-svn: 111222
 2010-08-17 01:25:29 +00:00
Eric Christopher
8a68f2fc40 Make arm fast-isel possible to enable via command line. 
llvm-svn: 111219
 2010-08-17 00:46:57 +00:00
Evan Cheng
1566171daa ARM fastisel isn't ready. 
llvm-svn: 109421
 2010-07-26 18:32:55 +00:00
Eric Christopher
3d118d5e8a Baby steps towards ARM fast-isel. 
llvm-svn: 109047
 2010-07-21 22:26:11 +00:00