Bob Wilson
fcc42f2f3a
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
Jim Grosbach
b01bcbd047
Encoding info for extension instructions.
...
llvm-svn: 116560
2010-10-15 02:29:58 +00:00
Jim Grosbach
6da1b52d7b
Add missing Rd encoding for MOVs instruction.
...
llvm-svn: 116537
2010-10-14 23:28:31 +00:00
Jim Grosbach
804505c7d4
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
...
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
Jim Grosbach
29dc23398f
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
Jim Grosbach
73c78f8790
MOVi16 and MOVT ARM mode encodings.
...
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
Jim Grosbach
6d5cb39757
Simplify encoding information and add 'dst' operand info for TAILJMP.
...
llvm-svn: 116488
2010-10-14 17:24:28 +00:00
Oscar Fuentes
1f9f1cc125
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
...
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
llvm-svn: 116480
2010-10-14 15:54:46 +00:00
Eric Christopher
9060ac1be3
Handle more complex GEP based loads and add a few TODOs to deal with
...
GEP + alloca.
llvm-svn: 116474
2010-10-14 09:29:41 +00:00
Bill Wendling
2c335d364c
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
...
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
Bill Wendling
33a2ecd5e4
Add encoding for 'fmstat'.
...
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
Bill Wendling
cd41f22ec1
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
Jim Grosbach
684289bc3c
Regenerate. No functional change, just cleanup.
...
llvm-svn: 116459
2010-10-14 00:15:18 +00:00
Jim Grosbach
151502662e
Detabify and clean up 80 column violations.
...
llvm-svn: 116454
2010-10-13 23:47:11 +00:00
Jim Grosbach
506b966b9d
A few 80 column fixes.
...
llvm-svn: 116451
2010-10-13 23:34:31 +00:00
Jim Grosbach
2e8a589fb2
trailing whitespace
...
llvm-svn: 116450
2010-10-13 23:12:26 +00:00
Jim Grosbach
41cd0dd4ba
Add a FIXME.
...
llvm-svn: 116449
2010-10-13 22:55:33 +00:00
Jim Grosbach
4c80dbda49
Add operand encoding bits for SMC and SVC in ARM mode.
...
llvm-svn: 116447
2010-10-13 22:38:23 +00:00
Jim Grosbach
66822f70b8
More encoding cleanup. Also add register Rd operands for indirect branches.
...
llvm-svn: 116444
2010-10-13 22:09:34 +00:00
Jim Grosbach
630efeb050
Simplify some ARM encoding information.
...
llvm-svn: 116440
2010-10-13 21:48:54 +00:00
Eric Christopher
19be5bd87c
Update comment.
...
llvm-svn: 116438
2010-10-13 21:41:51 +00:00
Jim Grosbach
f1d59d0fd5
Add a FIXME. The ADR instruction is a bit odd.
...
llvm-svn: 116437
2010-10-13 21:32:30 +00:00
Jim Grosbach
1699d40f80
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
Bill Wendling
bf63d6eb63
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
Jim Grosbach
3a4bfe4573
Add a FIXME.
...
llvm-svn: 116428
2010-10-13 20:38:04 +00:00
Jim Grosbach
d079fee8b1
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
...
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
llvm-svn: 116427
2010-10-13 20:30:55 +00:00
Jim Grosbach
8f0bea85bf
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
Jim Grosbach
79156dadf2
Fix encoding for compares. No Rd register.
...
llvm-svn: 116414
2010-10-13 18:05:25 +00:00
Jim Grosbach
9c4a598ef2
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
Eric Christopher
f7ab2cd3df
Start handling more global variables.
...
llvm-svn: 116401
2010-10-13 09:11:46 +00:00
Evan Cheng
d07bee932d
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
...
llvm-svn: 116389
2010-10-13 01:54:21 +00:00
Bill Wendling
6d8a23c978
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
Bill Wendling
ea062d454d
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
Jim Grosbach
3fe0337063
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
Bill Wendling
e6c2fdebbd
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
Bill Wendling
fddde4cc72
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
Jim Grosbach
79cebf409d
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
Bill Wendling
47155cfddd
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
Bill Wendling
185b548b07
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
Jim Grosbach
de78ccb013
Move the ARM so_imm encoding into a custom operand encoder and remove the
...
explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
Bill Wendling
d1f06024ce
Refactor some of the encoding logic into a base class. This keeps us from having
...
to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
llvm-svn: 116362
2010-10-12 23:06:54 +00:00
Jim Grosbach
f4cf5bef46
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
...
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
Bill Wendling
cd3cb8da45
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
Bill Wendling
33a26354c1
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
Bill Wendling
79d57782ad
Split out the "size" field from the encoding. The newer documentation has it as
...
a separate bit in the coding.
llvm-svn: 116347
2010-10-12 22:03:19 +00:00
Eric Christopher
af5b22e150
Fix thinko in arm fast isel alloca rewrite.
...
llvm-svn: 116339
2010-10-12 21:23:43 +00:00
Jim Grosbach
58ee6f3972
Encoding for ARM-mode VADD.F32 instruction.
...
llvm-svn: 116338
2010-10-12 21:22:40 +00:00
Jim Grosbach
a0f673b561
Add MOVi ARM encoding.
...
llvm-svn: 116321
2010-10-12 18:09:12 +00:00
Jim Grosbach
dbf116be66
Nuke unused wrapper function.
...
llvm-svn: 116318
2010-10-12 17:53:25 +00:00
Jim Grosbach
10d9bbe0ca
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
Bob Wilson
bbb91c6a1c
PR8359: The ARM backend may end up allocating registers D16 to D31 when
...
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
Eric Christopher
0763cc04c5
Rework alloca handling so that we can load or store from casted
...
address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
Eric Christopher
8789aa8799
Handle a wider arrangement of loads.
...
llvm-svn: 116284
2010-10-12 00:43:21 +00:00
Evan Cheng
6aac1548ab
More ARM scheduling itinerary fixes.
...
llvm-svn: 116266
2010-10-11 23:41:41 +00:00
Jim Grosbach
29ef87e765
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
Jason W Kim
59375bae75
Second set of ARM/MC/ELF changes.
...
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
Evan Cheng
77ba7b098a
Proper VST scheduling itineraries.
...
llvm-svn: 116251
2010-10-11 22:03:18 +00:00
Eric Christopher
e1574aa60a
Use a sane mechanism for that assert.
...
llvm-svn: 116249
2010-10-11 22:01:22 +00:00
Eric Christopher
926a41a84b
We're not going to handle dynamic allocas anywhere else.
...
llvm-svn: 116240
2010-10-11 21:37:35 +00:00
Eric Christopher
cac7b248c7
Make sure that the call stack adjustments have default operands. Also
...
leave custom lowerings for later.
Fixes some nightly tests.
llvm-svn: 116232
2010-10-11 21:20:02 +00:00
Eric Christopher
fa961e31b1
Found a bug turning this on by default. Disable again for now.
...
llvm-svn: 116220
2010-10-11 20:26:21 +00:00
Eric Christopher
ff35a1f090
Fix help text.
...
llvm-svn: 116218
2010-10-11 20:15:02 +00:00
Eric Christopher
b1a93706f7
Change flag from Enable to Disable since we're enabled by default.
...
Also don't use fast-isel on non-darwin since it's untested.
llvm-svn: 116217
2010-10-11 20:05:22 +00:00
Jim Grosbach
a697e32f36
More binary encoding stuff, taking advantage of the new "by name" operand
...
matching in tblgen to do the predicate operand.
llvm-svn: 116213
2010-10-11 18:51:51 +00:00
Eric Christopher
52c102fef0
Turn on arm fast isel by default.
...
llvm-svn: 116212
2010-10-11 18:48:18 +00:00
Francois Pichet
80ec466cf5
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
...
llvm-svn: 116201
2010-10-11 11:36:19 +00:00
Eric Christopher
019eeb9c55
Copy and pasteo.
...
llvm-svn: 116198
2010-10-11 08:40:05 +00:00
Eric Christopher
a412d25090
Whitespace cleanup in ARM fast isel.
...
llvm-svn: 116197
2010-10-11 08:38:55 +00:00
Eric Christopher
c100a052eb
Add srem libcall support to ARM fast isel.
...
llvm-svn: 116196
2010-10-11 08:37:26 +00:00
Eric Christopher
af5baa8a0f
Add i8 sdiv support for ARM fast isel.
...
llvm-svn: 116195
2010-10-11 08:31:54 +00:00
Eric Christopher
6f65f8a4d3
Implement select handling for ARM fast-isel.
...
llvm-svn: 116194
2010-10-11 08:27:59 +00:00
Evan Cheng
8c17a06411
Add VLD4 scheduling itineraries.
...
llvm-svn: 116143
2010-10-09 04:07:58 +00:00
Evan Cheng
df7f5672ee
Finish vld3 and vld4.
...
llvm-svn: 116140
2010-10-09 01:45:34 +00:00
Evan Cheng
bf6307d869
Complete vld2 instruction itineries.
...
llvm-svn: 116136
2010-10-09 01:26:12 +00:00
Evan Cheng
c0933d5ec1
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
...
llvm-svn: 116135
2010-10-09 01:15:04 +00:00
Evan Cheng
15fc769cf2
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
Bill Wendling
ba58fb0f42
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
Eric Christopher
a1d180e00e
Fix the store part of this as well. Fixes smg2000.
...
llvm-svn: 116123
2010-10-08 23:52:16 +00:00
Jim Grosbach
3075d28c15
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
Jim Grosbach
85b45fcc52
Reapply 116059, this time without the fatfingered pasto at the top.
...
''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
Jim Grosbach
674fa65e33
Reverting 116059. Bots are unhappy with it.
...
llvm-svn: 116064
2010-10-08 17:28:40 +00:00
Jim Grosbach
8d4bb23650
'const'ify getMachineOpValue() and associated helpers.
...
llvm-svn: 116059
2010-10-08 16:52:44 +00:00
Bob Wilson
8689a52c10
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
Eric Christopher
45a5ff5ca3
Move to thumb2 loads, fixes a problem with incoming registers
...
as thumb1.
Fixes lencod.
llvm-svn: 116027
2010-10-08 01:13:17 +00:00
Jim Grosbach
1214818a3e
Enable binary encoding of some simple instructions.
...
llvm-svn: 116022
2010-10-08 00:39:21 +00:00
Jim Grosbach
df2ff926a6
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
Evan Cheng
7fa1e3a474
Code refactoring.
...
llvm-svn: 116002
2010-10-07 23:12:15 +00:00
Jim Grosbach
e949170bad
Trivial MC code emitter shell. No instruction forms actually handled yet.
...
llvm-svn: 115993
2010-10-07 22:12:50 +00:00
Jim Grosbach
ec0a25f2b1
Include the auto-generated bits for machine encoding.
...
llvm-svn: 115987
2010-10-07 21:57:55 +00:00
Eric Christopher
183b18d430
Remember to promote load/store types for stack to register size.
...
llvm-svn: 115984
2010-10-07 21:40:18 +00:00
Jim Grosbach
671713cc62
ARM instruction don't have instruction prefixes, so remove the helper functions
...
for them from the MCCodeEmitter.
llvm-svn: 115975
2010-10-07 20:41:30 +00:00
Eric Christopher
3a068c4252
Use the correct register class for load instructions - fixes
...
compilation of MultiSource/Benchmarks/Bullet.
llvm-svn: 115907
2010-10-07 05:50:44 +00:00
Eric Christopher
b3e9588644
Use the correct register class here.
...
llvm-svn: 115906
2010-10-07 05:39:19 +00:00
Eric Christopher
67ca7a8fe3
Use the thumb2 conditional move instruction.
...
llvm-svn: 115905
2010-10-07 05:31:49 +00:00
Eric Christopher
8b8bce9a5b
Remove in-progress assertion, add TODO.
...
llvm-svn: 115904
2010-10-07 05:14:08 +00:00
Evan Cheng
1ce29574c2
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
...
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
Jim Grosbach
c0a61c0796
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
Jim Grosbach
1e2566c20d
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
Jim Grosbach
f2c54c9cf3
remove trailing whitespace
...
llvm-svn: 115860
2010-10-06 22:46:47 +00:00
Jason W Kim
de3044dcd1
First in a sequence of ARM/MC/*ELF* specific work.
...
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
Jim Grosbach
de2bd8cd3f
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
Jim Grosbach
4c7da8acbc
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
Jim Grosbach
e8a4fef4ea
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
...
"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
Jim Grosbach
e1e07b6bf1
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
...
pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
Jim Grosbach
54490de165
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
Jim Grosbach
dd7ee2836f
target operand flag values aren't a bitmask
...
llvm-svn: 115798
2010-10-06 16:51:55 +00:00
Evan Cheng
6fbb6dea7c
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
Chris Lattner
0b644ced02
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
Eric Christopher
9096fe41cb
Comment out fastisel debugging message.
...
llvm-svn: 115717
2010-10-05 23:50:58 +00:00
Eric Christopher
58254f68df
Random cleanup and make the intermediate register in fptosi a
...
32-bit fp reg, not 64-bit.
Fixes SingleSource.
llvm-svn: 115711
2010-10-05 23:13:24 +00:00
Jim Grosbach
7c112a9c65
Increase the number of bits used internally by the ARM target to represent the
...
addressing mode from four to five.
llvm-svn: 115645
2010-10-05 18:14:55 +00:00
Michael J. Spencer
d26ae30ed9
fix MSVC 2010 build.
...
llvm-svn: 115594
2010-10-05 06:00:43 +00:00
Michael J. Spencer
12a13def14
Cleanup Whitespace.
...
llvm-svn: 115593
2010-10-05 06:00:33 +00:00
Rafael Espindola
49d508fd19
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
...
so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
Evan Cheng
e8eec016c8
Major changes to Cortex-A9 itinerary.
...
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
llvm-svn: 115457
2010-10-03 02:03:59 +00:00
Eric Christopher
9e303eeb6f
Start on lowering global addresses.
...
llvm-svn: 115390
2010-10-02 00:32:44 +00:00
Jim Grosbach
a158e3e6c1
PrintSpecial() can go away now.
...
llvm-svn: 115376
2010-10-01 23:27:48 +00:00
Eric Christopher
c1f6f9a730
Stub out constant GV handling, fixes C++ eh tests.
...
llvm-svn: 115375
2010-10-01 23:24:42 +00:00
Jim Grosbach
619f1c1cc5
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
Jim Grosbach
8440cebbe9
Nuke a bunch of no-longer-needed comment-only asm strings.
...
llvm-svn: 115370
2010-10-01 23:09:33 +00:00
Evan Cheng
b068d1483a
Fix r115332: correctly model AGU / NEON mux.
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llvm-svn: 115365
2010-10-01 22:52:29 +00:00
Owen Anderson
95581657a4
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
...
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
llvm-svn: 115364
2010-10-01 22:45:50 +00:00
Jim Grosbach
2143c9d321
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
Evan Cheng
0da8dff3c7
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
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llvm-svn: 115354
2010-10-01 21:48:06 +00:00
Evan Cheng
cf5ed3cd53
Add operand cycles for vldr / vstr.
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llvm-svn: 115353
2010-10-01 21:40:30 +00:00
Eric Christopher
669452e47f
Direct calls only for arm fast isel for now.
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llvm-svn: 115350
2010-10-01 21:33:12 +00:00
Evan Cheng
fc1aee5b3c
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
...
llvm-svn: 115344
2010-10-01 20:50:58 +00:00
Eric Christopher
7daf669802
Fix thinko on store instructions. Fixes test_indvars failure.
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llvm-svn: 115342
2010-10-01 20:46:04 +00:00
Owen Anderson
e93e24ee5d
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
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llvm-svn: 115341
2010-10-01 20:33:47 +00:00
Owen Anderson
d6aa3da08e
Provide an option to restore old-style if-conversion heuristics for Thumb2.
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llvm-svn: 115339
2010-10-01 20:28:06 +00:00
Evan Cheng
c7c6c2d04d
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
...
llvm-svn: 115332
2010-10-01 19:41:46 +00:00
Jim Grosbach
1a837b8495
grammar
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llvm-svn: 115314
2010-10-01 14:57:48 +00:00
Eric Christopher
48606deb11
Implement double return values in calls. Fixes
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SingleSource/Regression/C/casts.c.
llvm-svn: 115246
2010-10-01 00:00:11 +00:00
Owen Anderson
918c558636
Temporarily add a flag to make it easier to compare the new-style ARM if
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conversion heuristics to the old-style ones.
llvm-svn: 115239
2010-09-30 23:48:38 +00:00
Eric Christopher
0c94293fb3
Movement and cleanup.
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llvm-svn: 115225
2010-09-30 22:34:19 +00:00
Eric Christopher
2d33066699
Start of generalized call support for ARM fast isel.
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llvm-svn: 115203
2010-09-30 20:49:44 +00:00
Jim Grosbach
2bf1c488de
Nuke a few more unused asm strings
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llvm-svn: 115193
2010-09-30 19:53:58 +00:00
Jim Grosbach
8bf43f57d4
Move getPointerSize() to the base class since it's not dependent on MachO
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vs. ELF
llvm-svn: 115180
2010-09-30 17:45:51 +00:00
Jim Grosbach
5d93ed90e5
Remove extraneous ';'
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llvm-svn: 115176
2010-09-30 17:19:17 +00:00
Jim Grosbach
52b5709c99
The asm strings are never used at all, so just nuke 'em entirely.
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llvm-svn: 115160
2010-09-30 16:56:53 +00:00
Kevin Enderby
dd3306fcb5
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
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for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
Jim Grosbach
37fbea8ac9
80 column fix
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llvm-svn: 115149
2010-09-30 15:25:22 +00:00
Jason W Kim
b181166ffc
Fix two tiny issues (ARM does not need COFF) and comment sanity.
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llvm-svn: 115147
2010-09-30 14:58:19 +00:00
Jim Grosbach
4ad95fa930
trailing whitespace
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llvm-svn: 115136
2010-09-30 03:21:00 +00:00
Jim Grosbach
5b0ae02149
Remove misplaced ';'. Make buildbots happy, hopefully.
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llvm-svn: 115135
2010-09-30 03:20:34 +00:00
Jason W Kim
7822e6aab5
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
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Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
Jim Grosbach
ad67153eb3
Go ahead and jump!
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Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
Jason W Kim
6d7784e5f5
I added a new file ARMAsmBackend which stubs out in similar ways to
...
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
llvm-svn: 115129
2010-09-30 02:17:26 +00:00
Jim Grosbach
3a7ca3301b
Now that the pseudos that needed this are all custom lowered, we can go back
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to an empty PrintSpecial()
llvm-svn: 115128
2010-09-30 02:02:22 +00:00
Jim Grosbach
efad965653
Nuke it from orbit. It's the only way to be sure.
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(Kill the dead non-MC asm printer for the ARM target.)
llvm-svn: 115127
2010-09-30 01:57:53 +00:00
Evan Cheng
fa5d40dbff
ARM instruction itinerary fixes:
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
Eric Christopher
ba01048ae2
Refactor arm fast isel libcall handling so that pieces can be used
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for generic call handling.
llvm-svn: 115105
2010-09-29 23:11:09 +00:00
Evan Cheng
b44d480808
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
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pipeline forwarding path.
llvm-svn: 115098
2010-09-29 22:42:35 +00:00
Eric Christopher
eb578cf724
Add a convenience variable so I'm not chasing all over looking for
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a context.
llvm-svn: 115094
2010-09-29 22:24:45 +00:00
Jim Grosbach
fd8705ab4a
Add specializations of addrmode2 that allow differentiating those forms
...
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
llvm-svn: 115066
2010-09-29 19:03:54 +00:00
Bob Wilson
d16aaccb05
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
2010-09-29 17:54:10 +00:00
Jim Grosbach
9939090a14
Add braces for legibility.
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llvm-svn: 115043
2010-09-29 17:32:29 +00:00
Jim Grosbach
fe21554145
One Printer to rule them all, One Printer to find them,
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One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
llvm-svn: 115038
2010-09-29 15:23:40 +00:00
Gabor Greif
e1de402213
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
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added some doxygen on the way
llvm-svn: 115033
2010-09-29 10:12:08 +00:00
Chris Lattner
cbecb9a4d3
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
Chris Lattner
9b9a847b8c
change the protocol TargetAsmPArser::MatchInstruction method to take an
...
MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
llvm-svn: 115014
2010-09-29 01:42:58 +00:00
Eric Christopher
e81be3c669
Rework comparison handling to set a register on true/false. This avoids
...
problems with phi-nodes in blocks that have hard and not virtual registers.
Accordingly update branch handling to compensate.
llvm-svn: 115013
2010-09-29 01:14:47 +00:00
Eric Christopher
0bde6df6a3
Remove unnecessary set ahead of time.
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llvm-svn: 115011
2010-09-29 00:50:57 +00:00
Evan Cheng
7eb08b1ad9
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
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llvm-svn: 115010
2010-09-29 00:49:25 +00:00
Eric Christopher
c9ebc75b88
Remove assert, add comment.
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llvm-svn: 115009
2010-09-29 00:49:09 +00:00
Evan Cheng
7fffe3cf58
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
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llvm-svn: 115008
2010-09-29 00:27:46 +00:00
Evan Cheng
39c462b4f1
Add support to model pipeline bypass / forwarding.
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llvm-svn: 115005
2010-09-28 23:50:49 +00:00
Eric Christopher
2803dbc225
32-bit constant ints only for now.
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llvm-svn: 115001
2010-09-28 22:47:54 +00:00
Oscar Fuentes
eb27a44982
Removed a bunch of unnecessary target_link_libraries.
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llvm-svn: 114999
2010-09-28 22:39:14 +00:00
Owen Anderson
c34e1296b8
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
...
cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
llvm-svn: 114995
2010-09-28 21:57:50 +00:00
Eric Christopher
3024929d5a
Integer materialization needed the same thinko change.
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llvm-svn: 114994
2010-09-28 21:55:34 +00:00
Nick Lewycky
b9daeb2fd0
Resolve this GCC warning:
...
ARMTargetMachine.cpp:53: error: control reaches end of non-void function
llvm-svn: 114992
2010-09-28 21:40:26 +00:00
Anton Korobeynikov
f1be021755
User proper libcall names & condcodes while compiling for ARM EABI.
...
Patch by Evzen Muller!
llvm-svn: 114991
2010-09-28 21:39:26 +00:00
Owen Anderson
c0e1200323
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
...
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
llvm-svn: 114973
2010-09-28 18:32:13 +00:00
Jim Grosbach
7915d03313
Factor out dbg_value comment printing and teach MC asm printing to use it.
...
This should make the arm-linux self-host buildbot happy again.
llvm-svn: 114964
2010-09-28 17:05:56 +00:00
Oscar Fuentes
cd481d2723
Add ARM Disassembler to the CMake build.
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llvm-svn: 114949
2010-09-28 11:48:19 +00:00
Eric Christopher
bff0f1805f
80-col fixups.
...
llvm-svn: 114943
2010-09-28 04:18:29 +00:00
Bob Wilson
dc396388cb
Add a command line option "-arm-strict-align" to disallow unaligned memory
...
accesses for ARM targets that would otherwise allow it. Radar 8465431.
llvm-svn: 114941
2010-09-28 04:09:35 +00:00
Eric Christopher
92ed90ad1a
Rework builtin handling and call setup. The builtin handling
...
now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.
llvm-svn: 114934
2010-09-28 01:21:42 +00:00
Eric Christopher
7d87a75fa4
Fix typo.
...
llvm-svn: 114931
2010-09-28 00:35:33 +00:00
Eric Christopher
fee68ebd81
Fix fp constant loads to have a destination register.
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llvm-svn: 114930
2010-09-28 00:35:09 +00:00
Jim Grosbach
ffbf83e49f
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
...
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114915
2010-09-27 22:28:11 +00:00
Jim Grosbach
0d15b006f7
ARM-mode eh.sjlj.longjmp MC lowering
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llvm-svn: 114896
2010-09-27 21:47:04 +00:00
Jim Grosbach
8cf10ca1cc
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
...
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114892
2010-09-27 21:28:44 +00:00
Daniel Dunbar
1f022a72ba
Hard to imagine there are still people using inferior compilers.
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llvm-svn: 114862
2010-09-27 20:12:58 +00:00
Rafael Espindola
3e325614db
Odd additional stub framework for the ARM MC ELF emission.
...
llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm
Patch by Jason Kim.
llvm-svn: 114856
2010-09-27 18:31:37 +00:00
Eric Christopher
d75d39ce4a
Insert missing coherency in comment. Add a quick check for hardware
...
divide support also.
llvm-svn: 114813
2010-09-27 06:08:12 +00:00
Eric Christopher
4f8a73aaa5
Mass rename for Jim.
...
llvm-svn: 114812
2010-09-27 06:02:23 +00:00
Evan Cheng
b64d587918
Fix IIC_iEXTAr itinerary class of Cortex-A9.
...
llvm-svn: 114784
2010-09-25 01:09:28 +00:00
Evan Cheng
2279dc1d2a
Remove a unused instruction itinerary class.
...
llvm-svn: 114782
2010-09-25 01:06:02 +00:00
Evan Cheng
64a24ab747
Fix zero and sign extension instructions scheduling itineraries.
...
llvm-svn: 114780
2010-09-25 00:49:35 +00:00
Evan Cheng
124ae30ef8
More pseudo instruction scheduling itinerary fixes.
...
llvm-svn: 114768
2010-09-24 22:41:41 +00:00
Evan Cheng
eb81dc39dc
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
...
llvm-svn: 114766
2010-09-24 22:03:46 +00:00
Jim Grosbach
f0bbd8c533
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
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llvm-svn: 114758
2010-09-24 20:47:58 +00:00
Evan Cheng
1d50dccdc5
Enable code placement optimization pass for ARM.
...
llvm-svn: 114746
2010-09-24 19:07:23 +00:00
Evan Cheng
54374c30f9
Fix a potential null dereference bug.
...
llvm-svn: 114723
2010-09-24 05:18:35 +00:00
Owen Anderson
4fc55c0e02
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
Bob Wilson
ff8139baa0
Set alignment operand for NEON VST instructions.
...
llvm-svn: 114709
2010-09-23 23:42:37 +00:00
Jim Grosbach
66ced0b804
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
...
llvm-svn: 114707
2010-09-23 23:33:56 +00:00
Jim Grosbach
c6efcc192d
#+4 --> #4 for consistency with other asm output
...
llvm-svn: 114706
2010-09-23 23:32:38 +00:00