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580 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
e58d077846 Add VCVTPD2PS, VCVTPS2DQ, VCVTPS2PDY, VCVTTPD2DQY, VCVTTPS2DQ and VCVTPD2DQ 256-bit conversion intrinsics 
llvm-svn: 110608
 2010-08-09 21:51:56 +00:00
Bruno Cardoso Lopes
e7ceec4edf Add patterns to AVX conversions instructions. Do that instead of declaring more intructions whenever is possible, more coming 
llvm-svn: 110605
 2010-08-09 21:24:59 +00:00
Bruno Cardoso Lopes
6a92e01d05 Memory version of vcvtdq2pd intrinsic 
llvm-svn: 110582
 2010-08-09 18:20:14 +00:00
Bruno Cardoso Lopes
0794b8ab3f Patterns to match vinsert, vbroadcast, vmovmask and vcvtdq2pd AVX intrinsics 
llvm-svn: 110580
 2010-08-09 18:03:43 +00:00
Dale Johannesen
23f9086dd3 Use sdmem and sse_load_f64 (etc.) for the vector 
form of CMPSD (etc.)  Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.)  8193553.

llvm-svn: 110491
 2010-08-07 00:33:42 +00:00
Bruno Cardoso Lopes
5b602f8822 Patterns to match AVX 256-bit vzero intrinsics 
llvm-svn: 110480
 2010-08-06 22:10:01 +00:00
Bruno Cardoso Lopes
821eebf946 Patterns to match AVX 256-bit permutation intrinsics 
llvm-svn: 110468
 2010-08-06 20:03:27 +00:00
Bruno Cardoso Lopes
d186fba555 Patterns to match AVX 256-bit horizontal arithmetic intrinsics 
llvm-svn: 110427
 2010-08-06 02:10:30 +00:00
Bruno Cardoso Lopes
5e9f9c921e Patterns to match AVX 256-bit arithmetic intrinsics 
llvm-svn: 110425
 2010-08-06 01:52:29 +00:00
Bruno Cardoso Lopes
0c0dd2173c Support all 128-bit AVX vector intrinsics. Most part of them I already 
declared during the addition of the assembler support, the additional
changes are:
- Add missing intrinsics
- Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file.
- Duplicate some patterns to AVX mode.
- Step into PCMPEST/PCMPIST custom inserter and add AVX versions.

llvm-svn: 109878
 2010-07-30 19:54:33 +00:00
Bruno Cardoso Lopes
a80b57e5fc Add AVX version of CLMUL instructions 
llvm-svn: 109248
 2010-07-23 18:41:12 +00:00
Bruno Cardoso Lopes
93fd8bdf6a Fix some AVX instructions which didnt had HasAVX prefix. And also a problem with PINSRW, which was totally wrong because of a typo I introduced previously 
llvm-svn: 109198
 2010-07-23 00:14:54 +00:00
Bruno Cardoso Lopes
7722724eee Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step 
llvm-svn: 109168
 2010-07-22 21:18:49 +00:00
Eric Christopher
4924d5fb93 Custom lower the memory barrier instructions and add support 
for lowering without sse2.  Add a couple of new testcases.

Fixes a few libgomp tests and latent bugs.  Remove a few todos.

llvm-svn: 109078
 2010-07-22 02:48:34 +00:00
Bruno Cardoso Lopes
5920e38cd2 Add more 256-bit forms for a bunch of regular AVX instructions 
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)

llvm-svn: 109063
 2010-07-21 23:53:50 +00:00
Bruno Cardoso Lopes
eea3b7ed83 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it 
llvm-svn: 109039
 2010-07-21 21:37:59 +00:00
Bruno Cardoso Lopes
1284fdc932 Avoid AVX instructions to be selected instead of its SSE form 
llvm-svn: 109032
 2010-07-21 20:38:42 +00:00
Bruno Cardoso Lopes
d13d8c2562 Add AVX only vzeroall and vzeroupper instructions 
llvm-svn: 109002
 2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
c4d93a5a34 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions 
llvm-svn: 108984
 2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
a7efb29695 Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
llvm-svn: 108983
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
e0dce1c741 Add new AVX vextractf128 instructions 
llvm-svn: 108964
 2010-07-20 23:19:02 +00:00
Bruno Cardoso Lopes
b677cbc9b2 Add new AVX instruction vinsertf128 
llvm-svn: 108892
 2010-07-20 19:44:51 +00:00
Bruno Cardoso Lopes
88869cb4db Add AVX vbroadcast new instruction 
llvm-svn: 108788
 2010-07-20 00:11:13 +00:00
Bruno Cardoso Lopes
4ca44dda21 Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! 
llvm-svn: 108769
 2010-07-19 23:32:44 +00:00
Bruno Cardoso Lopes
0616a418b6 Add AVX 256-bit compare instructions and a bunch of testcases 
llvm-svn: 108286
 2010-07-13 22:06:38 +00:00
Bruno Cardoso Lopes
7bc71d2d0a AVX 256-bit conversion instructions 
Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274
 2010-07-13 21:07:28 +00:00
Bruno Cardoso Lopes
ae37153b05 Add AVX 256-bit packed logical forms 
llvm-svn: 108224
 2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
495ae629bb Add AVX 256-bit unop arithmetic instructions 
llvm-svn: 108223
 2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
185483638b Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions 
llvm-svn: 108222
 2010-07-13 00:38:47 +00:00
David Greene
d81591ee09 Move some SIMD fragment code into X86InstrFragmentsSIMD so that the 
utility classes can be used from multiple files.  This will aid
transitioning to a new refactored x86 SIMD specification.

llvm-svn: 108213
 2010-07-12 23:41:28 +00:00
Bruno Cardoso Lopes
852e3bf472 Add AVX 256 binary arithmetic instructions 
llvm-svn: 108207
 2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes
b021506033 More refactoring of basic SSE arith instructions. Open room for 256-bit instructions 
llvm-svn: 108204
 2010-07-12 22:41:32 +00:00
Dan Gohman
e9c4426bb0 Apply the SSE dependence idiom for SSE unary operations to 
SD instructions too, in addition to SS instructions. And
add a comment about it.

llvm-svn: 108191
 2010-07-12 20:46:04 +00:00
Bruno Cardoso Lopes
a4889e6f93 Add AVX 256-bit MOVMSK forms 
llvm-svn: 108184
 2010-07-12 20:06:32 +00:00
Bruno Cardoso Lopes
f4180a9a7b Add AVX 256-bit packed MOVNT variants 
llvm-svn: 108021
 2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes
6ca8dc935c Add AVX 256-bit unpack and interleave 
llvm-svn: 108017
 2010-07-09 21:20:35 +00:00
Bruno Cardoso Lopes
3676e24b67 Start the support for AVX instructions with 256-bit %ymm registers. A couple of 
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996
 2010-07-09 18:27:43 +00:00
Bruno Cardoso Lopes
8d350872d4 Add AVX AES instructions 
llvm-svn: 107798
 2010-07-07 18:24:20 +00:00
Bruno Cardoso Lopes
6222076cd1 Add AVX SSE4.2 instructions 
llvm-svn: 107752
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
931471d7e8 Use only one multiclass to pinsrq instructions 
llvm-svn: 107750
 2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
65fbd0530f Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes 
llvm-svn: 107749
 2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
675ebe2dc0 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
llvm-svn: 107747
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
fa10461265 Add AVX SSE4.1 extractps and pinsr instructions 
llvm-svn: 107746
 2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
54c2f858b3 Add AVX SSE4.1 Extract Integer instructions 
llvm-svn: 107740
 2010-07-07 00:07:24 +00:00
Bruno Cardoso Lopes
b9e1c33054 Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107723
 2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
0c6ec0b068 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107720
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
a0b37e839c Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Chris Lattner
e7c95bcd9e rip out even more sporadic v2f32 support. 
llvm-svn: 107610
 2010-07-05 04:38:33 +00:00
Bill Wendling
689155c673 Revert r107583. I no longer think that this is the way to solve the problem. 
llvm-svn: 107585
 2010-07-04 09:16:57 +00:00
Bill Wendling
8a3ecba7a4 Mark sse_load_f32 and sse_load_f64 as having memory operands 
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.

llvm-svn: 107583
 2010-07-04 08:59:55 +00:00
Bruno Cardoso Lopes
dc16024895 Add AVX SSE4.1 blend, mpsadbw and vdp 
llvm-svn: 107560
 2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
9cbb625579 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions 
llvm-svn: 107558
 2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
df02d037e4 Add AVX SSE4.1 Horizontal Minimum and Position instruction 
llvm-svn: 107552
 2010-07-03 00:49:21 +00:00
Bruno Cardoso Lopes
e6b70efcb0 Add AVX SSE4.1 round instructions 
llvm-svn: 107549
 2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
473863e456 Simple refactoring of SSE4.1 instructions, making room for the AVX forms 
llvm-svn: 107540
 2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes
4931e183b5 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523
 2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes
c5670fcb23 Shrink down SSE3 code by more multiclass refactoring 
llvm-svn: 107448
 2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
c215186088 Shrink down SSE3 code by some multiclass refactoring - 1st part 
llvm-svn: 107438
 2010-07-01 22:33:18 +00:00
Bruno Cardoso Lopes
511e5f47de Move SSE3 Move patterns to a more appropriate section 
Add AVX SSE3 packed horizontal and & sub instructions

llvm-svn: 107405
 2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
0a3048e8b9 Add AVX SSE3 packed addsub instructions 
llvm-svn: 107404
 2010-07-01 17:08:18 +00:00
Bruno Cardoso Lopes
c1abe91367 Add AVX SSE3 replicate and convert instructions 
llvm-svn: 107375
 2010-07-01 02:33:39 +00:00
Bruno Cardoso Lopes
956316a3d7 - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ae1ebd3b4 Move MOVD/MODQ code around, creating sections for each of them 
llvm-svn: 107308
 2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
f8855c22be Add AVX SSE2 mask creation and conditional store instructions 
llvm-svn: 107306
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
6c468039a2 Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable 
llvm-svn: 107300
 2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
3c02702830 Add AVX SSE2 packed integer extract/insert instructions 
llvm-svn: 107293
 2010-06-30 17:03:03 +00:00
Bruno Cardoso Lopes
39594cc5d0 Add AVX SSE2 integer unpack instructions 
llvm-svn: 107246
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
419f8f29c3 Add AVX SSE2 packed integer shuffle instructions 
llvm-svn: 107245
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
c2f5cd2389 Small refactoring of SSE2 packed integer shuffle instructions 
llvm-svn: 107243
 2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
d9acb34aa2 Add AVX SSE2 pack with saturation integer instructions 
llvm-svn: 107241
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c470ba9937 Add AVX SSE2 integer packed compare instructions 
llvm-svn: 107240
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
cfbebb3921 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
2439877e05 Add *several* AVX integer packed binop instructions 
llvm-svn: 107225
 2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
b80121d316 Move SSE2 Packed Integer instructions around, and create specific sections for each of them 
llvm-svn: 107211
 2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
45e0ab4762 Add AVX Move Aligned/Unaligned packed integers 
llvm-svn: 107206
 2010-06-29 21:25:12 +00:00
Bruno Cardoso Lopes
e1b05180de Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
e60533aa42 Add AVX non-temporal stores 
llvm-svn: 107178
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
4731169504 Move non-temporal movs to their own section 
llvm-svn: 107168
 2010-06-29 17:42:37 +00:00
Bruno Cardoso Lopes
2dca1dd168 Add sqrt, rsqrt and rcp AVX instructions 
llvm-svn: 107166
 2010-06-29 17:26:30 +00:00
Bruno Cardoso Lopes
1fe3ed0e67 Refactoring of arithmetic instruction classes with unary operator 
llvm-svn: 107116
 2010-06-29 01:33:09 +00:00
Bruno Cardoso Lopes
e4809f15bf Described the missing AVX forms of SSE2 convert instructions 
llvm-svn: 107108
 2010-06-29 00:36:02 +00:00
Bruno Cardoso Lopes
277fcdf1c1 Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
llvm-svn: 106917
 2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
45109dd6c1 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
cc4c01f859 revert this now, it's using avx instead of sse :) 
llvm-svn: 106906
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
04ac570a8d Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg

llvm-svn: 106896
 2010-06-25 22:27:51 +00:00
Dan Gohman
388f198fe5 pcmpeqd and friends are Commutable. 
llvm-svn: 106886
 2010-06-25 21:05:35 +00:00
Bruno Cardoso Lopes
72ca75e10f Move the last piece of SSE2 convert instructions to the Convert Instructions section 
llvm-svn: 106877
 2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
fc7bfafe52 More SSE refactoring, this time with different types of MOVs 
llvm-svn: 106876
 2010-06-25 20:22:12 +00:00
Bruno Cardoso Lopes
0db2df31f4 Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders 
llvm-svn: 106867
 2010-06-25 18:06:22 +00:00
Bruno Cardoso Lopes
bde2881855 Add some AVX convert instructions 
llvm-svn: 106815
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
4663112339 Refactoring of SSE convert intrinsics 
llvm-svn: 106808
 2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
bacc90a80d Refactoring of SSE conversion instructions 
llvm-svn: 106804
 2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes
84ce865fea Refactor SSE cmp intrinsics and declare the same for AVX 
llvm-svn: 106796
 2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes
11a236d970 - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787
 2010-06-24 20:48:23 +00:00
Bruno Cardoso Lopes
633f345ba9 Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases 
llvm-svn: 106705
 2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
5aea735b46 Move SSE and AVX shuffle, unpack and compare code to more appropriate places 
llvm-svn: 106702
 2010-06-24 00:15:50 +00:00
Bruno Cardoso Lopes
b1bfbacead Add AVX MOVMSK{PS,PD}rr instructions 
llvm-svn: 106683
 2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
8cfdcf7691 Add AVX SHUF{PS,PD}{rr,rm} instructions 
llvm-svn: 106672
 2010-06-23 20:07:15 +00:00
Bruno Cardoso Lopes
db9027d95d Add AVX compare packed instructions 
llvm-svn: 106600
 2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
424b206ad4 Reapply support for AVX unpack and interleave instructions, with 
testcases this time.

llvm-svn: 106593
 2010-06-22 23:02:38 +00:00