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Author SHA1 Message Date
Kalle Raiskila
2001fd19b9 Mark the SPU 'lr' instruction to never have side effects. 
This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 

llvm-svn: 106420
 2010-06-21 15:08:16 +00:00
Kalle Raiskila
cbd0b7c43b Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats. 
llvm-svn: 106419
 2010-06-21 14:42:19 +00:00
Dan Gohman
b1b8a3a73a Do one lookup instead of two. 
llvm-svn: 106415
 2010-06-21 14:21:47 +00:00
Dan Gohman
408c991311 Generalize this to look in the regular ValueMap in addition to 
the LocalValueMap, to make it more flexible when fast-isel isn't
proceding straight top-down.

llvm-svn: 106414
 2010-06-21 14:17:46 +00:00
Rafael Espindola
5e123a1745 Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch. 
I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.

llvm-svn: 106413
 2010-06-21 13:31:32 +00:00
Kalle Raiskila
a30e45e2d3 Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm 
used to choke llc with the attached test.
 

llvm-svn: 106411
 2010-06-21 10:17:36 +00:00
Rafael Espindola
705c2bd4c3 add_input_file and add_input_library now take const arguments, remove the 
const_cast.

llvm-svn: 106410
 2010-06-21 02:23:12 +00:00
Rafael Espindola
cf8f391d49 Save more temps with -save-temps. 
llvm-svn: 106409
 2010-06-21 02:17:36 +00:00
Rafael Espindola
84260ed15a wip 
llvm-svn: 106408
 2010-06-21 02:17:34 +00:00
Nate Begeman
8a4ebbc2a6 Add support for returning multiple vectors via sret, which is how the ARM target expects the intrinsics to work. 
llvm-svn: 106406
 2010-06-20 21:09:52 +00:00
Nick Lewycky
059e327790 Fix warning in no-asserts build. 
llvm-svn: 106405
 2010-06-20 20:27:42 +00:00
Evan Cheng
c18fbafa74 Fix a crash caused by dereference of MBB.end(). rdar://8110842 
llvm-svn: 106399
 2010-06-20 00:54:38 +00:00
Dan Gohman
90c5f8753d Restore a call to rememberInstruction which was accidentally dropped 
in refactoring.

llvm-svn: 106398
 2010-06-19 22:50:35 +00:00
Dan Gohman
565876f980 Add a TODO comment. 
llvm-svn: 106397
 2010-06-19 21:30:18 +00:00
Dan Gohman
fcb0f1936b Include the use kind along with the expression in the key of the 
use sharing map. The reconcileNewOffset logic already forces a
separate use if the kinds differ, so incorporating the kind in the
key means we can track more sharing opportunities.

More sharing means fewer total uses to track, which means smaller
problem sizes, which means the conservative throttles don't kick
in as often.

llvm-svn: 106396
 2010-06-19 21:29:59 +00:00
Dan Gohman
5d3629eaa0 Don't include things in anonymous namespaces that don't need it. 
llvm-svn: 106395
 2010-06-19 21:21:39 +00:00
Benjamin Kramer
5d4a43151c Use calloc instead of new/memset, it is more efficient when the set is very large. 
llvm-svn: 106390
 2010-06-19 17:00:31 +00:00
Dan Gohman
cec5b682b6 Fix ScalarEvolution's "exhaustive" trip count evaluation code to avoid 
assuming that loops are in canonical form, as ScalarEvolution doesn't
depend on LoopSimplify itself. Also, with indirectbr not all loops can
be simplified. This fixes PR7416.

llvm-svn: 106389
 2010-06-19 14:17:24 +00:00
Dan Gohman
fb091c213b Factor out duplicated code for reusing and inserting casts into 
a helper function.

llvm-svn: 106388
 2010-06-19 13:25:23 +00:00
Bob Wilson
c4a6a42c20 Tidy. 
llvm-svn: 106383
 2010-06-19 05:33:57 +00:00
Bob Wilson
059880161b Remove a fixme comment that is no longer relevant. 
llvm-svn: 106382
 2010-06-19 05:32:41 +00:00
Bob Wilson
44afe2065d Fix error message to match function name. 
llvm-svn: 106381
 2010-06-19 05:32:09 +00:00
Bruno Cardoso Lopes
0403eaadce Refactoring of regular logical packed instructions to prepare for AVX ones. 
llvm-svn: 106375
 2010-06-19 04:09:22 +00:00
Bruno Cardoso Lopes
c41dfa7cad Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

llvm-svn: 106374
 2010-06-19 02:44:01 +00:00
Evan Cheng
142feca0de Ignore dbg_value's. 
llvm-svn: 106373
 2010-06-19 02:36:21 +00:00
Bruno Cardoso Lopes
4e76c6a522 Move new sse 1 & 2 generic classes to a more appropriate place 
llvm-svn: 106372
 2010-06-19 01:32:46 +00:00
Bruno Cardoso Lopes
962d79ed72 Remove unnecessary arguments 
llvm-svn: 106371
 2010-06-19 01:22:34 +00:00
Bruno Cardoso Lopes
2ca4dde535 Add AVX packed intrinsics for MIN, MAX 
llvm-svn: 106370
 2010-06-19 01:17:05 +00:00
Evan Cheng
f40b8f0e32 Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 
llvm-svn: 106368
 2010-06-19 01:01:32 +00:00
Eric Christopher
b6dfc01862 Finish ripping isTwoAddress out of X86. Some mindless formatting 
and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.

llvm-svn: 106367
 2010-06-19 00:37:40 +00:00
Bruno Cardoso Lopes
d6d12f37c6 Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
llvm-svn: 106366
 2010-06-19 00:37:31 +00:00
Chris Lattner
def4def8f9 rip out dead code. 
llvm-svn: 106365
 2010-06-19 00:34:14 +00:00
Chris Lattner
ed5a217085 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00
Evan Cheng
604fd85b52 Indentation and remove dead code. 
llvm-svn: 106362
 2010-06-19 00:11:54 +00:00
Bruno Cardoso Lopes
018fd49970 Clean up: remove now unnecessary Constraints 
llvm-svn: 106361
 2010-06-19 00:09:27 +00:00
Dan Gohman
8f0bc55ea5 Silence compiler warnings. 
llvm-svn: 106360
 2010-06-19 00:02:06 +00:00
Bruno Cardoso Lopes
c016e11c53 more refactoring! yay! big win over the intrinsics 
llvm-svn: 106359
 2010-06-19 00:00:22 +00:00
Eric Christopher
e0cc8e131e Remove isTwoAddress from here too. 
llvm-svn: 106358
 2010-06-18 23:56:07 +00:00
Bruno Cardoso Lopes
5af812b35b Fix typo, SSE1 should be used by XS, not SSE2 
llvm-svn: 106357
 2010-06-18 23:53:27 +00:00
Eric Christopher
10fa91df80 Remove isTwoAddress from 64-bit files. 
llvm-svn: 106356
 2010-06-18 23:51:21 +00:00
Evan Cheng
e9ba3241a3 Move ARM if-conversion before post-ra scheduling. 
llvm-svn: 106355
 2010-06-18 23:32:07 +00:00
Dan Gohman
823dff64cd Teach regular and fast isel to set dead flags on unused implicit defs 
on calls and similar instructions.

llvm-svn: 106353
 2010-06-18 23:28:01 +00:00
Bruno Cardoso Lopes
ec4b18a1cf Apply some refactor to packed instructions 
llvm-svn: 106349
 2010-06-18 23:13:35 +00:00
Evan Cheng
5e2c36c202 Update cmake list. 
llvm-svn: 106348
 2010-06-18 23:12:10 +00:00
Evan Cheng
f776ed836b Thumb2 hazard recognizer. 
llvm-svn: 106347
 2010-06-18 23:11:35 +00:00
Jakob Stoklund Olesen
7150b84292 Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean up 
the inserted INSERT_SUBREGs after us.

llvm-svn: 106345
 2010-06-18 23:10:20 +00:00
Evan Cheng
b5fadc47e0 Allow ARM if-converter to be run after post allocation scheduling. 
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344
 2010-06-18 23:09:54 +00:00
Jim Grosbach
b8c94667a8 back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set) 
llvm-svn: 106342
 2010-06-18 23:03:10 +00:00
Eric Christopher
b04dbfd059 Another typo. 
llvm-svn: 106340
 2010-06-18 22:51:25 +00:00
Jim Grosbach
c599143b45 Enable Expand handling of atomics for subtargets that can't do them inline. 
llvm-svn: 106336
 2010-06-18 22:35:32 +00:00