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933 Commits

Author SHA1 Message Date
Dan Gohman
3b99b3c807 Treat EntryToken nodes as "passive" so that they aren't added to the 
ScheduleDAG; they don't correspond to any actual instructions so they
don't need to be scheduled.

This fixes a bug where the EntryToken was being scheduled multiple
times in some cases, though it ended up not causing any trouble because 
EntryToken doesn't expand into anything. With this fixed the schedulers
reliably schedule the expected number of units, so we can check this
with an assertion.

This requires a tweak to test/CodeGen/X86/loop-hoist.ll because it
ends up getting scheduled differently in a trivial way, though it was
enough to fool the prcontext+grep that the test does.

llvm-svn: 49701
 2008-04-15 01:22:18 +00:00
Dan Gohman
cce2b42edc Upgrade these tests for the current intrinsic prototypes. 
llvm-svn: 49669
 2008-04-14 18:19:18 +00:00
Dale Johannesen
d9a9c746d8 Remove -unwind-tables-optional everywhere, since 
this is now the default.

llvm-svn: 49667
 2008-04-14 17:56:54 +00:00
Arnold Schwaighofer
82af0e6a43 This patch corrects the handling of byval arguments for tailcall 
optimized x86-64 (and x86) calls so that they work (... at least for
my test cases).

Should fix the following problems:

Problem 1: When i introduced the optimized handling of arguments for
tail called functions (using a sequence of copyto/copyfrom virtual
registers instead of always lowering to top of the stack) i did not
handle byval arguments correctly e.g they did not work at all :).

Problem 2: On x86-64 after the arguments of the tail called function
are moved to their registers (which include ESI/RSI etc), tail call
optimization performs byval lowering which causes xSI,xDI, xCX
registers to be overwritten. This is handled in this patch by moving
the arguments to virtual registers first and after the byval lowering
the arguments are moved from those virtual registers back to
RSI/RDI/RCX.

llvm-svn: 49584
 2008-04-12 18:11:06 +00:00
Dan Gohman
15edbf989f Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal 
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.

llvm-svn: 49572
 2008-04-12 04:36:06 +00:00
Dan Gohman
41f9d24d52 Fix a bug that prevented x86-64 from using rep.movsq for 
8-byte-aligned data.

llvm-svn: 49571
 2008-04-12 02:35:39 +00:00
Evan Cheng
6e52146f16 If a PHI node has a single implicit_def source, replace it with an implicit_def instead of a copy. 
llvm-svn: 49543
 2008-04-11 17:54:45 +00:00
Evan Cheng
56ca7e285a New test. 
llvm-svn: 49514
 2008-04-10 23:49:09 +00:00
Evan Cheng
6f164e3814 A copy instruction may use a register multiple times on some targets. Change them all. 
llvm-svn: 49491
 2008-04-10 18:38:47 +00:00
Chris Lattner
3b289289a7 Fix the x86-64 side of PR2108 by adding a v2f64 version of 
MOVZQI2PQIrr.  This would be better handled as a dag combine 
(with the goal of eliminating the bitconvert) but I don't know
how to do that safely.  Thoughts welcome.

llvm-svn: 49463
 2008-04-10 05:13:43 +00:00
Evan Cheng
1803e20a62 Teach branch folding pass about implicit_def instructions. Unfortunately we can't just eliminate them since register scavenger expects every register use to be defined. However, we can delete them when there are no intra-block uses. Carefully removing some implicit def's which enable more blocks to be optimized away. 
llvm-svn: 49461
 2008-04-10 02:32:10 +00:00
Evan Cheng
def576f9e6 - More aggressively coalescing away copies whose source is defined by an implicit_def. 
- Added insert_subreg coalescing support.

llvm-svn: 49448
 2008-04-09 20:57:25 +00:00
Evan Cheng
f35cc57821 Missed a hasInterval check. 
llvm-svn: 49415
 2008-04-09 01:30:15 +00:00
Dale Johannesen
5ac0a0ed21 Rename -disable-required-unwind-tables to -unwind-tables-optional. 
llvm-svn: 49391
 2008-04-08 18:10:08 +00:00
Dale Johannesen
576a7685f2 Missed one. 
llvm-svn: 49365
 2008-04-08 00:14:59 +00:00
Dale Johannesen
3f992b224e Add -disable-required-unwind-tables to tests 
that need it (usually, grepping for some string
found in unwind info)

llvm-svn: 49364
 2008-04-08 00:14:17 +00:00
Evan Cheng
6c58f2397d Fix test. 
llvm-svn: 49343
 2008-04-07 17:02:18 +00:00
Chris Lattner
f88214caca fix this testcase to pass and remove a duplicate instance of itself. 
llvm-svn: 49281
 2008-04-06 21:39:17 +00:00
Torok Edwin
34e6889671 Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. 
If it cannot be expanded, it will keep the old behaviour and try to shrink the constant.
Part of enhancement for PR2191.

llvm-svn: 49280
 2008-04-06 21:23:02 +00:00
Evan Cheng
d7d1c94e67 1. IMPLICIT_DEF can *re-define* any register. 
2. Coalescer can now create an interesting situation where a register def can
   reaches itself without being killed.

llvm-svn: 49246
 2008-04-05 01:27:09 +00:00
Evan Cheng
4d7b2ab16f Favors pshufd over shufps when shuffling elements from one vector. pshufd is faster than shufps. 
llvm-svn: 49244
 2008-04-05 00:30:36 +00:00
Evan Cheng
f045d86660 New test case. 
llvm-svn: 49190
 2008-04-03 21:25:03 +00:00
Dale Johannesen
ebfa6edc65 Testcase for EH with functions whose names are stripped. 
llvm-svn: 49111
 2008-04-02 20:16:41 +00:00
Dan Gohman
168b2b1300 Speculatively micro-optimize memory-zeroing calls on Darwin 10. 
llvm-svn: 49048
 2008-04-01 20:38:36 +00:00
Evan Cheng
c2f298f318 More soft fp fixes. 
llvm-svn: 49016
 2008-04-01 02:18:22 +00:00
Evan Cheng
a38ae9c502 Unbreak ARM / Thumb soft FP support. 
llvm-svn: 49012
 2008-04-01 01:50:16 +00:00
Dale Johannesen
d9a5b77269 Mark functions in some tests as 'nounwind'. Generating 
EH info for these functions causes the tests to fail for
random reasons (e.g. looking for 'or' or counting lines
with asm-printer; labels count as lines.)

llvm-svn: 49003
 2008-03-31 23:20:09 +00:00
Evan Cheng
a3ce7b4c76 It's not safe to fold a load from GV stub or constantpool into a two-address use. 
llvm-svn: 49002
 2008-03-31 23:19:51 +00:00
Dan Gohman
f223eaafcd Fix a DAGCombiner optimization to respect volatile qualification. 
llvm-svn: 48994
 2008-03-31 20:32:52 +00:00
Dan Gohman
227e702cae Fix a tokenfactor node to use the load chain rather than the 
load value. This fixes PR2177.

llvm-svn: 48932
 2008-03-28 23:45:16 +00:00
Evan Cheng
6cbce6b602 Fix a memory bug: increment an iterator of a deleted machine instr. 
llvm-svn: 48853
 2008-03-27 01:27:25 +00:00
Evan Cheng
6fc37c8f25 One more coalescer fix wrt deadness propagation. 
llvm-svn: 48837
 2008-03-26 20:15:49 +00:00
Evan Cheng
8d222d6221 Avoid commuting a def MI in order to coalesce a copy instruction away if any use of the same val# is a copy instruction that has already been coalesced. 
llvm-svn: 48833
 2008-03-26 19:03:01 +00:00
Dale Johannesen
8c1e95810f Use ## for comment delimiter on darwin x86-32, so 
llvm's output .s files will go through gcc -std=c99
without triggering preprocesser errors.  Approach
suggested by Daveed Vandevoorde.

llvm-svn: 48808
 2008-03-25 23:29:30 +00:00
Evan Cheng
8cb64d8e8b Handle a special case xor undef, undef -> 0. Technically this should be transformed to undef. But this is such a common idiom (misuse) we are going to handle it. 
llvm-svn: 48792
 2008-03-25 20:08:07 +00:00
Dan Gohman
58ad056286 Add CMP32mr and friends to the load-unfolding table. Among 
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.

llvm-svn: 48777
 2008-03-25 16:53:19 +00:00
Tanya Lattner
b6a27ed83f Byebye llvm-upgrade! 
llvm-svn: 48762
 2008-03-25 04:26:08 +00:00
Evan Cheng
7c1dcd8371 lastRegisterUse() should ignore identity copies. Those will be erased. 
llvm-svn: 48759
 2008-03-25 02:02:19 +00:00
Bill Wendling
2097b72649 Use the bit size of the operand instead of the hard-coded 32 to generate the 
mask.

llvm-svn: 48750
 2008-03-24 23:16:37 +00:00
Evan Cheng
dbdf48276a - SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction. 
llvm-svn: 48746
 2008-03-24 21:52:23 +00:00
Dan Gohman
b9c5e6258f APIntify SelectionDAG's EXTRACT_ELEMENT code. 
llvm-svn: 48726
 2008-03-24 16:38:05 +00:00
Bill Wendling
f607f27320 New testcase. 
llvm-svn: 48697
 2008-03-22 22:27:01 +00:00
Evan Cheng
874aee2eec Teach DAG combiner to commute commutable binary nodes in order to achieve sdisel CSE. 
llvm-svn: 48673
 2008-03-22 01:55:50 +00:00
Dan Gohman
59aeac6320 Handle getresult instructions in different basic blocks 
from their aggregate operands by moving the getresult
instructions.

llvm-svn: 48657
 2008-03-21 21:01:32 +00:00
Chris Lattner
8a4fa95cae Add support for calls that return two FP values in 
ST(0)/ST(1).

llvm-svn: 48634
 2008-03-21 06:38:26 +00:00
Chris Lattner
933d0d318b disable a bogus assertion. 
llvm-svn: 48633
 2008-03-21 06:01:05 +00:00
Chris Lattner
260473f983 Enable support for returning two long-double values in ST(0)/ST(1). 
This allows us to compile fp-stack-2results.ll into:

_test:
	fldz
	fld1
	ret

which returns 1 in ST(0) and 0 in ST(1).  This is needed for x86-64
_Complex long double.

llvm-svn: 48632
 2008-03-21 05:57:20 +00:00
Evan Cheng
4ae9fee64c Undo 48570. Correctly match mmx shift instructions with an immediate operand. 
llvm-svn: 48627
 2008-03-21 00:40:09 +00:00
Evan Cheng
8ecb189245 Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m))) 
llvm-svn: 48578
 2008-03-20 02:18:41 +00:00
Scott Michel
e747d20130 Add more patterns to match in the integer comparison test harnesses. 
Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.

llvm-svn: 48575
 2008-03-20 00:51:36 +00:00
Evan Cheng
6f729b2820 Add intrinsics to match mmx shift builtin's with immediate operand. 
llvm-svn: 48569
 2008-03-19 23:38:52 +00:00
Dan Gohman
c9dec33f3f Add support for multiple return values for the PPC target by 
converting call result lowering to use the CallingConvLowering
infastructure.

llvm-svn: 48552
 2008-03-19 21:39:28 +00:00
Christopher Lamb
958b0494c3 Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491. 
llvm-svn: 48542
 2008-03-19 08:30:06 +00:00
Evan Cheng
e9aa507edc Fixed a coalescer bug caused by a typo. 
llvm-svn: 48526
 2008-03-19 02:26:36 +00:00
Evan Cheng
3d9309c11d Fix live variables issues: 
1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue.
2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register:
   = EAX, AX<imp-use,kill>
...
AX =
In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things.

llvm-svn: 48521
 2008-03-19 00:52:20 +00:00
Evan Cheng
5ac87b837e Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it! 
llvm-svn: 48515
 2008-03-18 23:36:35 +00:00
Bill Wendling
c8f3fc7c3d It might be nice to have this run as x86 on non-x86 platforms... 
llvm-svn: 48511
 2008-03-18 22:38:22 +00:00
Bill Wendling
5ea2aec3ac Temporarily revert r48491. It's breaking test/CodeGen/X86/xorl.ll. 
llvm-svn: 48510
 2008-03-18 22:29:51 +00:00
Dale Johannesen
7f51ebc90c Make conversions of i8/i16 to ppcf128 work. 
llvm-svn: 48493
 2008-03-18 17:28:38 +00:00
Christopher Lamb
1d70509b55 Target independent DAG transform to use truncate for field extraction + sign extend on targets where this is profitable. Passes nightly on x86-64. 
llvm-svn: 48491
 2008-03-18 16:46:39 +00:00
Evan Cheng
5750c3cd1e Rewrite code that propagate isDead information after a dead copy is coalesced. This remove some ugly spaghetti code and fixed a number of subtle bugs. 
llvm-svn: 48490
 2008-03-18 08:26:47 +00:00
Chris Lattner
bb335409c2 ensure we continue matching x86-64 rotates. 
llvm-svn: 48437
 2008-03-17 01:35:03 +00:00
Evan Cheng
3612a7ed30 Fix PR2138. Apparently any modification to a std::multimap (including remove entries for a different key) can invalidate multimap iterators. 
llvm-svn: 48371
 2008-03-14 20:44:01 +00:00
Dan Gohman
486f664806 More APInt-ification. 
llvm-svn: 48344
 2008-03-13 22:13:53 +00:00
Evan Cheng
53c3dd0267 New test case. 
llvm-svn: 48338
 2008-03-13 08:05:02 +00:00
Evan Cheng
a76bb6e64e A test case I forgot to check in. 
llvm-svn: 48335
 2008-03-13 06:42:46 +00:00
Evan Cheng
0b8b1647dd TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one. 
llvm-svn: 48333
 2008-03-13 06:37:55 +00:00
Evan Cheng
620fd19798 Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: 
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!

llvm-svn: 48307
 2008-03-12 22:19:41 +00:00
Dan Gohman
2ec41788ab Fix this test on hosts that don't have sse2. 
llvm-svn: 48296
 2008-03-12 20:40:51 +00:00
Dan Gohman
2a124430e9 Make this test x86-specific for now; targets that don't use 
the automated CallingConv code to handle return values typically
don't support multiple return values.

llvm-svn: 48265
 2008-03-12 00:25:14 +00:00
Dan Gohman
155ffdd955 Basic feature test for multiple return values in codegen. 
llvm-svn: 48260
 2008-03-11 23:53:16 +00:00
Anton Korobeynikov
d2fd135594 Testcase for PR2137 
llvm-svn: 48258
 2008-03-11 22:43:42 +00:00
Anton Korobeynikov
efa9405b94 Update testcase for recent aliases change 
llvm-svn: 48250
 2008-03-11 21:42:20 +00:00
Dan Gohman
f9f25bd41b Add a test to ensure that all-ones vectors are materialized with pcmpeqd. 
llvm-svn: 48247
 2008-03-11 21:37:00 +00:00
Dan Gohman
1fece90de9 Use the correct value for InSignBit. 
llvm-svn: 48245
 2008-03-11 21:29:43 +00:00
Chris Lattner
fd2c24af72 Implement basic support for the 'f' register class constraint. This basically 
works, but probably won't if you mix it with 't' or 'u' yet.

llvm-svn: 48243
 2008-03-11 19:50:13 +00:00
Dale Johannesen
c03216ac3e The feature this is testing did not work in the general case, 
and has been removed.

llvm-svn: 48232
 2008-03-11 17:48:26 +00:00
Evan Cheng
6a30fc4e94 Learn how to xfail a test. 
llvm-svn: 48219
 2008-03-11 07:51:31 +00:00
Evan Cheng
af1c76846d When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. 
llvm-svn: 48218
 2008-03-11 07:19:34 +00:00
Evan Cheng
9ae65a13c3 XFAIL due to Dale's change. 
llvm-svn: 48216
 2008-03-11 07:15:44 +00:00
Dan Gohman
85bfbe2293 Generalize ExpandIntToFP to handle the case where the operand is legal 
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 

llvm-svn: 48206
 2008-03-11 01:59:03 +00:00
Scott Michel
599ff689d0 - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency. 
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.

llvm-svn: 48197
 2008-03-10 23:49:09 +00:00
Chris Lattner
f0684bfd16 Don't emit FP_REG_KILL into a block that just returns. Nothing 
can be live out of the block anyway, so it isn't needed.

llvm-svn: 48192
 2008-03-10 23:34:12 +00:00
Dan Gohman
67aed9bbb0 Implement more support for fp-to-i128 and i128-to-fp conversions. 
llvm-svn: 48189
 2008-03-10 23:03:31 +00:00
Bill Wendling
8e3a4a45ce Update llc flags for PPC register scavenger. 
llvm-svn: 48187
 2008-03-10 22:59:08 +00:00
Dan Gohman
47137eba06 Fix mul expansion to check the correct number of bits for 
zero extension when checking if an unsigned multiply is
safe.

llvm-svn: 48171
 2008-03-10 20:42:19 +00:00
Dale Johannesen
62a0b6a79b These tests don't work unless SSE2 is active. 
Judging from the checking comments this is intentional,
so add the flag (makes them pass on non-x86 host).

llvm-svn: 48157
 2008-03-10 17:33:57 +00:00
Dale Johannesen
c9ecee85c4 There is no "-mattr=+sse1" flag; fix test for non-x86 hosts. 
llvm-svn: 48156
 2008-03-10 17:13:37 +00:00
Scott Michel
38f8a1043a Integer comparison tests for CellSPU. 
llvm-svn: 48152
 2008-03-10 16:58:52 +00:00
Evan Cheng
02b66c3a32 - Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where the source is defined; BLR is the live range which is defined by the copy. 
If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.                                                                                                 
 A = or A, B                                                                                                                                                            
 ...                                                                                                                                                                    
 B = A                                                                                                                                                                  
 ...                                                                                                                                                                    
 C = A<kill>                                                                                                                                                            
 ...                                                                                                                                                                    
   = B                                                                                                                                                                  
                                                                                                                                                                        
then do not add kills of A to the newly created B interval.
- Also fix some kill info update bug.

llvm-svn: 48141
 2008-03-10 08:11:32 +00:00
Evan Cheng
3c0ddc999f Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case. 
llvm-svn: 48136
 2008-03-10 07:19:13 +00:00
Chris Lattner
95a37b6592 remove an execution test. 
llvm-svn: 48135
 2008-03-10 06:53:14 +00:00
Evan Cheng
53424806b1 Fix RUN line. 
llvm-svn: 48116
 2008-03-09 19:55:22 +00:00
Chris Lattner
b6bfedbcfd teach X86InstrInfo::copyRegToReg how to copy into ST(0) from 
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.

llvm-svn: 48107
 2008-03-09 09:15:31 +00:00
Chris Lattner
8d0203478f Add ScheduleDAG support for copytoreg where the src/dst register are 
in different register classes, e.g. copy of ST(0) to RFP*.  This gets
some really trivial inline asm working that plops things on the top of
stack (PR879)

llvm-svn: 48105
 2008-03-09 08:49:15 +00:00
Tanya Lattner
9aa573954c Remove llvm-upgrade and update tests. 
llvm-svn: 48103
 2008-03-09 08:16:40 +00:00
Chris Lattner
b9a4c86fbf reduce this testcase more 
llvm-svn: 48092
 2008-03-09 06:57:21 +00:00
Chris Lattner
b628208161 Finish implementing a readme entry: when inserting an i64 variable 
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48090
 2008-03-09 05:42:06 +00:00
Chris Lattner
17f68a3075 Implement a readme entry, compiling 
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.

llvm-svn: 48063
 2008-03-09 01:05:04 +00:00
Chris Lattner
1b16dc4a6e upgrade this test 
llvm-svn: 48062
 2008-03-09 00:32:10 +00:00
Chris Lattner
24031c9426 make this test harder 
llvm-svn: 48061
 2008-03-09 00:30:06 +00:00
Chris Lattner
7173d3bd70 Teach SD some vector identities, allowing us to compile vec_set-9 into: 
_test3:
	movd	%rdi, %xmm1
	#IMPLICIT_DEF %xmm0
	punpcklqdq	%xmm1, %xmm0
	ret

instead of:

_test3:
	#IMPLICIT_DEF %rax
	movd	%rax, %xmm0
	movd	%rdi, %xmm1
	punpcklqdq	%xmm1, %xmm0
	ret

This is still not ideal.  There is no reason to two xmm regs.

llvm-svn: 48058
 2008-03-08 23:43:36 +00:00
Evan Cheng
dba1dfe962 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. 
llvm-svn: 48042
 2008-03-08 00:58:38 +00:00
Dan Gohman
afeac8050d Add support for calls with i128 return values on ppc64. 
llvm-svn: 48041
 2008-03-08 00:19:12 +00:00
Dan Gohman
5bf464e1e6 Add support for lowering 128-bit shifts on ppc64. 
llvm-svn: 48029
 2008-03-07 20:36:53 +00:00
Evan Cheng
5f74d1a8dc Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI. 
llvm-svn: 48024
 2008-03-07 20:12:54 +00:00
Chris Lattner
aa81dc7d21 mark frem as expand for all legal fp types on x86, regardless of whether 
we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006
 2008-03-07 06:36:32 +00:00
Bill Wendling
f0615bf090 Add testcase. 
llvm-svn: 48005
 2008-03-06 23:34:22 +00:00
Gabor Greif
92e00c1e50 some more spelling changes 
llvm-svn: 47996
 2008-03-06 10:51:21 +00:00
Evan Cheng
9c77211639 Constant fold SIGN_EXTEND_INREG with ashr not lshr. 
llvm-svn: 47992
 2008-03-06 08:20:51 +00:00
Scott Michel
8dd2324903 Refine Cell's i64 constant generation code to cover more constants where the 
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)

llvm-svn: 47985
 2008-03-06 04:02:54 +00:00
Scott Michel
3c19a3950c - Expand tabs to spaces. 
- select_bits.ll now fully functional now that PR1993 is closed. It was
  previously broken by refactoring in SPUInstrInfo.td and using multiclasses.
- Same for eqv.ll

llvm-svn: 47972
 2008-03-05 23:00:19 +00:00
Evan Cheng
8f5092bea8 Fix a coalescer bug wrt how dead copy interval is shortened. 
llvm-svn: 47966
 2008-03-05 22:09:42 +00:00
Chris Lattner
a9fcb187af Generalize FP constant shrinking optimization to apply to any vt 
except ppc long double.  This allows us to shrink constant pool
entries for x86 long double constants, which in turn allows us to
use flds/fldl instead of fldt.

llvm-svn: 47938
 2008-03-05 06:48:13 +00:00
Evan Cheng
e0b3c221ab Add a target lowering hook to control whether it's worthwhile to compress fp constant. 
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.

llvm-svn: 47931
 2008-03-05 01:30:59 +00:00
Bill Wendling
cf70f2c2a0 Use -enable-ppc-regscavenger flag for these checks 
llvm-svn: 47916
 2008-03-04 23:16:26 +00:00
Evan Cheng
14f556a6d7 Really fix the test. 
llvm-svn: 47882
 2008-03-04 08:01:56 +00:00
Evan Cheng
7a67175fcc Fix broken test. 
llvm-svn: 47881
 2008-03-04 07:59:13 +00:00
Evan Cheng
3123d6ced3 Add PR1501 test case. 
llvm-svn: 47874
 2008-03-04 00:47:45 +00:00
Bill Wendling
8d64999daf This is the initial check-in for adding register scavenging to PPC. (Currently, 
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.

llvm-svn: 47863
 2008-03-03 22:19:16 +00:00
Chris Lattner
299977b5ca Evan implemented these. 
llvm-svn: 47828
 2008-03-02 18:05:14 +00:00
Chris Lattner
4c67781884 Evan implemented this. 
llvm-svn: 47827
 2008-03-02 17:56:29 +00:00
Chris Lattner
7f3c8ea9bf add a testcase for misc vector stuff 
llvm-svn: 47826
 2008-03-02 08:57:59 +00:00
Bill Wendling
246237f14f DCE'ed this testcase. 
llvm-svn: 47760
 2008-02-29 19:28:11 +00:00
Bill Wendling
d0f85a5ca3 If we reload a virtual register that's already been assigned, we want to mark 
that instruction as its "last use". This fixes PR1925.

llvm-svn: 47758
 2008-02-29 18:52:01 +00:00
Lauro Ramos Venancio
15e03a8950 Update testcase. 
llvm-svn: 47735
 2008-02-28 23:13:15 +00:00
Evan Cheng
e1d3e0958b Set to default: x86 no longer fold and into test if it has more than one use. 
llvm-svn: 47711
 2008-02-28 07:46:38 +00:00
Dale Johannesen
7b8dae547d New test for misaligned Altivec laod/store. 
llvm-svn: 47698
 2008-02-27 23:14:50 +00:00
Dan Gohman
5d96a06b0b Don't hard-code the mask size to be 32, which is incorrect on ppc64 
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.

llvm-svn: 47692
 2008-02-27 21:12:32 +00:00
Evan Cheng
da92e34fe3 Fix a bug in dead spill slot elimination. 
llvm-svn: 47687
 2008-02-27 19:57:11 +00:00
Chris Lattner
e51c23341d actually run llc, thanks Dan :) 
llvm-svn: 47677
 2008-02-27 17:46:54 +00:00
Evan Cheng
295ae42ede Don't track max alignment during stack object allocations since they can be deleted later. Let PEI compute it. 
llvm-svn: 47668
 2008-02-27 10:04:56 +00:00
Chris Lattner
1f46cc2345 Make X86TargetLowering::LowerSINT_TO_FP return without creating a dead 
stack slot and store if the  SINT_TO_FP is actually legal.  This allows
us to compile:

double a(double b) {return (unsigned)b;}

to:

_a:
	cvttsd2siq	%xmm0, %rax
	movl	%eax, %eax
	cvtsi2sdq	%rax, %xmm0
	ret

instead of:

_a:
	subq	$8, %rsp
	cvttsd2siq	%xmm0, %rax
	movl	%eax, %eax
	cvtsi2sdq	%rax, %xmm0
	addq	$8, %rsp
	ret

crazy.

llvm-svn: 47660
 2008-02-27 05:57:41 +00:00
Chris Lattner
bc686e546a Compile x86-64-and-mask.ll into: 
_test:
	movl	%edi, %eax
	ret

instead of:

_test:
        movl    $4294967295, %ecx
        movq    %rdi, %rax
        andq    %rcx, %rax
        ret

It would be great to write this as a Pat pattern that used subregs 
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.

llvm-svn: 47658
 2008-02-27 05:47:54 +00:00
Evan Cheng
7553230e3a Spiller now remove unused spill slots. 
llvm-svn: 47657
 2008-02-27 03:04:06 +00:00
Bill Wendling
24932cf415 Upgrade testcase. 
llvm-svn: 47644
 2008-02-26 23:22:40 +00:00
Evan Cheng
701b6a1dc3 Enable -coalescer-commute-instrs by default. 
llvm-svn: 47623
 2008-02-26 20:40:22 +00:00
Dan Gohman
8a8f3fe7e0 Avoid aborting on invalid shift counts. 
llvm-svn: 47612
 2008-02-26 18:50:50 +00:00
Eli Friedman
1f2cabfbcf Fix for pr2093: direct operands aren't necessarily addresses, so don't 
try to simplify them.

llvm-svn: 47610
 2008-02-26 18:37:49 +00:00
Chris Lattner
1a461075ef Fix PR2096, a regression introduced with my patch last night. This 
also fixes cfrac, flops, and 175.vpr

llvm-svn: 47605
 2008-02-26 17:09:59 +00:00
Gabor Greif
a8990a9cac Really feed llvm-as with the testcase, do not let it read from stdin. This fixes the hangs seen on solaris10. 
llvm-svn: 47604
 2008-02-26 13:37:13 +00:00
Evan Cheng
8e99554e84 This is possible: 
vr1 = extract_subreg vr2, 3
...
vr3 = extract_subreg vr1, 2
The end result is vr3 is equal to vr2 with subidx 2.

llvm-svn: 47592
 2008-02-26 08:03:41 +00:00
Chris Lattner
5b4101cf68 Fix isNegatibleForFree to not return true for ConstantFP nodes 
after legalize.  Just because a constant is legal (e.g. 0.0 in SSE) 
doesn't mean that its negated value is legal (-0.0).  We could make
this stronger by checking to see if the negated constant is actually
legal post negation, but it doesn't seem like a big deal.

llvm-svn: 47591
 2008-02-26 07:04:54 +00:00
Evan Cheng
6366bbf577 Fix PR2076. CodeGenPrepare now sinks address computation for inline asm memory 
operands into inline asm block.

llvm-svn: 47589
 2008-02-26 02:42:37 +00:00
Scott Michel
36bbc39272 Merge current work back to tree to minimize diffs and drift. Major highlights 
for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

llvm-svn: 47532
 2008-02-23 18:41:37 +00:00
Evan Cheng
d299f09bc5 Rematerialization logic was overly conservative when it comes to loads from fixed stack slots. 
llvm-svn: 47529
 2008-02-23 03:38:34 +00:00
Evan Cheng
6782480bd1 Update test. 
llvm-svn: 47527
 2008-02-23 02:57:25 +00:00
Evan Cheng
4e9d5f1ead Remat of pic loads are now on by default. 
llvm-svn: 47525
 2008-02-23 02:08:30 +00:00
Evan Cheng
7c3a8d0056 Really. Why doesn't every arch support MMX? 
llvm-svn: 47513
 2008-02-23 00:56:14 +00:00
Evan Cheng
3b35d2a86c Test case for PR2082. 
llvm-svn: 47501
 2008-02-22 20:38:49 +00:00