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Author SHA1 Message Date
Jim Grosbach
6225a96bf5 Thumb2 assembly parsing and encoding for MLA and MLS. 
llvm-svn: 139399
 2011-09-09 20:24:45 +00:00
Duncan Sands
3311da4d79 Don't tack "Instruction not interpretable yet!" onto the end of 
the instruction.

llvm-svn: 139398
 2011-09-09 20:22:48 +00:00
Jim Grosbach
915ba5189e Thumb2 assembly parsing and encoding for LDRSB. 
llvm-svn: 139389
 2011-09-09 19:42:40 +00:00
Akira Hatanaka
17df2dfe8c Drop support for Allegrex. Allegrex implements a variant of Mips2. 
llvm-svn: 139383
 2011-09-09 19:00:51 +00:00
Jim Grosbach
eb2d668899 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
llvm-svn: 139381
 2011-09-09 18:37:27 +00:00
Jakob Stoklund Olesen
659d713274 Reapply r139247: Cache intermediate results during traceSiblingValue. 
In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs.  When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.

This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early.  This speeds up
spilling by 20x in one interpreter test case.  For more typical code,
this is just a 10% speedup of spilling.

The previous version had bugs that caused miscompilations. They have
been fixed.

llvm-svn: 139378
 2011-09-09 18:11:41 +00:00
Andrew Trick
77fa88a786 Comment formatting. 
llvm-svn: 139375
 2011-09-09 17:35:10 +00:00
Craig Topper
18cbd5db26 Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875. 
llvm-svn: 139353
 2011-09-09 05:40:53 +00:00
Akira Hatanaka
e1eb015eb9 Change default target architecture from Mips1 to Mips32r1 in preparation for 
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344
 2011-09-09 01:13:27 +00:00
Benjamin Kramer
da0ca686c9 Remove dead code. 
llvm-svn: 139343
 2011-09-09 00:22:05 +00:00
Nick Lewycky
ec5437bfc4 Fix release build: 
MachOObjectFile.cpp:524: error: unused variable 'NumLoadCommands' [-Wunused-variable]

llvm-svn: 139341
 2011-09-09 00:16:50 +00:00
Akira Hatanaka
94deb5f3f9 80 columns. 
llvm-svn: 139339
 2011-09-09 00:13:35 +00:00
Devang Patel
ba2d56b1ef Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. 
llvm-svn: 139330
 2011-09-08 22:59:09 +00:00
Owen Anderson
99ad1a853e All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. 
llvm-svn: 139329
 2011-09-08 22:48:37 +00:00
Owen Anderson
d7127e0c27 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
llvm-svn: 139328
 2011-09-08 22:42:49 +00:00
Eric Christopher
fc8e09962f Formatting and typo. 
llvm-svn: 139325
 2011-09-08 22:17:40 +00:00
Nadav Rotem
2f256b7f9f Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types. 
llvm-svn: 139324
 2011-09-08 22:17:35 +00:00
Jim Grosbach
9f150bfedf Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322
 2011-09-08 22:07:06 +00:00
Bruno Cardoso Lopes
54962ac233 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320
 2011-09-08 21:52:33 +00:00
Kevin Enderby
16f9df1f05 Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom 
without a base symbol that must not have a relocation entry.

llvm-svn: 139316
 2011-09-08 20:53:44 +00:00
Benjamin Kramer
3c40c2100b Add support for relocations to ObjectFile. 
Patch by Danil Malyshev!

llvm-svn: 139314
 2011-09-08 20:52:17 +00:00
Bruno Cardoso Lopes
2f07ca9728 * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a 
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Patch by David Meyer

llvm-svn: 139311
 2011-09-08 18:35:57 +00:00
Bruno Cardoso Lopes
74a67e22b0 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305
 2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
84c53e3965 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. 
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304
 2011-09-08 18:05:02 +00:00
Nadav Rotem
b461f2190e Add X86-SSE4 codegen support for vector-select. 
llvm-svn: 139285
 2011-09-08 08:11:19 +00:00
Eli Friedman
c933295353 A couple minor corrections to r139276. 
llvm-svn: 139277
 2011-09-08 02:37:07 +00:00
Eli Friedman
6e9cab83b0 Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881. 
llvm-svn: 139276
 2011-09-08 02:23:31 +00:00
Jim Grosbach
5ac3aa158b Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

llvm-svn: 139272
 2011-09-08 01:01:32 +00:00
Jim Grosbach
1aa191032a Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270
 2011-09-08 00:39:19 +00:00
Owen Anderson
4a5ec6836f Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. 
llvm-svn: 139268
 2011-09-08 00:11:18 +00:00
Jim Grosbach
8b54d19514 Thumb2 assembly parsing and encoding for LDRBT. 
llvm-svn: 139267
 2011-09-07 23:39:14 +00:00
Jim Grosbach
a3ff9eeb85 Thumb2 assembly parsing and encoding for LDR(register). 
llvm-svn: 139264
 2011-09-07 23:10:15 +00:00
Benjamin Kramer
f4e9cbfc05 Add two notes for correlated-expression optimizations. 
llvm-svn: 139263
 2011-09-07 22:49:26 +00:00
Jakob Stoklund Olesen
6853bdde5b Revert r139247 "Cache intermediate results during traceSiblingValue." 
It broke the self host and clang-x86_64-darwin10-RA.

llvm-svn: 139259
 2011-09-07 21:43:52 +00:00
Jim Grosbach
d640c62856 Thumb2 assembly parsing and encoding for LDRB(immediate). 
llvm-svn: 139258
 2011-09-07 21:41:25 +00:00
Owen Anderson
26467730c1 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
llvm-svn: 139256
 2011-09-07 21:10:42 +00:00
Jim Grosbach
20642fb479 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254
 2011-09-07 20:58:57 +00:00
Jim Grosbach
054b346e46 Thumb2 parsing and encoding for LDMDB. 
llvm-svn: 139251
 2011-09-07 19:57:53 +00:00
James Molloy
ac057f13a5 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
llvm-svn: 139250
 2011-09-07 19:42:28 +00:00
Jakob Stoklund Olesen
46444bd655 Cache intermediate results during traceSiblingValue. 
In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs.  When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.

This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early.  This speeds up
spilling by 20x in one interpreter test case.  For more typical code,
this is just a 10% speedup of spilling.

llvm-svn: 139247
 2011-09-07 19:07:31 +00:00
Eli Friedman
9ea5599729 Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()). 
This isn't exactly ideal, but it is good enough for the moment.

llvm-svn: 139245
 2011-09-07 18:48:32 +00:00
Jim Grosbach
bd018fd94f Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix. 
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.

llvm-svn: 139243
 2011-09-07 18:39:47 +00:00
Jim Grosbach
20689d28e7 Thumb2 parsing and encoding for LDMIA. 
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

llvm-svn: 139242
 2011-09-07 18:05:34 +00:00
Owen Anderson
4106b9fb31 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
llvm-svn: 139240
 2011-09-07 17:55:19 +00:00
James Molloy
f781d3d8e9 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
llvm-svn: 139237
 2011-09-07 17:24:38 +00:00
Jim Grosbach
c0ebdea61f Thumb2 use 'ldm' as default mnemonic. 
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).

llvm-svn: 139234
 2011-09-07 16:22:42 +00:00
Rafael Espindola
1cca4f99bd Detect attempt to use segmented stacks on non ELF systems and error 
(not assert) early.

llvm-svn: 139233
 2011-09-07 16:10:57 +00:00
Jim Grosbach
7969f880c0 Better diagnostic location information for mnemonic suffices. 
llvm-svn: 139232
 2011-09-07 16:06:04 +00:00
Eli Friedman
6a45370c0f Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM. 
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)

llvm-svn: 139221
 2011-09-07 02:23:42 +00:00
Devang Patel
f4483238b6 While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor. 
llvm-svn: 139208
 2011-09-07 00:07:58 +00:00
Bill Wendling
763ed58408 Reenable compact unwind by default. However, also emit the old version of unwind 
information for older linkers.

llvm-svn: 139206
 2011-09-06 23:47:14 +00:00
Owen Anderson
9ae90800a2 memset_pattern16 uses a 16 BYTE pattern, not a 16 BIT pattern. Add comments to that effect. 
llvm-svn: 139205
 2011-09-06 23:43:26 +00:00
Owen Anderson
483f94e8d1 Teach BasicAA about the aliasing properties of memset_pattern16. 
Fixes PR10872 and <rdar://problem/10065079>.

llvm-svn: 139204
 2011-09-06 23:33:25 +00:00
Jim Grosbach
2b87e14298 ISB is HasDB, not just HasV7. 
llvm-svn: 139202
 2011-09-06 23:09:19 +00:00
Jim Grosbach
14720bed32 Thumb2 parsing and encoding for ISB. 
llvm-svn: 139200
 2011-09-06 22:53:27 +00:00
Jim Grosbach
276e51888c Thumb2 parsing and encoding for DMB. 
llvm-svn: 139193
 2011-09-06 22:14:58 +00:00
Jim Grosbach
c0aaa747a1 Thumb2 parsing and encoding for DBG. 
llvm-svn: 139191
 2011-09-06 22:06:40 +00:00
Jim Grosbach
4258d5ffba Thumb2 parsing and encoding for CMN and CMP. 
llvm-svn: 139188
 2011-09-06 21:44:58 +00:00
Nick Lewycky
8203bcfd03 This transform only handles two-operand AddRec's. Prevent it from trying to 
handle anything more complex. Fixes PR10383 again!

llvm-svn: 139186
 2011-09-06 21:42:18 +00:00
Eli Friedman
33a078523a Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions. 
llvm-svn: 139179
 2011-09-06 20:53:37 +00:00
Jim Grosbach
b5dcc965a7 Thumb2 parsing and encoding for CLREX. 
llvm-svn: 139172
 2011-09-06 20:27:04 +00:00
Andrew Trick
8145f71bab Add -verify-indvars for imperfect SCEV trip count verification after indvars. 
llvm-svn: 139169
 2011-09-06 20:20:38 +00:00
Rafael Espindola
9182560b8f Fix comment. Noticed by Duncan. 
llvm-svn: 139161
 2011-09-06 19:29:31 +00:00
Duncan Sands
d1311488fe Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
 2011-09-06 19:07:46 +00:00
Evan Cheng
891e9696ea Fix fall outs from my recent change on how carry bit is modeled during isel. 
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745

llvm-svn: 139157
 2011-09-06 18:52:20 +00:00
Devang Patel
1366637777 Use IRBuilder. 
llvm-svn: 139156
 2011-09-06 18:49:53 +00:00
Jim Grosbach
86c318e475 ARM .code directive should always go to the streamer. 
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

llvm-svn: 139155
 2011-09-06 18:46:23 +00:00
Rafael Espindola
9d9df4bc1a Fix style issues and typos found by Duncan. 
llvm-svn: 139154
 2011-09-06 18:43:08 +00:00
Bill Wendling
32608b1900 As a first step, emit both the compact unwind and CIE/FDEs for a function. 
llvm-svn: 139152
 2011-09-06 18:37:11 +00:00
Owen Anderson
ca0326a423 Try again at r138809 (make DSE more aggressive in removing dead stores at the end of a function), now with less deleting stores before memcpy's. 
llvm-svn: 139150
 2011-09-06 18:14:09 +00:00
Jakob Stoklund Olesen
7994269719 Atomic pseudos don't use (as in read) CPSR. They clobber it. 
llvm-svn: 139148
 2011-09-06 17:40:35 +00:00
Devang Patel
2c2dd9114e Now, named mdnode llvm.dbg.cu keeps track of all compile units in a module. Update DebugInfoFinder to collect compile units from llvm.dbg.cu. 
llvm-svn: 139147
 2011-09-06 17:40:08 +00:00
Duncan Sands
6939ae53ac Split the init.trampoline intrinsic, which currently combines GCC's 
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140
 2011-09-06 13:37:06 +00:00
Nick Lewycky
e1c0b41d41 Fix typo in comment again. 
llvm-svn: 139139
 2011-09-06 07:02:40 +00:00
Nick Lewycky
700f71a0ac Apparently we compile the code, not the comments. Thanks Eli! 
llvm-svn: 139138
 2011-09-06 06:56:00 +00:00
Nick Lewycky
4add6eec38 Fix typo in comment. 
llvm-svn: 139137
 2011-09-06 06:46:01 +00:00
Nick Lewycky
0c9df5d6c2 Nope! I had it right the first time. Revert the operative part of r139135 and 
add more showing of my work.

llvm-svn: 139136
 2011-09-06 06:39:54 +00:00
Nick Lewycky
39b165bb7d Fix flipped sign. While there, show my math. 
llvm-svn: 139135
 2011-09-06 05:33:18 +00:00
Nick Lewycky
fdc650ea7a No no no, fix typo properly! 
llvm-svn: 139134
 2011-09-06 05:08:09 +00:00
Nick Lewycky
3823432a57 The logic inside getMulExpr to simplify {a,+,b}*{c,+,d} was wrong, which was 
visible given a=b=c=d=1, on iteration #1 (the second iteration). Replace it with
correct math. Fixes PR10383!

llvm-svn: 139133
 2011-09-06 05:05:14 +00:00
Nick Lewycky
18c0b01a56 Revert r139126 due to selfhost failures reported by buildbots. 
llvm-svn: 139130
 2011-09-06 02:43:13 +00:00
Nick Lewycky
30dcc754df Teach SCEV to report a max backedge count in one interesting case in 
HowFarToZero; the case for a canonical loop.

llvm-svn: 139126
 2011-09-05 23:25:16 +00:00
Nick Lewycky
9b5a242546 Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain 
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

llvm-svn: 139125
 2011-09-05 21:51:43 +00:00
Nick Lewycky
cf82a5a673 Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger! 
llvm-svn: 139124
 2011-09-05 18:50:59 +00:00
Nick Lewycky
c10a9bb850 Fix typo in comment. 
llvm-svn: 139122
 2011-09-05 18:35:03 +00:00
Benjamin Kramer
ec933b857e InstSimplify: Don't try to replace an extractvalue/insertvalue pair with the original value if types don't match. 
Fixes clang selfhost.

llvm-svn: 139120
 2011-09-05 18:16:19 +00:00
Duncan Sands
d883f9f371 Delete trivial landing pads that just continue unwinding the caught 
exception.

llvm-svn: 139117
 2011-09-05 12:57:57 +00:00
Duncan Sands
a74d10bb60 Add some simple insertvalue simplifications, for the purpose of cleaning 
up do-nothing exception handling code produced by dragonegg.

llvm-svn: 139113
 2011-09-05 06:52:48 +00:00
Benjamin Kramer
0c1a5d2067 Use canonical forms for the branch probability zero heutistic. 
- Drop support for X >u 0, it's equivalent to X != 0 and should be canonicalized into the latter.
- Add X < 1 -> unlikely, which is what instcombine canonicalizes X <= 0 into.
- Add X > -1 -> likely, which is what instcombine canonicalizes X >= 0 into.

llvm-svn: 139110
 2011-09-04 23:53:04 +00:00
Bill Wendling
0506959970 Use Duncan's patch to delete the instructions in reverse order (minus the landingpad and terminator). 
llvm-svn: 139090
 2011-09-04 09:43:36 +00:00
Bill Wendling
dbea8de893 The insertion point for the loads is right before the llvm.eh.exception 
call. The call may be in the same BB as the landingpad instruction. If that's
the case, then inserting the loads after the landingpad inst, but before the
extractvalues, causes undefined behavior.

llvm-svn: 139088
 2011-09-04 09:02:18 +00:00
Benjamin Kramer
902004dcd8 Use internal storage for command line option. 
llvm-svn: 139079
 2011-09-03 03:45:06 +00:00
Bill Wendling
c273c3f456 Don't reload the values that are already there. The llvm.eh.resume uses the same 
values that the resume instruction uses.
PR10850

llvm-svn: 139076
 2011-09-03 01:38:17 +00:00
Bruno Cardoso Lopes
02157d584a Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends 
the cycle of missing AVX counterparts of already present SSE* patterns

llvm-svn: 139073
 2011-09-03 00:47:08 +00:00
Bruno Cardoso Lopes
c72ce24240 Add AVX version of a SSE4.1 VPBLENDVB pattern 
llvm-svn: 139072
 2011-09-03 00:47:05 +00:00
Bruno Cardoso Lopes
a25fc6f941 Add AVX versions of SSE4.1 EXTRACTPS patterns 
llvm-svn: 139071
 2011-09-03 00:47:03 +00:00
Bruno Cardoso Lopes
45d02d5eca Add AVX versions for SSE4.1 MOVZX* patterns 
llvm-svn: 139070
 2011-09-03 00:47:01 +00:00
Bruno Cardoso Lopes
cadec3711c Add one more AVX pattern for MOVZPQILo2PQI 
llvm-svn: 139069
 2011-09-03 00:46:58 +00:00
Bruno Cardoso Lopes
48eeb79003 Move PUNPCKLQDQ splat pattern close to the instruction definition and 
duplicate it for AVX mode.

llvm-svn: 139068
 2011-09-03 00:46:56 +00:00
Bruno Cardoso Lopes
ca90af60bd Add AVX pattern versions for PSHUFB,PSIGN{B,W,D} 
llvm-svn: 139067
 2011-09-03 00:46:54 +00:00
Bruno Cardoso Lopes
7fae5ca308 Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate 
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

llvm-svn: 139066
 2011-09-03 00:46:51 +00:00
Bruno Cardoso Lopes
e749426ece Enforce subtarget checks in a few places to be explicit when the 
pattern should be matched

llvm-svn: 139065
 2011-09-03 00:46:49 +00:00
Bruno Cardoso Lopes
323a5b334e Tidy up code moving patterns to their appropriate place! 
llvm-svn: 139064
 2011-09-03 00:46:47 +00:00
Bruno Cardoso Lopes
ea1931b9d0 Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use 
it!

llvm-svn: 139063
 2011-09-03 00:46:45 +00:00
Bruno Cardoso Lopes
eb041875c1 Teach X86FastISel to use AVX versions of instructions when possible 
llvm-svn: 139062
 2011-09-03 00:46:42 +00:00
Bruno Cardoso Lopes
86c67e11c9 Fix 80-column and style 
llvm-svn: 139061
 2011-09-03 00:46:40 +00:00
Bruno Cardoso Lopes
beb7a448e7 Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of 
OptForSize pattern

llvm-svn: 139060
 2011-09-03 00:46:38 +00:00
Owen Anderson
05f809efff Fix a truly heinous bug in DAGCombine related to AssertZext. 
If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert.  The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users.  No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.

llvm-svn: 139059
 2011-09-03 00:26:49 +00:00
Jakob Stoklund Olesen
ef8527b836 Pseudo CMOV instructions don't clobber EFLAGS. 
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
 2011-09-02 23:52:55 +00:00
Jakob Stoklund Olesen
29145a3de1 Check for EFLAGS live-out before clobbering it. 
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

llvm-svn: 139056
 2011-09-02 23:52:52 +00:00
Jakob Stoklund Olesen
6d5d51f687 Use existing function. 
llvm-svn: 139055
 2011-09-02 23:52:49 +00:00
Jim Grosbach
fb5e64e731 Thumb2 parsing and encoding for BXJ. 
llvm-svn: 139053
 2011-09-02 23:43:09 +00:00
Jim Grosbach
44483a9ba5 Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Jakob Stoklund Olesen
c710d8fdc7 Remove unused variables. 
llvm-svn: 139047
 2011-09-02 22:41:25 +00:00
Eli Friedman
383a3c76b2 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Jim Grosbach
ba4ceeaae6 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040
 2011-09-02 21:28:54 +00:00
Andrew Trick
43d88c3879 Comment and clarifying assert. 
llvm-svn: 139036
 2011-09-02 21:20:46 +00:00
Bill Wendling
e35fdee39e No need to get fancy inserting a PHI node when the values are stored in stack 
slots. This fixes a bug where the number of nodes coming into the PHI node may
not equal the number of predecessors. E.g., two or more landingpad instructions
may require a PHI before reaching the eh.exception and eh.selector instructions.

llvm-svn: 139035
 2011-09-02 21:17:08 +00:00
Kevin Enderby
90a1526592 Change X86 disassembly to print immediates values as signed by default. Special 
case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028
 2011-09-02 20:01:23 +00:00
Jim Grosbach
20ed697ea7 Tidy up. Formatting. 
llvm-svn: 139024
 2011-09-02 18:46:15 +00:00
Bill Wendling
3033d7846d Update comments to reflect reality. 
llvm-svn: 139023
 2011-09-02 18:43:33 +00:00
Jim Grosbach
a93f292add Tidy up. 80 columns. 
llvm-svn: 139022
 2011-09-02 18:43:25 +00:00
Jim Grosbach
cbf37eebff Thumb2 parsing and encoding for AND (register). 
llvm-svn: 139021
 2011-09-02 18:41:35 +00:00
Jakob Stoklund Olesen
d10a0768cb Simplify by using isFullCopy(). 
llvm-svn: 139019
 2011-09-02 18:18:29 +00:00
Bill Wendling
991a1dab16 Revert r138826 until PR10834 can be fixed. 
llvm-svn: 139018
 2011-09-02 18:15:04 +00:00
Jim Grosbach
dd0421034a Thumb2 parsing and encoding for ADD (register). 
llvm-svn: 139017
 2011-09-02 18:14:46 +00:00
Duncan Sands
33f33411e8 Darwin wants ctors/dtors to be ordered the other way round to linux. 
llvm-svn: 139015
 2011-09-02 18:07:19 +00:00
Andrew Trick
36b96e4619 Enable SCEV-based unrolling by default. 
This changes loop unrolling to use the same mechanism for trip count
computation as indvars. This is a stronger check that tends to unroll
more loops. A very common side-effect is that many single iteration
loops will be removed sooner. The real goal was simply to remove
dependence on canonical IVs.

x86 is break even.
ARM performance changes to expect (+ is good):
External/SPEC/CFP2000/183.equake/183.equake +13%
SingleSource/Benchmarks/Dhrystone/fldry     +21%
MultiSource/Applications/spiff/spiff         +3%
SingleSource/Benchmarks/Stanford/Puzzle     -14%

The Puzzle regression is actually an improvement in loop optimization
that defeats GVN: rdar://problem/10065079.

llvm-svn: 139009
 2011-09-02 17:26:28 +00:00
Jakub Staszak
4df162e09b Return undef value (instead of arbitrary) for wrong or undef index in 
ConstantVector.

llvm-svn: 139007
 2011-09-02 17:01:40 +00:00
Jakub Staszak
132e24bf28 ConstantVector returns arbitrary value for the wrong index. 
This fixes PR10813.

llvm-svn: 139006
 2011-09-02 15:43:43 +00:00
Jakub Staszak
b82758ae9b Compare type size instead of type _store_ size to make sure that BitCastInst 
will be valid. This fixes PR10820.

llvm-svn: 139005
 2011-09-02 14:57:37 +00:00
Kalle Raiskila
7c154fe467 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction. 
llvm-svn: 139004
 2011-09-02 10:05:01 +00:00
Bill Wendling
66d5793dcf Perform the upgrading of the old EH to the new EH in a more sane manner. 
Perform the upgrading in steps.

* First, create a map of the invokes to the EH intrinsics.

* Next, take that mapping and determine if the invoke's unwind destination has a
  single predecessor. If not, then create a new empty block to hold the new
  landingpad instruction.

* Create a landingpad instruction into the uwnind destination. Fill it with the
  values from the old selector. Map the old intrinsic calls to the new
  landingpad values (there may be multiple landingpad instructions per instrinic
  call pairs).

* Go through the old intrinsic calls, create a PHI node when necessary, and then
  replace their values with the new values from the landingpad instructions.

* Delete all dead instructions.

* ???

* Profit!

llvm-svn: 138990
 2011-09-02 01:30:08 +00:00
Owen Anderson
a319b9901d Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
llvm-svn: 138982
 2011-09-01 23:35:51 +00:00
Owen Anderson
c4ec9cc45f Fix 80 columns violations. 
llvm-svn: 138980
 2011-09-01 23:23:50 +00:00
Dan Gohman
6d0230847c Revert r131152, r129796, r129761. This code is currently considered 
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977
 2011-09-01 23:07:08 +00:00
Benjamin Kramer
bd939ad83e Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
 2011-09-01 23:04:27 +00:00
Eli Friedman
1400b24e06 Null-initialize to shut up -Wuninitialized warnings. 
llvm-svn: 138974
 2011-09-01 22:27:41 +00:00
James Molloy
5f19051fbd Fix apparent build error caused by r138948 on certain versions of GCC with -Werror. Sorry for the inconvenience. 
llvm-svn: 138973
 2011-09-01 22:01:14 +00:00
Bill Wendling
b6a419d0f0 Reduce indentation. No functionality change. 
llvm-svn: 138968
 2011-09-01 21:29:49 +00:00
Bill Wendling
759eb19f0b Change worklist driven deletion to be an iterative process. 
Duncan noticed this!

llvm-svn: 138967
 2011-09-01 21:28:33 +00:00
Eli Friedman
00a62b2122 Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.) 
llvm-svn: 138965
 2011-09-01 21:21:24 +00:00
Nick Lewycky
99efd4b3ac Fix the build for us -Werror users. 
Remove broken emacs mode major notation marking a C++ file as C.
No functionality change.

llvm-svn: 138963
 2011-09-01 21:09:04 +00:00
Eli Friedman
3e1fc84a39 Make isSafeToSpeculativelyExecute() return the right answer for some new instructions. Found by inspection; not sure what practical impact, if any, this has. 
llvm-svn: 138962
 2011-09-01 21:03:03 +00:00
Jakob Stoklund Olesen
c26e2e6221 Permit remat of partial register defs when it is safe. 
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:

  %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>

The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.

This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.

llvm-svn: 138953
 2011-09-01 18:27:51 +00:00
Jim Grosbach
36ea6726dd ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
Bruno Cardoso Lopes
10f234f1a7 Fix vbroadcast matching logic to early unmatch if the node doesn't have 
only one use. Fix PR10825.

llvm-svn: 138951
 2011-09-01 18:15:06 +00:00
James Molloy
4a63186421 Fix up r137380 based on post-commit review by Jim Grosbach. 
llvm-svn: 138948
 2011-09-01 18:02:14 +00:00
Owen Anderson
d8157fabfb t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jakob Stoklund Olesen
ff7cf9e336 Revert r138794, "Do not try to rematerialize a value from a partial definition." 
The problem is fixed for all register allocators by r138944, so this
patch is no longer necessary.

<rdar://problem/10032939>

llvm-svn: 138945
 2011-09-01 17:25:18 +00:00
Jakob Stoklund Olesen
bc000bf219 Prevent remat of partial register redefinitions. 
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944
 2011-09-01 17:18:50 +00:00
Evan Cheng
6f4f659df2 Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690 
llvm-svn: 138934
 2011-09-01 01:45:00 +00:00
Bill Wendling
a6d17107f5 Resubmit with fix. Properly remove the instructions except for landingpad, which should be removed only when its invokes are. 
llvm-svn: 138932
 2011-09-01 01:28:11 +00:00
Bill Wendling
d984ff9663 Submitted this too early. 
llvm-svn: 138931
 2011-09-01 01:18:33 +00:00
Bill Wendling
37fc90ccd9 Don't DCE the landingpad instruction. 
The landingpad instruction can be removed only when its invokes are removed.

llvm-svn: 138930
 2011-09-01 01:16:58 +00:00
Andrew Trick
e5d7c0d111 PreRA scheduler should avoid cloning compares. 
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924
 2011-09-01 00:54:31 +00:00
Bill Wendling
220f6a3b14 Don't forget to add the landingpad and resume instructions to the InstructionList. 
This was found via a nightly build of 483.xalancbmk.

llvm-svn: 138923
 2011-09-01 00:50:20 +00:00
Jim Grosbach
2b04342a91 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Chad Rosier
aa490636db Fixup for functions that return a bool. 
llvm-svn: 138918
 2011-08-31 23:49:05 +00:00
Jim Grosbach
1af1d2dfda Static relocation model Thumb jump table interworking. 
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912
 2011-08-31 22:23:09 +00:00
Owen Anderson
dd71d9efb9 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
llvm-svn: 138910
 2011-08-31 22:00:41 +00:00
David Greene
bff3eae46b Fix Size Typing 
Stores sizes as uint64_t to avoid possible truncation.

llvm-svn: 138901
 2011-08-31 21:34:20 +00:00
Jim Grosbach
3dd66f0c98 Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
llvm-svn: 138898
 2011-08-31 21:17:31 +00:00
Bruno Cardoso Lopes
8771512b75 Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS 
llvm-svn: 138897
 2011-08-31 21:15:32 +00:00
Bruno Cardoso Lopes
22aceefbf7 Move MOVAPS,MOVUPS patterns close to the instructions definition 
llvm-svn: 138896
 2011-08-31 21:15:29 +00:00
Bruno Cardoso Lopes
4823fe07e6 Remove "_Int" forms of MOVUPSmr and MOVAPSmr 
llvm-svn: 138895
 2011-08-31 21:15:22 +00:00
Bill Wendling
df24e0d185 Make sure we aren't deleting the landingpad instruction. 
The landingpad instruction is required in the landing pad block. Because we're
not deleting terminating instructions, the invoke may still jump to here (see
Transforms/SCCP/2004-11-16-DeadInvoke.ll). Remove all uses of the landingpad
instruction, but keep it around until code-gen can remove the basic block.

llvm-svn: 138890
 2011-08-31 20:55:20 +00:00
Owen Anderson
4024b91dbe Fix encoding for tBcc with immediate offset operand. 
llvm-svn: 138889
 2011-08-31 20:26:14 +00:00
Eli Friedman
f57df1ac66 Misc cleanup; addresses Duncan's comments on r138877. 
llvm-svn: 138887
 2011-08-31 20:13:26 +00:00
Owen Anderson
de17548520 When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. 
<rdar://problem/10046188>

llvm-svn: 138885
 2011-08-31 20:00:11 +00:00
Jim Grosbach
74f916342a Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.

llvm-svn: 138879
 2011-08-31 18:39:39 +00:00
Eli Friedman
5f0e04a5bd Fill in type legalization for MERGE_VALUES in all the various cases. Patch by Micah Villmow. (No testcase because the issue only showed up in an out-of-tree backend.) 
llvm-svn: 138877
 2011-08-31 18:36:04 +00:00
Owen Anderson
f30633abbf Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
llvm-svn: 138874
 2011-08-31 18:30:20 +00:00
Jim Grosbach
4dddfb237c tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
llvm-svn: 138873
 2011-08-31 18:29:05 +00:00
Eli Friedman
8ae6a88723 Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. 
llvm-svn: 138872
 2011-08-31 18:26:09 +00:00
Jim Grosbach
a2f9012605 Thumb2 parsing and encoding for ADC(register). 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

llvm-svn: 138871
 2011-08-31 18:23:08 +00:00
Devang Patel
26f7aeed7c After r138010, subroutine type does not have context info. Update type verifier accordingly. 
This fixes ptype.exp gdb testsuite regressions.

llvm-svn: 138869
 2011-08-31 18:04:31 +00:00
Eli Friedman
5d3814e0c4 64-bit atomic cmpxchg for ARM. 
llvm-svn: 138868
 2011-08-31 17:52:22 +00:00
Akira Hatanaka
6617606549 Fix typo. Patch by Liu. 
llvm-svn: 138866
 2011-08-31 17:49:04 +00:00
David Greene
a975ef3213 Compress Repeated Byte Output 
Emit a repeated sequence of bytes using .zero.  This saves an enormous
amount of asm file space for certain programs.

llvm-svn: 138864
 2011-08-31 17:30:56 +00:00
Jim Grosbach
a4c1e9d88a Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862
 2011-08-31 17:07:33 +00:00
Jakob Stoklund Olesen
ad3a292ff7 Put VMOVS widening under a command line option, off by default. 
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

llvm-svn: 138861
 2011-08-31 17:00:02 +00:00
Rafael Espindola
295e404961 Spelling and grammar fixes to problems found by Duncan. 
llvm-svn: 138858
 2011-08-31 16:43:33 +00:00
Eli Friedman
4fefb0a561 Make sure we don't crash when -miphoneos-version-min is specified on x86. Hopefully this will fix gcc testsuite failures. 
llvm-svn: 138856
 2011-08-31 16:19:51 +00:00
Eric Christopher
157bf8b08d Rework this conditional a bit. 
Patch by Sanjoy Das

llvm-svn: 138853
 2011-08-31 04:17:21 +00:00
Bruno Cardoso Lopes
5bd6e92f99 - Move all MOVSS and MOVSD patterns close to their definitions 
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

llvm-svn: 138851
 2011-08-31 03:04:20 +00:00
Bruno Cardoso Lopes
a9c2c56e13 Remove unnecessary AVX checks 
llvm-svn: 138850
 2011-08-31 03:04:14 +00:00
Bruno Cardoso Lopes
fe3f3344a6 Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS, 
whenever AVX is enabled.

llvm-svn: 138849
 2011-08-31 03:04:09 +00:00
Evan Cheng
bbabe9ff60 Fix (movhps load) lowering / pattern to match more cases. rdar://10050549 
llvm-svn: 138848
 2011-08-31 02:05:24 +00:00
Eli Friedman
928959bc52 Some minor cleanups for r138845. 
llvm-svn: 138846
 2011-08-31 00:41:05 +00:00
Eli Friedman
d71c865ae0 Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. 
llvm-svn: 138845
 2011-08-31 00:31:29 +00:00
Rafael Espindola
3bb0f9391c Remove the old tail duplication pass. It is not used and is unable to update 
ssa, so it has to be run really early in the pipeline. Any replacement
should probably use the SSAUpdater.

llvm-svn: 138841
 2011-08-30 23:03:45 +00:00
Owen Anderson
adac5b2109 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
llvm-svn: 138840
 2011-08-30 22:58:27 +00:00
Owen Anderson
a59d489162 Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. 
llvm-svn: 138837
 2011-08-30 22:15:17 +00:00
Benjamin Kramer
2ca7c2b2c7 Teach macho-dump to dump the uleb128s referred to by linkedit_data segments. 
llvm-svn: 138836
 2011-08-30 22:10:58 +00:00
Owen Anderson
9465c7fee0 Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. 
llvm-svn: 138835
 2011-08-30 22:10:03 +00:00
Owen Anderson
309c4b7ef6 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. 
llvm-svn: 138834
 2011-08-30 22:03:20 +00:00
Owen Anderson
d9dbde4a50 Clean up whitespace. 
llvm-svn: 138833
 2011-08-30 21:58:18 +00:00
Bill Wendling
1e8c335302 Fix off-by-one error Benjamin noticed. 
llvm-svn: 138832
 2011-08-30 21:23:24 +00:00
Owen Anderson
d3a9f00a58 Speculatively revert r138809 in an attempt to fix DragonEgg. 
llvm-svn: 138829
 2011-08-30 21:11:06 +00:00
Bill Wendling
569b9fee87 Enable compact unwind info by default. This only applies to Darwin when CFI is 
disabled.

llvm-svn: 138826
 2011-08-30 20:54:11 +00:00
Jeffrey Yasskin
8f36e758c2 Fix C++0x narrowing errors when char is unsigned. 
In the case of EDInstInfo, this would actually cause a bug when -1 became 255
and was then compared >=0 in llvm-mc/Disassembler.cpp.

llvm-svn: 138825
 2011-08-30 20:53:29 +00:00
Rafael Espindola
9db302e741 Adds support for variable sized allocas. For a variable sized alloca, 
code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.

Patch by Sanjoy Das.

llvm-svn: 138818
 2011-08-30 19:47:04 +00:00
Rafael Espindola
7721c15106 Adds a SelectionDAG node X86SegAlloca which will be custom lowered 
from DYNAMIC_STACKALLOC.

Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added.  They
will be custom emitted to inject the actual stack handling code.

Patch by Sanjoy Das.

llvm-svn: 138814
 2011-08-30 19:43:21 +00:00
Rafael Espindola
321e47cd0b Emit segmented-stack specific code into function prologues for 
X86. Modify the pass added in the previous patch to call this new
code.

This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required

Patch by Sanjoy Das.

llvm-svn: 138812
 2011-08-30 19:39:58 +00:00
Rafael Espindola
84f69a1992 Command line option to enable support for segmented stacks: 
-segmented-stacks.
Patch by Sanjoy Das!

llvm-svn: 138811
 2011-08-30 19:29:02 +00:00
Evan Cheng
91aa81acaa Follow up to r138791. 
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810
 2011-08-30 19:09:48 +00:00
Owen Anderson
3ec8beb8c8 When walking backwards to eliminate final stores to allocas at the end of a function, encountering an unrelated store should not cause us to give up like encountering a load does. 
llvm-svn: 138809
 2011-08-30 18:51:55 +00:00
Benjamin Kramer
de3a6db63c Teach macho-dump how to dump linkedit_data load commands. 
llvm-svn: 138807
 2011-08-30 18:33:37 +00:00
Roman Divacky
7ac1bc57f7 Set CR1EQ only when lowering vararg floating arguments (not any vararg 
arguments as before), unset CR1EQ otherwise.

llvm-svn: 138802
 2011-08-30 17:04:16 +00:00
James Molloy
a7a4266f83 Fix typos in SPUMCTargetDesc.h 
Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138799
 2011-08-30 07:27:02 +00:00
James Molloy
c537f89907 Fix typo in BlackfinFrameLowering.h 
Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138798
 2011-08-30 07:26:11 +00:00
James Molloy
21b255e052 Fix typo in MSP430MCTargetDesc.h. 
Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138797
 2011-08-30 07:24:47 +00:00
James Molloy
e841c9709a Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com) 
llvm-svn: 138796
 2011-08-30 07:23:29 +00:00
Bob Wilson
cc7b5b71eb Do not try to rematerialize a value from a partial definition. 
I don't currently have a good testcase for this; will try to get one
tomorrow.  <rdar://problem/10032939>

llvm-svn: 138794
 2011-08-30 05:36:02 +00:00
Evan Cheng
1eacb83316 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576

llvm-svn: 138791
 2011-08-30 01:34:54 +00:00
Jim Grosbach
187be92001 Revert 138781. It's not playing nicely with the immediate forms for ADC. 
llvm-svn: 138782
 2011-08-29 23:24:15 +00:00
Jim Grosbach
bc2d35e0ec Thumb2 assembler aliases for ADC/SBC w/o the .w suffix. 
llvm-svn: 138781
 2011-08-29 23:20:54 +00:00
Owen Anderson
4bd28c69c4 Add missing encoding information for some of the GPR<->FP register moves. 
llvm-svn: 138780
 2011-08-29 23:15:25 +00:00
Jim Grosbach
a1aa6a2e8b Thumb2 parsing and encoding for IT blocks. 
llvm-svn: 138773
 2011-08-29 22:24:09 +00:00
Eli Friedman
4d90e53381 Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. 
llvm-svn: 138768
 2011-08-29 21:15:46 +00:00
Owen Anderson
bbb6ed8264 Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. 
llvm-svn: 138766
 2011-08-29 21:14:19 +00:00
Bill Wendling
d9df43679c Fix grammar, noticed by Duncan. 
llvm-svn: 138764
 2011-08-29 21:03:12 +00:00
Owen Anderson
518e14771a Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding. 
llvm-svn: 138760
 2011-08-29 20:42:00 +00:00
Owen Anderson
44c24b13a3 addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. 
llvm-svn: 138758
 2011-08-29 20:16:50 +00:00
Nadav Rotem
43912ff374 Fixes following the CR by Chris and Duncan: 
Optimize chained bitcasts of the form A->B->A.
Undo r138722 and change isEliminableCastPair to allow this case.

llvm-svn: 138756
 2011-08-29 19:58:36 +00:00
Owen Anderson
e14d6edccc Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
llvm-svn: 138754
 2011-08-29 19:36:44 +00:00
Bill Wendling
6d2c747e53 Initialize CompactUnwindSection so that other targets won't use an uninitialized value. 
llvm-svn: 138752
 2011-08-29 18:25:59 +00:00
Eli Friedman
6d27cb5e01 Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
llvm-svn: 138751
 2011-08-29 18:23:02 +00:00
Benjamin Kramer
da658378b3 Dump with dbgs() instead of printf. 
llvm-svn: 138749
 2011-08-29 18:14:17 +00:00
Benjamin Kramer
442620e4c4 Make GCC happy by adding parens. 
llvm-svn: 138748
 2011-08-29 18:14:15 +00:00
Owen Anderson
3136f0a930 Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653. 
llvm-svn: 138746
 2011-08-29 17:59:41 +00:00
Bruno Cardoso Lopes
3a09888a72 Move non-intruction patterns to a more appropriate place! 
llvm-svn: 138744
 2011-08-29 17:51:24 +00:00
Owen Anderson
8719e2c1c3 Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
llvm-svn: 138739
 2011-08-29 17:17:09 +00:00
Andrew Trick
026fa4da72 Reapply r138695. Fix PassManager stack depths. 
Patch by Xiaoyi Guo!

llvm-svn: 138737
 2011-08-29 17:07:00 +00:00
Tobias Grosser
c6abc36833 Add AMDIL as valid target triple to LLVM. 
Submitted by: Villmow, Micah <Micah.Villmow@amd.com>

llvm-svn: 138734
 2011-08-29 15:44:55 +00:00
Nicolas Geoffray
74b006fe71 Remove premature previous commit. 
llvm-svn: 138725
 2011-08-28 14:52:51 +00:00
Duncan Sands
1a69e0119a Fix PR5329: pay attention to constructor/destructor priority 
when outputting them.  With this, the entire LLVM testsuite
passes when built with dragonegg.

llvm-svn: 138724
 2011-08-28 13:17:22 +00:00
Nicolas Geoffray
d30e51ca07 Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does. 
llvm-svn: 138723
 2011-08-28 13:07:57 +00:00
Nadav Rotem
6280c8eecc Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X. 
llvm-svn: 138722
 2011-08-28 11:51:08 +00:00
Nick Lewycky
a28dc138a1 Fix integer overflow bug in raw_ostream::write. This showed up as a 
non-deterministic crash in the test suite. Fixes PR10055!

llvm-svn: 138717
 2011-08-28 03:30:02 +00:00
Benjamin Kramer
6411b8f81a Silence GCC warnings and make an array const. 
llvm-svn: 138706
 2011-08-27 17:36:14 +00:00
Benjamin Kramer
70ba1d6ab4 Report failure if there are less bytes than requested in a MemoryObject. 
Before we just left the remaining bytes uninitialized. This is another step in making llvm valgrind-clean again.

llvm-svn: 138705
 2011-08-27 07:45:46 +00:00
Bill Wendling
b0412973be Auto upgrade the old EH scheme to use the new one. This is on a trial basis. If 
things to disasterously over night, this can be reverted.

llvm-svn: 138702
 2011-08-27 06:11:03 +00:00
Andrew Trick
65754eb3f7 Reverting r138695 to see if it fixes clang self host. 
llvm-svn: 138701
 2011-08-27 06:10:16 +00:00
Bill Wendling
607b3c3898 Only delete instructions once. 
llvm-svn: 138700
 2011-08-27 06:10:02 +00:00
Bill Wendling
a23e3f4f85 These splits should be done whether they are critical edges or not. 
llvm-svn: 138697
 2011-08-27 04:40:37 +00:00
Andrew Trick
e38568bc07 Fix PassManager stack depths. 
Patch by Xiaoyi Guo!

llvm-svn: 138695
 2011-08-27 02:11:03 +00:00
Owen Anderson
fd21da3506 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
llvm-svn: 138675
 2011-08-26 23:32:08 +00:00
Owen Anderson
9b85a034c9 Correct encoding of BL with immediate offset. 
llvm-svn: 138673
 2011-08-26 22:54:51 +00:00