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Author SHA1 Message Date
Bruno Cardoso Lopes
7fae5ca308 Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate 
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

llvm-svn: 139066
 2011-09-03 00:46:51 +00:00
Bruno Cardoso Lopes
e749426ece Enforce subtarget checks in a few places to be explicit when the 
pattern should be matched

llvm-svn: 139065
 2011-09-03 00:46:49 +00:00
Bruno Cardoso Lopes
323a5b334e Tidy up code moving patterns to their appropriate place! 
llvm-svn: 139064
 2011-09-03 00:46:47 +00:00
Bruno Cardoso Lopes
ea1931b9d0 Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use 
it!

llvm-svn: 139063
 2011-09-03 00:46:45 +00:00
Bruno Cardoso Lopes
eb041875c1 Teach X86FastISel to use AVX versions of instructions when possible 
llvm-svn: 139062
 2011-09-03 00:46:42 +00:00
Bruno Cardoso Lopes
86c67e11c9 Fix 80-column and style 
llvm-svn: 139061
 2011-09-03 00:46:40 +00:00
Bruno Cardoso Lopes
beb7a448e7 Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of 
OptForSize pattern

llvm-svn: 139060
 2011-09-03 00:46:38 +00:00
Owen Anderson
05f809efff Fix a truly heinous bug in DAGCombine related to AssertZext. 
If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert.  The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users.  No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.

llvm-svn: 139059
 2011-09-03 00:26:49 +00:00
Jakob Stoklund Olesen
ef8527b836 Pseudo CMOV instructions don't clobber EFLAGS. 
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
 2011-09-02 23:52:55 +00:00
Jakob Stoklund Olesen
29145a3de1 Check for EFLAGS live-out before clobbering it. 
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

llvm-svn: 139056
 2011-09-02 23:52:52 +00:00
Jakob Stoklund Olesen
6d5d51f687 Use existing function. 
llvm-svn: 139055
 2011-09-02 23:52:49 +00:00
Jim Grosbach
fb5e64e731 Thumb2 parsing and encoding for BXJ. 
llvm-svn: 139053
 2011-09-02 23:43:09 +00:00
Jim Grosbach
44483a9ba5 Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Jakob Stoklund Olesen
c710d8fdc7 Remove unused variables. 
llvm-svn: 139047
 2011-09-02 22:41:25 +00:00
Eli Friedman
383a3c76b2 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Jim Grosbach
ba4ceeaae6 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040
 2011-09-02 21:28:54 +00:00
Andrew Trick
43d88c3879 Comment and clarifying assert. 
llvm-svn: 139036
 2011-09-02 21:20:46 +00:00
Bill Wendling
e35fdee39e No need to get fancy inserting a PHI node when the values are stored in stack 
slots. This fixes a bug where the number of nodes coming into the PHI node may
not equal the number of predecessors. E.g., two or more landingpad instructions
may require a PHI before reaching the eh.exception and eh.selector instructions.

llvm-svn: 139035
 2011-09-02 21:17:08 +00:00
Kevin Enderby
90a1526592 Change X86 disassembly to print immediates values as signed by default. Special 
case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028
 2011-09-02 20:01:23 +00:00
Jim Grosbach
20ed697ea7 Tidy up. Formatting. 
llvm-svn: 139024
 2011-09-02 18:46:15 +00:00
Bill Wendling
3033d7846d Update comments to reflect reality. 
llvm-svn: 139023
 2011-09-02 18:43:33 +00:00
Jim Grosbach
a93f292add Tidy up. 80 columns. 
llvm-svn: 139022
 2011-09-02 18:43:25 +00:00
Jim Grosbach
cbf37eebff Thumb2 parsing and encoding for AND (register). 
llvm-svn: 139021
 2011-09-02 18:41:35 +00:00
Jakob Stoklund Olesen
d10a0768cb Simplify by using isFullCopy(). 
llvm-svn: 139019
 2011-09-02 18:18:29 +00:00
Bill Wendling
991a1dab16 Revert r138826 until PR10834 can be fixed. 
llvm-svn: 139018
 2011-09-02 18:15:04 +00:00
Jim Grosbach
dd0421034a Thumb2 parsing and encoding for ADD (register). 
llvm-svn: 139017
 2011-09-02 18:14:46 +00:00
Duncan Sands
33f33411e8 Darwin wants ctors/dtors to be ordered the other way round to linux. 
llvm-svn: 139015
 2011-09-02 18:07:19 +00:00
Andrew Trick
36b96e4619 Enable SCEV-based unrolling by default. 
This changes loop unrolling to use the same mechanism for trip count
computation as indvars. This is a stronger check that tends to unroll
more loops. A very common side-effect is that many single iteration
loops will be removed sooner. The real goal was simply to remove
dependence on canonical IVs.

x86 is break even.
ARM performance changes to expect (+ is good):
External/SPEC/CFP2000/183.equake/183.equake +13%
SingleSource/Benchmarks/Dhrystone/fldry     +21%
MultiSource/Applications/spiff/spiff         +3%
SingleSource/Benchmarks/Stanford/Puzzle     -14%

The Puzzle regression is actually an improvement in loop optimization
that defeats GVN: rdar://problem/10065079.

llvm-svn: 139009
 2011-09-02 17:26:28 +00:00
Jakub Staszak
4df162e09b Return undef value (instead of arbitrary) for wrong or undef index in 
ConstantVector.

llvm-svn: 139007
 2011-09-02 17:01:40 +00:00
Jakub Staszak
132e24bf28 ConstantVector returns arbitrary value for the wrong index. 
This fixes PR10813.

llvm-svn: 139006
 2011-09-02 15:43:43 +00:00
Jakub Staszak
b82758ae9b Compare type size instead of type _store_ size to make sure that BitCastInst 
will be valid. This fixes PR10820.

llvm-svn: 139005
 2011-09-02 14:57:37 +00:00
Kalle Raiskila
7c154fe467 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction. 
llvm-svn: 139004
 2011-09-02 10:05:01 +00:00
Bill Wendling
66d5793dcf Perform the upgrading of the old EH to the new EH in a more sane manner. 
Perform the upgrading in steps.

* First, create a map of the invokes to the EH intrinsics.

* Next, take that mapping and determine if the invoke's unwind destination has a
  single predecessor. If not, then create a new empty block to hold the new
  landingpad instruction.

* Create a landingpad instruction into the uwnind destination. Fill it with the
  values from the old selector. Map the old intrinsic calls to the new
  landingpad values (there may be multiple landingpad instructions per instrinic
  call pairs).

* Go through the old intrinsic calls, create a PHI node when necessary, and then
  replace their values with the new values from the landingpad instructions.

* Delete all dead instructions.

* ???

* Profit!

llvm-svn: 138990
 2011-09-02 01:30:08 +00:00
Owen Anderson
a319b9901d Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
llvm-svn: 138982
 2011-09-01 23:35:51 +00:00
Owen Anderson
c4ec9cc45f Fix 80 columns violations. 
llvm-svn: 138980
 2011-09-01 23:23:50 +00:00
Dan Gohman
6d0230847c Revert r131152, r129796, r129761. This code is currently considered 
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977
 2011-09-01 23:07:08 +00:00
Benjamin Kramer
bd939ad83e Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
 2011-09-01 23:04:27 +00:00
Eli Friedman
1400b24e06 Null-initialize to shut up -Wuninitialized warnings. 
llvm-svn: 138974
 2011-09-01 22:27:41 +00:00
James Molloy
5f19051fbd Fix apparent build error caused by r138948 on certain versions of GCC with -Werror. Sorry for the inconvenience. 
llvm-svn: 138973
 2011-09-01 22:01:14 +00:00
Bill Wendling
b6a419d0f0 Reduce indentation. No functionality change. 
llvm-svn: 138968
 2011-09-01 21:29:49 +00:00
Bill Wendling
759eb19f0b Change worklist driven deletion to be an iterative process. 
Duncan noticed this!

llvm-svn: 138967
 2011-09-01 21:28:33 +00:00
Eli Friedman
00a62b2122 Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.) 
llvm-svn: 138965
 2011-09-01 21:21:24 +00:00
Nick Lewycky
99efd4b3ac Fix the build for us -Werror users. 
Remove broken emacs mode major notation marking a C++ file as C.
No functionality change.

llvm-svn: 138963
 2011-09-01 21:09:04 +00:00
Eli Friedman
3e1fc84a39 Make isSafeToSpeculativelyExecute() return the right answer for some new instructions. Found by inspection; not sure what practical impact, if any, this has. 
llvm-svn: 138962
 2011-09-01 21:03:03 +00:00
Jakob Stoklund Olesen
c26e2e6221 Permit remat of partial register defs when it is safe. 
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:

  %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>

The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.

This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.

llvm-svn: 138953
 2011-09-01 18:27:51 +00:00
Jim Grosbach
36ea6726dd ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
Bruno Cardoso Lopes
10f234f1a7 Fix vbroadcast matching logic to early unmatch if the node doesn't have 
only one use. Fix PR10825.

llvm-svn: 138951
 2011-09-01 18:15:06 +00:00
James Molloy
4a63186421 Fix up r137380 based on post-commit review by Jim Grosbach. 
llvm-svn: 138948
 2011-09-01 18:02:14 +00:00
Owen Anderson
d8157fabfb t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jakob Stoklund Olesen
ff7cf9e336 Revert r138794, "Do not try to rematerialize a value from a partial definition." 
The problem is fixed for all register allocators by r138944, so this
patch is no longer necessary.

<rdar://problem/10032939>

llvm-svn: 138945
 2011-09-01 17:25:18 +00:00
Jakob Stoklund Olesen
bc000bf219 Prevent remat of partial register redefinitions. 
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944
 2011-09-01 17:18:50 +00:00
Evan Cheng
6f4f659df2 Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690 
llvm-svn: 138934
 2011-09-01 01:45:00 +00:00
Bill Wendling
a6d17107f5 Resubmit with fix. Properly remove the instructions except for landingpad, which should be removed only when its invokes are. 
llvm-svn: 138932
 2011-09-01 01:28:11 +00:00
Bill Wendling
d984ff9663 Submitted this too early. 
llvm-svn: 138931
 2011-09-01 01:18:33 +00:00
Bill Wendling
37fc90ccd9 Don't DCE the landingpad instruction. 
The landingpad instruction can be removed only when its invokes are removed.

llvm-svn: 138930
 2011-09-01 01:16:58 +00:00
Andrew Trick
e5d7c0d111 PreRA scheduler should avoid cloning compares. 
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924
 2011-09-01 00:54:31 +00:00
Bill Wendling
220f6a3b14 Don't forget to add the landingpad and resume instructions to the InstructionList. 
This was found via a nightly build of 483.xalancbmk.

llvm-svn: 138923
 2011-09-01 00:50:20 +00:00
Jim Grosbach
2b04342a91 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Chad Rosier
aa490636db Fixup for functions that return a bool. 
llvm-svn: 138918
 2011-08-31 23:49:05 +00:00
Jim Grosbach
1af1d2dfda Static relocation model Thumb jump table interworking. 
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912
 2011-08-31 22:23:09 +00:00
Owen Anderson
dd71d9efb9 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
llvm-svn: 138910
 2011-08-31 22:00:41 +00:00
David Greene
bff3eae46b Fix Size Typing 
Stores sizes as uint64_t to avoid possible truncation.

llvm-svn: 138901
 2011-08-31 21:34:20 +00:00
Jim Grosbach
3dd66f0c98 Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
llvm-svn: 138898
 2011-08-31 21:17:31 +00:00
Bruno Cardoso Lopes
8771512b75 Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS 
llvm-svn: 138897
 2011-08-31 21:15:32 +00:00
Bruno Cardoso Lopes
22aceefbf7 Move MOVAPS,MOVUPS patterns close to the instructions definition 
llvm-svn: 138896
 2011-08-31 21:15:29 +00:00
Bruno Cardoso Lopes
4823fe07e6 Remove "_Int" forms of MOVUPSmr and MOVAPSmr 
llvm-svn: 138895
 2011-08-31 21:15:22 +00:00
Bill Wendling
df24e0d185 Make sure we aren't deleting the landingpad instruction. 
The landingpad instruction is required in the landing pad block. Because we're
not deleting terminating instructions, the invoke may still jump to here (see
Transforms/SCCP/2004-11-16-DeadInvoke.ll). Remove all uses of the landingpad
instruction, but keep it around until code-gen can remove the basic block.

llvm-svn: 138890
 2011-08-31 20:55:20 +00:00
Owen Anderson
4024b91dbe Fix encoding for tBcc with immediate offset operand. 
llvm-svn: 138889
 2011-08-31 20:26:14 +00:00
Eli Friedman
f57df1ac66 Misc cleanup; addresses Duncan's comments on r138877. 
llvm-svn: 138887
 2011-08-31 20:13:26 +00:00
Owen Anderson
de17548520 When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. 
<rdar://problem/10046188>

llvm-svn: 138885
 2011-08-31 20:00:11 +00:00
Jim Grosbach
74f916342a Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.

llvm-svn: 138879
 2011-08-31 18:39:39 +00:00
Eli Friedman
5f0e04a5bd Fill in type legalization for MERGE_VALUES in all the various cases. Patch by Micah Villmow. (No testcase because the issue only showed up in an out-of-tree backend.) 
llvm-svn: 138877
 2011-08-31 18:36:04 +00:00
Owen Anderson
f30633abbf Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
llvm-svn: 138874
 2011-08-31 18:30:20 +00:00
Jim Grosbach
4dddfb237c tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
llvm-svn: 138873
 2011-08-31 18:29:05 +00:00
Eli Friedman
8ae6a88723 Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. 
llvm-svn: 138872
 2011-08-31 18:26:09 +00:00
Jim Grosbach
a2f9012605 Thumb2 parsing and encoding for ADC(register). 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

llvm-svn: 138871
 2011-08-31 18:23:08 +00:00
Devang Patel
26f7aeed7c After r138010, subroutine type does not have context info. Update type verifier accordingly. 
This fixes ptype.exp gdb testsuite regressions.

llvm-svn: 138869
 2011-08-31 18:04:31 +00:00
Eli Friedman
5d3814e0c4 64-bit atomic cmpxchg for ARM. 
llvm-svn: 138868
 2011-08-31 17:52:22 +00:00
Akira Hatanaka
6617606549 Fix typo. Patch by Liu. 
llvm-svn: 138866
 2011-08-31 17:49:04 +00:00
David Greene
a975ef3213 Compress Repeated Byte Output 
Emit a repeated sequence of bytes using .zero.  This saves an enormous
amount of asm file space for certain programs.

llvm-svn: 138864
 2011-08-31 17:30:56 +00:00
Jim Grosbach
a4c1e9d88a Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862
 2011-08-31 17:07:33 +00:00
Jakob Stoklund Olesen
ad3a292ff7 Put VMOVS widening under a command line option, off by default. 
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

llvm-svn: 138861
 2011-08-31 17:00:02 +00:00
Rafael Espindola
295e404961 Spelling and grammar fixes to problems found by Duncan. 
llvm-svn: 138858
 2011-08-31 16:43:33 +00:00
Eli Friedman
4fefb0a561 Make sure we don't crash when -miphoneos-version-min is specified on x86. Hopefully this will fix gcc testsuite failures. 
llvm-svn: 138856
 2011-08-31 16:19:51 +00:00
Eric Christopher
157bf8b08d Rework this conditional a bit. 
Patch by Sanjoy Das

llvm-svn: 138853
 2011-08-31 04:17:21 +00:00
Bruno Cardoso Lopes
5bd6e92f99 - Move all MOVSS and MOVSD patterns close to their definitions 
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

llvm-svn: 138851
 2011-08-31 03:04:20 +00:00
Bruno Cardoso Lopes
a9c2c56e13 Remove unnecessary AVX checks 
llvm-svn: 138850
 2011-08-31 03:04:14 +00:00
Bruno Cardoso Lopes
fe3f3344a6 Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS, 
whenever AVX is enabled.

llvm-svn: 138849
 2011-08-31 03:04:09 +00:00
Evan Cheng
bbabe9ff60 Fix (movhps load) lowering / pattern to match more cases. rdar://10050549 
llvm-svn: 138848
 2011-08-31 02:05:24 +00:00
Eli Friedman
928959bc52 Some minor cleanups for r138845. 
llvm-svn: 138846
 2011-08-31 00:41:05 +00:00
Eli Friedman
d71c865ae0 Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. 
llvm-svn: 138845
 2011-08-31 00:31:29 +00:00
Rafael Espindola
3bb0f9391c Remove the old tail duplication pass. It is not used and is unable to update 
ssa, so it has to be run really early in the pipeline. Any replacement
should probably use the SSAUpdater.

llvm-svn: 138841
 2011-08-30 23:03:45 +00:00
Owen Anderson
adac5b2109 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
llvm-svn: 138840
 2011-08-30 22:58:27 +00:00
Owen Anderson
a59d489162 Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. 
llvm-svn: 138837
 2011-08-30 22:15:17 +00:00
Benjamin Kramer
2ca7c2b2c7 Teach macho-dump to dump the uleb128s referred to by linkedit_data segments. 
llvm-svn: 138836
 2011-08-30 22:10:58 +00:00
Owen Anderson
9465c7fee0 Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. 
llvm-svn: 138835
 2011-08-30 22:10:03 +00:00
Owen Anderson
309c4b7ef6 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. 
llvm-svn: 138834
 2011-08-30 22:03:20 +00:00
Owen Anderson
d9dbde4a50 Clean up whitespace. 
llvm-svn: 138833
 2011-08-30 21:58:18 +00:00
Bill Wendling
1e8c335302 Fix off-by-one error Benjamin noticed. 
llvm-svn: 138832
 2011-08-30 21:23:24 +00:00
Owen Anderson
d3a9f00a58 Speculatively revert r138809 in an attempt to fix DragonEgg. 
llvm-svn: 138829
 2011-08-30 21:11:06 +00:00
Bill Wendling
569b9fee87 Enable compact unwind info by default. This only applies to Darwin when CFI is 
disabled.

llvm-svn: 138826
 2011-08-30 20:54:11 +00:00
Jeffrey Yasskin
8f36e758c2 Fix C++0x narrowing errors when char is unsigned. 
In the case of EDInstInfo, this would actually cause a bug when -1 became 255
and was then compared >=0 in llvm-mc/Disassembler.cpp.

llvm-svn: 138825
 2011-08-30 20:53:29 +00:00
Rafael Espindola
9db302e741 Adds support for variable sized allocas. For a variable sized alloca, 
code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.

Patch by Sanjoy Das.

llvm-svn: 138818
 2011-08-30 19:47:04 +00:00
Rafael Espindola
7721c15106 Adds a SelectionDAG node X86SegAlloca which will be custom lowered 
from DYNAMIC_STACKALLOC.

Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added.  They
will be custom emitted to inject the actual stack handling code.

Patch by Sanjoy Das.

llvm-svn: 138814
 2011-08-30 19:43:21 +00:00
Rafael Espindola
321e47cd0b Emit segmented-stack specific code into function prologues for 
X86. Modify the pass added in the previous patch to call this new
code.

This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required

Patch by Sanjoy Das.

llvm-svn: 138812
 2011-08-30 19:39:58 +00:00
Rafael Espindola
84f69a1992 Command line option to enable support for segmented stacks: 
-segmented-stacks.
Patch by Sanjoy Das!

llvm-svn: 138811
 2011-08-30 19:29:02 +00:00
Evan Cheng
91aa81acaa Follow up to r138791. 
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810
 2011-08-30 19:09:48 +00:00
Owen Anderson
3ec8beb8c8 When walking backwards to eliminate final stores to allocas at the end of a function, encountering an unrelated store should not cause us to give up like encountering a load does. 
llvm-svn: 138809
 2011-08-30 18:51:55 +00:00
Benjamin Kramer
de3a6db63c Teach macho-dump how to dump linkedit_data load commands. 
llvm-svn: 138807
 2011-08-30 18:33:37 +00:00
Roman Divacky
7ac1bc57f7 Set CR1EQ only when lowering vararg floating arguments (not any vararg 
arguments as before), unset CR1EQ otherwise.

llvm-svn: 138802
 2011-08-30 17:04:16 +00:00
James Molloy
a7a4266f83 Fix typos in SPUMCTargetDesc.h 
Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138799
 2011-08-30 07:27:02 +00:00
James Molloy
c537f89907 Fix typo in BlackfinFrameLowering.h 
Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138798
 2011-08-30 07:26:11 +00:00
James Molloy
21b255e052 Fix typo in MSP430MCTargetDesc.h. 
Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138797
 2011-08-30 07:24:47 +00:00
James Molloy
e841c9709a Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com) 
llvm-svn: 138796
 2011-08-30 07:23:29 +00:00
Bob Wilson
cc7b5b71eb Do not try to rematerialize a value from a partial definition. 
I don't currently have a good testcase for this; will try to get one
tomorrow.  <rdar://problem/10032939>

llvm-svn: 138794
 2011-08-30 05:36:02 +00:00
Evan Cheng
1eacb83316 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576

llvm-svn: 138791
 2011-08-30 01:34:54 +00:00
Jim Grosbach
187be92001 Revert 138781. It's not playing nicely with the immediate forms for ADC. 
llvm-svn: 138782
 2011-08-29 23:24:15 +00:00
Jim Grosbach
bc2d35e0ec Thumb2 assembler aliases for ADC/SBC w/o the .w suffix. 
llvm-svn: 138781
 2011-08-29 23:20:54 +00:00
Owen Anderson
4bd28c69c4 Add missing encoding information for some of the GPR<->FP register moves. 
llvm-svn: 138780
 2011-08-29 23:15:25 +00:00
Jim Grosbach
a1aa6a2e8b Thumb2 parsing and encoding for IT blocks. 
llvm-svn: 138773
 2011-08-29 22:24:09 +00:00
Eli Friedman
4d90e53381 Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. 
llvm-svn: 138768
 2011-08-29 21:15:46 +00:00
Owen Anderson
bbb6ed8264 Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. 
llvm-svn: 138766
 2011-08-29 21:14:19 +00:00
Bill Wendling
d9df43679c Fix grammar, noticed by Duncan. 
llvm-svn: 138764
 2011-08-29 21:03:12 +00:00
Owen Anderson
518e14771a Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding. 
llvm-svn: 138760
 2011-08-29 20:42:00 +00:00
Owen Anderson
44c24b13a3 addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. 
llvm-svn: 138758
 2011-08-29 20:16:50 +00:00
Nadav Rotem
43912ff374 Fixes following the CR by Chris and Duncan: 
Optimize chained bitcasts of the form A->B->A.
Undo r138722 and change isEliminableCastPair to allow this case.

llvm-svn: 138756
 2011-08-29 19:58:36 +00:00
Owen Anderson
e14d6edccc Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
llvm-svn: 138754
 2011-08-29 19:36:44 +00:00
Bill Wendling
6d2c747e53 Initialize CompactUnwindSection so that other targets won't use an uninitialized value. 
llvm-svn: 138752
 2011-08-29 18:25:59 +00:00
Eli Friedman
6d27cb5e01 Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
llvm-svn: 138751
 2011-08-29 18:23:02 +00:00
Benjamin Kramer
da658378b3 Dump with dbgs() instead of printf. 
llvm-svn: 138749
 2011-08-29 18:14:17 +00:00
Benjamin Kramer
442620e4c4 Make GCC happy by adding parens. 
llvm-svn: 138748
 2011-08-29 18:14:15 +00:00
Owen Anderson
3136f0a930 Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653. 
llvm-svn: 138746
 2011-08-29 17:59:41 +00:00
Bruno Cardoso Lopes
3a09888a72 Move non-intruction patterns to a more appropriate place! 
llvm-svn: 138744
 2011-08-29 17:51:24 +00:00
Owen Anderson
8719e2c1c3 Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
llvm-svn: 138739
 2011-08-29 17:17:09 +00:00
Andrew Trick
026fa4da72 Reapply r138695. Fix PassManager stack depths. 
Patch by Xiaoyi Guo!

llvm-svn: 138737
 2011-08-29 17:07:00 +00:00
Tobias Grosser
c6abc36833 Add AMDIL as valid target triple to LLVM. 
Submitted by: Villmow, Micah <Micah.Villmow@amd.com>

llvm-svn: 138734
 2011-08-29 15:44:55 +00:00
Nicolas Geoffray
74b006fe71 Remove premature previous commit. 
llvm-svn: 138725
 2011-08-28 14:52:51 +00:00
Duncan Sands
1a69e0119a Fix PR5329: pay attention to constructor/destructor priority 
when outputting them.  With this, the entire LLVM testsuite
passes when built with dragonegg.

llvm-svn: 138724
 2011-08-28 13:17:22 +00:00
Nicolas Geoffray
d30e51ca07 Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does. 
llvm-svn: 138723
 2011-08-28 13:07:57 +00:00
Nadav Rotem
6280c8eecc Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X. 
llvm-svn: 138722
 2011-08-28 11:51:08 +00:00
Nick Lewycky
a28dc138a1 Fix integer overflow bug in raw_ostream::write. This showed up as a 
non-deterministic crash in the test suite. Fixes PR10055!

llvm-svn: 138717
 2011-08-28 03:30:02 +00:00
Benjamin Kramer
6411b8f81a Silence GCC warnings and make an array const. 
llvm-svn: 138706
 2011-08-27 17:36:14 +00:00
Benjamin Kramer
70ba1d6ab4 Report failure if there are less bytes than requested in a MemoryObject. 
Before we just left the remaining bytes uninitialized. This is another step in making llvm valgrind-clean again.

llvm-svn: 138705
 2011-08-27 07:45:46 +00:00
Bill Wendling
b0412973be Auto upgrade the old EH scheme to use the new one. This is on a trial basis. If 
things to disasterously over night, this can be reverted.

llvm-svn: 138702
 2011-08-27 06:11:03 +00:00
Andrew Trick
65754eb3f7 Reverting r138695 to see if it fixes clang self host. 
llvm-svn: 138701
 2011-08-27 06:10:16 +00:00
Bill Wendling
607b3c3898 Only delete instructions once. 
llvm-svn: 138700
 2011-08-27 06:10:02 +00:00
Bill Wendling
a23e3f4f85 These splits should be done whether they are critical edges or not. 
llvm-svn: 138697
 2011-08-27 04:40:37 +00:00
Andrew Trick
e38568bc07 Fix PassManager stack depths. 
Patch by Xiaoyi Guo!

llvm-svn: 138695
 2011-08-27 02:11:03 +00:00
Owen Anderson
fd21da3506 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
llvm-svn: 138675
 2011-08-26 23:32:08 +00:00
Owen Anderson
9b85a034c9 Correct encoding of BL with immediate offset. 
llvm-svn: 138673
 2011-08-26 22:54:51 +00:00
Jim Grosbach
fb526fdc70 ARM assembly parsing tweak for pldw. 
llvm-svn: 138669
 2011-08-26 22:21:51 +00:00
Owen Anderson
f47325fc54 Spelling fail. 
llvm-svn: 138667
 2011-08-26 21:47:57 +00:00
Jim Grosbach
6071776c8a Thumb2 assembler parsing and encoding of IT instruction. 
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.

llvm-svn: 138665
 2011-08-26 21:43:41 +00:00
Bill Wendling
21d93fcc0e Update the dominator tree with the correct dominator for the new 'unwind' block. 
llvm-svn: 138664
 2011-08-26 21:36:12 +00:00
Eli Friedman
9f95c7d381 Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. 
llvm-svn: 138660
 2011-08-26 21:21:21 +00:00
Bill Wendling
88b318ca91 Split the landing pad block only if it's a critical edge. Also intelligently 
split it in the other place where we're splitting critical edges.

llvm-svn: 138658
 2011-08-26 21:18:55 +00:00
Owen Anderson
e7857867d6 Fix ARM codegen breakage caused by r138653. 
llvm-svn: 138657
 2011-08-26 21:12:37 +00:00
Eric Christopher
09fd6a961c Whitespace and 80-col. 
llvm-svn: 138654
 2011-08-26 21:02:40 +00:00
Owen Anderson
af51fd9868 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
llvm-svn: 138653
 2011-08-26 20:43:14 +00:00
Bill Wendling
400ec8bd8f Don't sink landingpad instructions during ind-var simplification. 
llvm-svn: 138651
 2011-08-26 20:40:15 +00:00
Owen Anderson
7658e342c3 Update for feedback from Jim. 
llvm-svn: 138642
 2011-08-26 19:39:26 +00:00
Benjamin Kramer
b279f20034 ARMDisassembler: Always return a size, even when disassembling fails. 
This should fix PR10772.

llvm-svn: 138636
 2011-08-26 18:21:36 +00:00
Owen Anderson
86b11d01eb Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
llvm-svn: 138635
 2011-08-26 18:09:22 +00:00
Kalle Raiskila
914b04c32b Don't insert branch hint lables that are never used. 
llvm-svn: 138630
 2011-08-26 10:14:56 +00:00
Owen Anderson
87c906dabf Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. 
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.

llvm-svn: 138625
 2011-08-26 06:19:51 +00:00
Craig Topper
b20cee1e19 Fix disassembling of VCVTSD2SI 
llvm-svn: 138623
 2011-08-26 04:49:29 +00:00
Andrew Trick
504187a152 LoopInfo::updateUnloop fix, and verify Block->Loop maps. 
Fixes an oversight, and adds verification to catch it in the unloop.ll tests.

llvm-svn: 138622
 2011-08-26 03:06:34 +00:00
Eli Friedman
802dd20495 Atomic load/store on ARM/Thumb. 
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.

llvm-svn: 138621
 2011-08-26 02:59:24 +00:00
Benjamin Kramer
0e1a09f38c Address review comments. 
- Reword comments.
- Allow undefined behavior interfering with undefined behavior.
- Add address space checks.

llvm-svn: 138619
 2011-08-26 02:25:55 +00:00
Benjamin Kramer
dc1c57af91 SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between. 
In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.

This shrinks the size of a Release clang by 16k on x86_64.

llvm-svn: 138618
 2011-08-26 01:22:29 +00:00
Bill Wendling
0eb4df639e Look at only the terminators of the basic block. Also, if we're using the new EH 
scheme, return 'true' so that it doesn't try to run the old EH scheme's fixup on
the new code.

llvm-svn: 138605
 2011-08-25 23:48:11 +00:00
Bill Wendling
546c7a05de Initial check in that will auto-upgrade the old EH scheme to the new EH scheme. 
This upgrade suffers from the problems of the old EH scheme - i.e., that the
calls to llvm.eh.exception() and llvm.eh.selector() can wander off and get
lost. It makes a valiant effort to reclaim these little lost lambs.

This is a first draft, so it hasn't yet been hooked up to the parser.

llvm-svn: 138602
 2011-08-25 23:22:40 +00:00
Bruno Cardoso Lopes
e6119d18de Do the same as r138461. Mark VZEROALL as clobbering all YMM registers 
llvm-svn: 138592
 2011-08-25 22:23:58 +00:00
Nick Lewycky
59cb9e0d85 Remove stray fullstop. 
llvm-svn: 138589
 2011-08-25 21:46:20 +00:00
Bruno Cardoso Lopes
5b3d2c9e17 Add support for AVX 256-bit version of MOVDDUP! 
llvm-svn: 138588
 2011-08-25 21:40:37 +00:00
Bruno Cardoso Lopes
dedd2ffa0b Make isMOVDDUP mask check more strict and update comments! 
llvm-svn: 138587
 2011-08-25 21:40:34 +00:00
Owen Anderson
d387b48b0b Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
llvm-svn: 138575
 2011-08-25 18:30:18 +00:00
Benjamin Kramer
d710063e1e Intel family 6 model 44 is Gulftown/Westmere-EP and doesn't have AVX. 
llvm-svn: 138573
 2011-08-25 18:05:56 +00:00
Andrew Trick
0dd0ae11f8 ARM fix for missing implicit operands on ldmia_ret. 
rdar://10005094: miscompile of 176.gcc

llvm-svn: 138568
 2011-08-25 17:50:53 +00:00
Andrew Trick
cd6126c2ab whitespace 
llvm-svn: 138566
 2011-08-25 17:40:54 +00:00
Jim Grosbach
e8641a3bc7 Explicitly disallow predication in Thumb1 assembly. 
llvm-svn: 138562
 2011-08-25 17:23:55 +00:00
Craig Topper
a6085b9757 Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678. 
llvm-svn: 138553
 2011-08-25 08:11:01 +00:00
Craig Topper
06ed6cb856 Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723. 
llvm-svn: 138551
 2011-08-25 06:57:46 +00:00
Bill Wendling
1eec5affec LSR wants to split the landing pad's critical edge. Let it do it, but use the 
proper function to do it.

llvm-svn: 138550
 2011-08-25 05:55:40 +00:00
Benjamin Kramer
fc1e6fbc69 Initialize member variable. 
llvm-svn: 138548
 2011-08-25 04:04:18 +00:00
Bruno Cardoso Lopes
5d34219953 Add support for 256-bit versions of VSHUFPD and VSHUFPS. 
llvm-svn: 138546
 2011-08-25 02:58:26 +00:00
Bruno Cardoso Lopes
ccffe56b5d Add memory version of SHUFPD to mask decoding! 
llvm-svn: 138545
 2011-08-25 02:58:21 +00:00
Evan Cheng
7de8defb9c Hide -global-merge option. 
llvm-svn: 138540
 2011-08-25 01:22:49 +00:00
Bill Wendling
bc21b6ec6d When inserting new instructions, use getFirstInsertionPt instead of 
getFirstNonPHI so that it will skip over the landingpad instructions as well.

llvm-svn: 138537
 2011-08-25 01:08:34 +00:00
Evan Cheng
6c89acc6d1 Add a command line option to disable global merge pass. 
llvm-svn: 138536
 2011-08-25 01:00:36 +00:00
Evan Cheng
9a2607f3b9 Remove a out-of-place comment. 
llvm-svn: 138534
 2011-08-25 00:54:42 +00:00
Bruno Cardoso Lopes
dfa5cf4620 Create a section for non-instructions patterns in the beginning of the 
file, and move more code around!

llvm-svn: 138521
 2011-08-24 23:18:11 +00:00
Bruno Cardoso Lopes
719b357628 Move code around! 
llvm-svn: 138520
 2011-08-24 23:18:09 +00:00
Bruno Cardoso Lopes
3824b766ac Organize UNPCK* patterns, also add remaining for AVX. 
llvm-svn: 138519
 2011-08-24 23:18:06 +00:00
Bruno Cardoso Lopes
82c8bc7efd Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate 
the missing ones for AVX.

llvm-svn: 138518
 2011-08-24 23:18:04 +00:00
Bruno Cardoso Lopes
d315a6b6e6 Organize and tidy up MOVDDUP section. Also update comments! 
llvm-svn: 138517
 2011-08-24 23:18:02 +00:00
Bruno Cardoso Lopes
762fb13cc9 Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the 
pattern for 128-bit AVX mode.

llvm-svn: 138516
 2011-08-24 23:17:59 +00:00
Bruno Cardoso Lopes
d62766849f Move all PSHUF* patterns close to the PSHUF* definitions. Also be 
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!

llvm-svn: 138515
 2011-08-24 23:17:57 +00:00
Bruno Cardoso Lopes
122f7cfc92 Move all SHUFP* patterns close to the SHUFP* definitions. Also be 
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!

llvm-svn: 138514
 2011-08-24 23:17:55 +00:00
Owen Anderson
8a6cf48f0e Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. 
llvm-svn: 138507
 2011-08-24 22:40:22 +00:00
Eli Friedman
b6597a2e70 Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. 
llvm-svn: 138505
 2011-08-24 22:33:28 +00:00
Evan Cheng
7bfc442b2d Some autoconf tests use module level inline asm to test compiler's handling of 
.cfi_startproc. e.g. libffi:

 $ cat confopt.c 
asm (".cfi_startproc\n\t.cfi_endproc");

int main () { return 0; }

Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.

rdar://10017184

llvm-svn: 138504
 2011-08-24 22:31:37 +00:00
Jim Grosbach
76b50c3819 ARM asm backend initialize isThumbMode based on target triple. 
llvm-svn: 138501
 2011-08-24 22:27:35 +00:00
Jim Grosbach
7374e16344 Thumb .n mnemonic qualifiers can be ignored for now. 
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.

llvm-svn: 138500
 2011-08-24 22:19:48 +00:00
Jim Grosbach
effaf1e15d Thumb parsing and encoding for SUB (SP minu immediate). 
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494
 2011-08-24 21:42:27 +00:00
Owen Anderson
3732f1644b Be careful not to walk off the end of the operand info list while updating VFP predicates. 
llvm-svn: 138492
 2011-08-24 21:35:46 +00:00
Jim Grosbach
b2b155a93f Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
 2011-08-24 21:22:15 +00:00
Eli Friedman
e4cd816e7b Fix whitespace. 
llvm-svn: 138487
 2011-08-24 21:17:30 +00:00
Bill Wendling
15062f817a Skip the landingpad instruction when determining the insertion point. 
llvm-svn: 138481
 2011-08-24 21:06:46 +00:00
Eli Friedman
6f95a6ae1b Basic x86 code generation for atomic load and store instructions. 
llvm-svn: 138478
 2011-08-24 20:50:09 +00:00
Bill Wendling
0301dcfde8 Use getFirstInsertionPt instead of getFirstNonPHI so that it skips to the proper 
insertion place.

llvm-svn: 138473
 2011-08-24 20:28:43 +00:00
Nadav Rotem
43673d6d0b Implement Constant::isAllOnesValue(). Fix ConstantFolding to use the new api. 
llvm-svn: 138469
 2011-08-24 20:18:38 +00:00
Jim Grosbach
ccee1ff0f5 When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate. 
rdar://10015134

llvm-svn: 138467
 2011-08-24 20:06:14 +00:00
Bruno Cardoso Lopes
734febce18 Mark VZEROALL as clobbering all YMM registers 
llvm-svn: 138461
 2011-08-24 18:48:33 +00:00
Jim Grosbach
9ae0de4db3 Add missing explicit writeback operand to tSTMIA_UPD. 
rdar://10014745

llvm-svn: 138457
 2011-08-24 18:19:42 +00:00
Evan Cheng
420bf5446c Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.

llvm-svn: 138450
 2011-08-24 18:08:43 +00:00
Rafael Espindola
e864ec28bd Fix a crashing bug in SplitBlock when it is called on a block with no 
dominator information even though dominators were previously computed.

Patch by Nick Sumner.

llvm-svn: 138449
 2011-08-24 18:07:01 +00:00
Jim Grosbach
bf012c3f19 Thumb add SP assembly syntax fix. 
llvm-svn: 138448
 2011-08-24 18:04:27 +00:00
Jim Grosbach
b33129ebad Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. 
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.

llvm-svn: 138445
 2011-08-24 17:46:13 +00:00
Owen Anderson
ee4d781cd3 Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. 
llvm-svn: 138443
 2011-08-24 17:21:43 +00:00
Jim Grosbach
6d81544e1a Tidy up. Trailing whitespace. 
llvm-svn: 138437
 2011-08-24 16:44:17 +00:00
Richard Osborne
6b6b0b535d Add Uses=[SP] to call instructions. This fixes a miscompilation with a 
variable sized alloca.

llvm-svn: 138433
 2011-08-24 13:32:43 +00:00
Craig Topper
1da38a34a6 Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711. 
llvm-svn: 138427
 2011-08-24 06:14:18 +00:00
Bill Wendling
2cd76365f2 Add the sentinal "no handle" value to the ResumeInst. 
A value of -1 at a call site tells the personality function that this call isn't
handled by the current function. Since the ResumeInsts are converted to calls to
_Unwind_SjLj_Resume, add a (volatile) store of -1 to its 'call site'.

llvm-svn: 138416
 2011-08-24 00:00:23 +00:00
Bill Wendling
79b1f95f89 Don't replace *all* uses with the new stuff. 
This is not necessarily the first or dominating use of the EH values. The IR
breaks if it's not. So replace the specific value in the instruction with the
new value.

llvm-svn: 138406
 2011-08-23 22:55:03 +00:00
Bill Wendling
acd21d7162 Look at the end of the entry block for an invoke. 
The invoke could be at the end of the entry block. If it's the only one, then we
won't process all of the landingpad instructions correctly. This code is
currently ugly, but should be made much nicer once the new EH switch is thrown.

llvm-svn: 138397
 2011-08-23 22:20:16 +00:00
Bruno Cardoso Lopes
8959b54713 Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit 
permutations. Also tidy up some patterns and make them close to their
instruction definition!

llvm-svn: 138392
 2011-08-23 22:06:37 +00:00
Bill Wendling
3de8a041b7 A landingpad instruction is neither folded nor dead. 
llvm-svn: 138387
 2011-08-23 21:33:05 +00:00
Jim Grosbach
b65ec7c64f Move ARM frame-unwinding EHABI handling a touch earlier. 
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.

llvm-svn: 138386
 2011-08-23 21:32:34 +00:00
Jim Grosbach
3832c5ac34 [SU]XT[BH] are only available on ARMv6 and up. 
llvm-svn: 138373
 2011-08-23 20:53:08 +00:00
Nate Begeman
87ffb9491b Add some useful accessors to c++ api that appear to be missing from the c api 
llvm-svn: 138371
 2011-08-23 20:27:46 +00:00
Evan Cheng
ed13551c1d Some refactoring so TargetRegistry.h no longer has to include any files 
from MC.

llvm-svn: 138367
 2011-08-23 20:15:21 +00:00
Eric Christopher
aa4993b9aa Revert "Address Duncan's CR request:" 
This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340)

Conflicts:

	test/Transforms/InstCombine/bitcast.ll

llvm-svn: 138366
 2011-08-23 20:11:10 +00:00
Jim Grosbach
1f5b8e9044 Thumb parsing and encoding for SVC. 
llvm-svn: 138360
 2011-08-23 19:49:10 +00:00
Evan Cheng
ff0339eccc Fix 80 col violations. 
llvm-svn: 138356
 2011-08-23 19:17:21 +00:00
Nick Lewycky
11874a4e0a PerformSubCombine to work on integers larger than i128. Fixes a crasher. 
llvm-svn: 138354
 2011-08-23 19:01:24 +00:00
Jim Grosbach
f9bc99b518 Thumb parsing and encoding for tSTRspi. 
llvm-svn: 138348
 2011-08-23 18:39:41 +00:00
Jim Grosbach
3b20e779cd Thumb parsing and encoding for STM. 
llvm-svn: 138345
 2011-08-23 18:15:37 +00:00
Jim Grosbach
709c1644b0 Factor low reg checking into a helper function. 
llvm-svn: 138344
 2011-08-23 18:13:04 +00:00
Owen Anderson
3de2d7656d Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
llvm-svn: 138341
 2011-08-23 17:51:38 +00:00
Nadav Rotem
d449bc9bff Address Duncan's CR request: 
1. Cleanup the tests in ConstantFolding.cpp
2. Implement isAllOnes for Constant, ConstantFP, ConstantVector

llvm-svn: 138340
 2011-08-23 17:48:43 +00:00
Owen Anderson
4ae835d7c9 Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. 
llvm-svn: 138339
 2011-08-23 17:45:18 +00:00
Jim Grosbach
6ada94c011 Clean up Thumb load/store multiple definitions. 
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.

llvm-svn: 138338
 2011-08-23 17:41:15 +00:00
Owen Anderson
9d5074746f Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing. 
llvm-svn: 138337
 2011-08-23 17:37:32 +00:00
Ivan Krasin
aa3c2057c5 This patch adds support of le32 pseudo-cpu that stands for generic 
32-bit little-endian CPU. Used by PNaCl and Emscripten.

llvm-svn: 138335
 2011-08-23 16:59:00 +00:00
Craig Topper
67b22aedb4 Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712. 
llvm-svn: 138321
 2011-08-23 04:36:33 +00:00
NAKAMURA Takumi
6b729bec35 lib/Support/Windows/Windows.h: Update required IE ver. 0x0600 should be enough for Windows XP. 
llvm-svn: 138319
 2011-08-23 03:49:11 +00:00
Bruno Cardoso Lopes
8024703a16 Introduce a pass to insert vzeroupper instructions to avoid AVX to 
SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

llvm-svn: 138317
 2011-08-23 01:14:17 +00:00
Jim Grosbach
d299db0857 Thumb parsing and encoding for SBC. 
llvm-svn: 138311
 2011-08-22 23:55:58 +00:00
Jim Grosbach
5ae40d73a6 Thumb parsing and encoding for RSB. 
llvm-svn: 138308
 2011-08-22 23:47:13 +00:00
Owen Anderson
33f3f4ec2a Reject invalid imod values in t2CPS instructions. 
llvm-svn: 138306
 2011-08-22 23:44:04 +00:00
Bill Wendling
02e66489db Split the landing pad's edge. Then for all uses of a landingpad instruction's 
value, we insert a load of the exception object and selector object from memory,
which is where it actually resides. If it's used by a PHI node, we follow that
to where it is being used. Eventually, all landingpad instructions should have
no uses. Any PHI nodes that were associated with those landingpads should be
removed.

llvm-svn: 138302
 2011-08-22 23:38:40 +00:00
Owen Anderson
d5b7d73696 t2SMLAD is a four-register instruction, not a three-register one. 
llvm-svn: 138301
 2011-08-22 23:31:45 +00:00
Owen Anderson
c395a07c42 Correct operand naming of t2USAT16 to allow proper decoding. 
llvm-svn: 138300
 2011-08-22 23:27:47 +00:00
Jim Grosbach
a59709ec01 Revert r138278 now that r138289 has fixed the root issue. 
llvm-svn: 138299
 2011-08-22 23:25:48 +00:00
Owen Anderson
9e750147fb Match operand naming to allow correct decoding of t2LDRSH_POST. 
llvm-svn: 138298
 2011-08-22 23:22:05 +00:00
Jim Grosbach
54234257fa Improve error checking for tPUSH and tPOP register lists. 
llvm-svn: 138295
 2011-08-22 23:17:34 +00:00
Owen Anderson
1cc1a1cb6a Match operand names to provide correct decoding for Thumb2 SMULL. 
llvm-svn: 138294
 2011-08-22 23:16:48 +00:00
Owen Anderson
b400952853 Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. 
llvm-svn: 138292
 2011-08-22 23:10:16 +00:00
Ivan Krasin
47d91d86ca Add NativeClient support to Triple::ParseOS. 
llvm-svn: 138291
 2011-08-22 23:08:53 +00:00
Evan Cheng
a828915f91 Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-) 
llvm-svn: 138289
 2011-08-22 23:04:56 +00:00
Jim Grosbach
ec3958e68e Thumb assemmbly parsing diagnostic improvements for LDM. 
llvm-svn: 138287
 2011-08-22 23:01:07 +00:00
Benjamin Kramer
bd13a6a319 X86: Add some operand types required to identify calls. 
llvm-svn: 138285
 2011-08-22 22:55:32 +00:00
Jim Grosbach
d28882c799 Temporarilly mark tMUL as not commutable. 
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.

llvm-svn: 138278
 2011-08-22 22:00:18 +00:00
Owen Anderson
a2231fad2e Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. 
llvm-svn: 138273
 2011-08-22 21:34:00 +00:00
Bruno Cardoso Lopes
8007165688 Add support for breaking 256-bit int VETCC into two 128-bit ones, 
avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.

llvm-svn: 138271
 2011-08-22 20:31:04 +00:00
Bruno Cardoso Lopes
23ff325f5b Add 128-bit AVX codegen for PCMP* family of integer instructions 
llvm-svn: 138270
 2011-08-22 20:31:00 +00:00
Owen Anderson
39d3f234f7 Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
llvm-svn: 138269
 2011-08-22 20:27:12 +00:00
Jordy Rose
62453a17f9 Make DynamicLibrary thread-safe w/r/t call to dlerror() after dlopen(). PR10718 
llvm-svn: 138260
 2011-08-22 19:01:52 +00:00
Jim Grosbach
303d34cede Tighten up ARM reglist validation a bit. 
llvm-svn: 138258
 2011-08-22 18:50:36 +00:00
Bill Wendling
675b27b3f9 Some whitespace fixes and #include reordering. 
llvm-svn: 138256
 2011-08-22 18:44:49 +00:00
Owen Anderson
926f360e53 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
llvm-svn: 138255
 2011-08-22 18:42:13 +00:00
Nick Lewycky
0f0a595ec9 Be less redundant. 
llvm-svn: 138252
 2011-08-22 18:26:12 +00:00
Owen Anderson
816f5524f8 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
llvm-svn: 138251
 2011-08-22 18:22:06 +00:00
Jim Grosbach
a5715c60b5 Clean up predicates on ARM target instruction aliases. 
llvm-svn: 138249
 2011-08-22 18:04:24 +00:00
Owen Anderson
59178665b5 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
llvm-svn: 138246
 2011-08-22 17:56:58 +00:00
Dan Gohman
a6ceaf82c5 Add a comment. 
llvm-svn: 138243
 2011-08-22 17:29:37 +00:00
Dan Gohman
9619488506 Constant pointers to objects don't need reference counting. 
llvm-svn: 138242
 2011-08-22 17:29:11 +00:00
Benjamin Kramer
c767059573 PathV2: Handle more reserved filenames on windows. 
Patch by Aaron Ballman!

llvm-svn: 138213
 2011-08-20 21:36:38 +00:00
Jim Grosbach
a6e1ed8f2b Fix AsmParser binary precedence for shift operators. 
rdar://9976729

llvm-svn: 138208
 2011-08-20 16:24:13 +00:00
Nadav Rotem
1dc1eb1ae0 Add constant folding support for bitcasts of splat vectors to integers. 
llvm-svn: 138206
 2011-08-20 14:02:29 +00:00
NAKAMURA Takumi
e2ae0063cf lib/Support/CrashRecoveryContext.cpp: Add Win32 support to CrashRecoveryContext. Thanks to Aaron Ballman! 
llvm-svn: 138199
 2011-08-20 06:35:36 +00:00
NAKAMURA Takumi
c5e4d7690d lib/Support/Windows/Windows.h: Require at least Windows XP(5.1) API. We will not support Windows 2000 any more. 
llvm-svn: 138198
 2011-08-20 06:35:31 +00:00
Benjamin Kramer
1adacca2e5 Cast through intptr_t, ISO C++ requires it. 
llvm-svn: 138186
 2011-08-20 02:22:42 +00:00
Chad Rosier
3c596dbe51 Remove the VMOVQQ pseudo instruction. 
llvm-svn: 138177
 2011-08-20 00:52:40 +00:00
Chad Rosier
0d49bb37fb Remove VMOVQQQQ pseudo instruction. 
llvm-svn: 138174
 2011-08-20 00:40:14 +00:00
Jakob Stoklund Olesen
ee6264c790 Add <imp-def> operands to QQ and QQQQ stack loads. 
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

llvm-svn: 138164
 2011-08-20 00:17:45 +00:00
Chad Rosier
55c57f07dd VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. 
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

llvm-svn: 138163
 2011-08-20 00:17:25 +00:00
Bill Wendling
bfc0c6c1de If we're splitting the landing pad block and assigning it only one predecessor, 
then don't split it a second time, since that block will be dead.

llvm-svn: 138153
 2011-08-19 23:46:30 +00:00
Devang Patel
e4127d626e Do not use named md nodes to track variables that are completely optimized. This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly. 
llvm-svn: 138145
 2011-08-19 23:28:12 +00:00
Jim Grosbach
be94868d66 Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
 2011-08-19 23:24:36 +00:00
Akira Hatanaka
02cff5ae2d Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not 
needed for Mips32.

llvm-svn: 138132
 2011-08-19 22:59:00 +00:00
Jim Grosbach
326e78be7a Thumb assembly parsing and encoding for NEG. 
llvm-svn: 138131
 2011-08-19 22:51:03 +00:00
Benjamin Kramer
cca4305d51 Roll back the rest of r126557. It's a hack that will break in some obscure cases. 
llvm-svn: 138130
 2011-08-19 22:39:31 +00:00
Jim Grosbach
3cb3facb8f Fix NEG alias 
llvm-svn: 138125
 2011-08-19 22:30:58 +00:00
Jim Grosbach
a97661cac4 Be more lenient on tied operand matching for MUL. 
llvm-svn: 138124
 2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes
9979e44f1b Re-write part of VEX encoding logic, to be more easy to read! Also fix 
a bug and add a testcase!

llvm-svn: 138123
 2011-08-19 22:27:29 +00:00
Jim Grosbach
5481e15390 Update tests. 
llvm-svn: 138116
 2011-08-19 22:19:48 +00:00
Jim Grosbach
8e2d4a63dc Thumb assembly parsing and encoding for MUL. 
llvm-svn: 138108
 2011-08-19 22:07:46 +00:00
Bill Wendling
31d80032c6 The landingpad instruction isn't dead simply because it's value isn't used. 
llvm-svn: 138102
 2011-08-19 21:52:06 +00:00
Nick Lewycky
97d6254420 Eli points out that this is what report_fatal_error() is for. 
llvm-svn: 138091
 2011-08-19 21:45:19 +00:00
Jim Grosbach
cf35d78b16 Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach
8952a2e87e Tidy up. Tab character. 
llvm-svn: 138072
 2011-08-19 20:30:19 +00:00
Nick Lewycky
ed042d8794 This is not actually unreachable, so don't use llvm_unreachable for it. Since 
the intent seems to be to terminate even in Release builds, just use abort()
directly.

If program flow ever reaches a __builtin_unreachable (which llvm_unreachable is
#define'd to on newer GCCs) then the program is undefined.

llvm-svn: 138068
 2011-08-19 20:14:27 +00:00
Jim Grosbach
8e03b52754 Tab characters. 
llvm-svn: 138066
 2011-08-19 19:41:46 +00:00
Jim Grosbach
7d707b4fb1 Thumb assembly parsing and encoding for LSL(immediate). 
llvm-svn: 138063
 2011-08-19 19:29:25 +00:00
Jim Grosbach
9174714826 Thumb assembly parsing and encoding for LDRSB and LDRSH. 
llvm-svn: 138061
 2011-08-19 19:17:58 +00:00
Jim Grosbach
27001ee5fd Thumb assembly parsing and encoding for LDRH. 
llvm-svn: 138060
 2011-08-19 18:55:51 +00:00
Jim Grosbach
36fb75a109 Thumb assembly parsing and encoding for LDRB. 
llvm-svn: 138059
 2011-08-19 18:49:59 +00:00
Sean Callanan
e6d9e9ed24 Fixed a memory bug in the MCDisassembler where 
MCParsedAsmOperand objects were being leaked.

llvm-svn: 138053
 2011-08-19 18:23:06 +00:00
Jim Grosbach
6d9a3e68bb Thumb assembly parsing and encoding for LDR(literal). 
llvm-svn: 138052
 2011-08-19 18:20:48 +00:00
Jim Grosbach
d429ab26cb Thumb assembly parsing and encoding for LDR(immediate) form T2. 
llvm-svn: 138050
 2011-08-19 18:13:48 +00:00
Jim Grosbach
ce30deef35 Use helper function to check for low registers. 
llvm-svn: 138048
 2011-08-19 17:57:22 +00:00
Jim Grosbach
35b968afdc Thumb assembly parsing and encoding for LDR(immediate) form T1. 
llvm-svn: 138047
 2011-08-19 17:55:24 +00:00
Jim Grosbach
b70142a801 Add explanatory comment. 
llvm-svn: 138042
 2011-08-19 16:52:32 +00:00
Kalle Raiskila
a86e3cd02c Have SPU backend use the external TCE scheduler, if the library is loaded as a 
module.

Patch by Pekka Jääskeläinen.

llvm-svn: 138037
 2011-08-19 10:50:24 +00:00
Craig Topper
f68d77215d Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler 
llvm-svn: 138034
 2011-08-19 05:28:50 +00:00
Bruno Cardoso Lopes
306110c29a Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the 
implementation!

llvm-svn: 138029
 2011-08-19 02:23:56 +00:00
Jakob Stoklund Olesen
d65435a076 Add llc flags to disable machine DCE and CSE. 
This is useful for unit tests.

llvm-svn: 138028
 2011-08-19 02:05:35 +00:00
Benjamin Kramer
0d60a5573c Make a bunch of symbols private. 
llvm-svn: 138025
 2011-08-19 01:42:18 +00:00
Benjamin Kramer
c5a90f3683 C API functions must be able to see their extern "C" definitions, or it will be impossible to call them from C. 
llvm-svn: 138022
 2011-08-19 01:36:54 +00:00
Jakob Stoklund Olesen
d18e1ee34f Don't treat a partial <def,undef> operand as a read. 
Normally, a partial register def is treated as reading the
super-register unless it also defines the full register like this:

  %vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def>

This patch also uses the <undef> flag on partial defs to recognize
non-reading operands:

  %vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit

This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses
would treat a coalesced copy as still reading the register, extending
the live range artificially.

My test case only works when I disable DCE so a dead copy is left for
RegisterCoalescer, so I am not including it.

<rdar://problem/9967101>

llvm-svn: 138018
 2011-08-19 00:30:17 +00:00
Dan Gohman
c5d64c76e0 Track a retain+release nesting level independently of the 
known-incremented level, because the two concepts can be used
to prove the saftey of a retain+release removal in different
ways.

llvm-svn: 138016
 2011-08-19 00:26:36 +00:00
Bill Wendling
4eead96931 Intelligently split the landing pad block. 
We have to be careful when splitting the landing pad block, because the
landingpad instruction is required to remain as the first non-PHI of an invoke's
unwind edge. To retain this, we split the block into two blocks, moving the
predecessors within the loop to one block and the remaining predecessors to the
other. The landingpad instruction is cloned into the new blocks.

llvm-svn: 138015
 2011-08-19 00:09:22 +00:00
Bill Wendling
3079e1ccda Add SplitLandingPadPredecessors(). 
SplitLandingPadPredecessors is similar to SplitBlockPredecessors in that it
splits the current block and attaches a set of predecessors to the new basic
block. However, it differs from SplitBlockPredecessors in that it's specifically
designed to handle landing pad blocks.

Two new basic blocks are created: one that is has the vector of predecessors as
its predecessors and one that has the remaining predecessors as its
predecessors. Those two new blocks then receive a cloned copy of the landingpad
instruction from the original block. The landingpad instructions are joined in a
PHI, etc. Like SplitBlockPredecessors, it updates the LLVM IR, AliasAnalysis,
DominatorTree, DominanceFrontier, LoopInfo, and LCCSA analyses.

llvm-svn: 138014
 2011-08-19 00:05:40 +00:00
Bruno Cardoso Lopes
0d458d4bb3 Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands 
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.

Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.

There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)

llvm-svn: 138012
 2011-08-18 23:59:21 +00:00
Devang Patel
9fa42d022b There is no need to add file as context for subroutine type. The subroutine type does not need any context. 
llvm-svn: 138010
 2011-08-18 23:50:57 +00:00
Renato Golin
300ff0b415 add the comments of each declaration follow it, making it easier to read and compare to GCC's result. 
llvm-svn: 138009
 2011-08-18 23:43:14 +00:00
Bill Wendling
ba667af404 Use 'getFirstInsertionPt' when trying to insert new instructions during LICM. 
llvm-svn: 138008
 2011-08-18 23:42:36 +00:00
Akira Hatanaka
163382894e Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Devang Patel
68d2232bfe Eliminate unnecessary forwarding function. 
llvm-svn: 138006
 2011-08-18 23:17:55 +00:00
Ivan Krasin
311fcc9b92 Add NativeClient operating system support. 
This patch adds support of NativeClient (*-*-nacl) OS support to LLVM.
It's already supported in autoconf/config.sub.

The motivation for this change is to start upstreaming PNaCl work. The
whole set of patches include llvm backends (i686, x86_64, ARM),
llvm-gcc (probably, would not be upstreamed because it's deprecated)
and clang (the work has been just started, the amount of changes is
going to be low and the most of the work is expected to be done close
to the mainline).

llvm-svn: 138005
 2011-08-18 22:54:21 +00:00
Owen Anderson
421e30086e STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.

llvm-svn: 138003
 2011-08-18 22:47:44 +00:00
Owen Anderson
d113a59074 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
llvm-svn: 138000
 2011-08-18 22:31:17 +00:00
Devang Patel
0253beee5c Add new DIE into the map asap. 
llvm-svn: 137998
 2011-08-18 22:21:50 +00:00
Owen Anderson
7f3f0234a2 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. 
llvm-svn: 137997
 2011-08-18 22:15:25 +00:00
Owen Anderson
d121f0e77c Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
 2011-08-18 22:11:02 +00:00
Ivan Krasin
338df71d60 FastISel: avoid function calls between the materialization of the constant and its use. 
llvm-svn: 137993
 2011-08-18 22:06:10 +00:00
Jim Grosbach
7ecefeb594 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Dan Gohman
323adc0a3a Make it clear that this code is iterating in reverse order through the array. 
llvm-svn: 137985
 2011-08-18 21:27:42 +00:00
Bill Wendling
fef33f1d24 Revert r137871. The loop simplify pass should require all exits from a loop that 
aren't from an indirect branch need to be dominated by the loop header.

llvm-svn: 137981
 2011-08-18 21:10:01 +00:00
Bill Wendling
f3c0fabac7 Split out the updating of PHI nodes after splitting the BB into a separate 
function.

llvm-svn: 137979
 2011-08-18 20:51:04 +00:00
Bill Wendling
dec05a3784 Use this fantzy ArrayRef thing to pass in the list of predecessors. 
llvm-svn: 137978
 2011-08-18 20:39:32 +00:00
Akira Hatanaka
1876aadea7 Make IsShiftedMask a static function rather than defining it in an 
anonymous namespace.

llvm-svn: 137975
 2011-08-18 20:07:42 +00:00
Nick Lewycky
0b43a027b3 The edge from DISubprogram to DICompileUnit has been removed in recent versions 
of debug info.

llvm-svn: 137972
 2011-08-18 19:07:42 +00:00
Jim Grosbach
d14d4c0aa8 Thumb assembly parsing and encoding for CMP. 
llvm-svn: 137963
 2011-08-18 18:08:29 +00:00
Bill Wendling
3fbc8471bb Use static instead of anonymous namespace. 
llvm-svn: 137959
 2011-08-18 17:57:57 +00:00
Jim Grosbach
088d205084 Thumb instructions CBZ and CBNZ are Thumb2, not THumb1. 
llvm-svn: 137956
 2011-08-18 17:51:36 +00:00
Chris Lattner
8213fad390 Rip out the old StructType APIs as warned about on llvmdev last week. 
llvm-svn: 137953
 2011-08-18 17:39:28 +00:00
Jim Grosbach
2f385f0f38 ARM Thumb blx instruction fixup has same data range as bl. 
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.

llvm-svn: 137947
 2011-08-18 16:57:50 +00:00