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Commit Graph

217562 Commits

Author SHA1 Message Date
LLVM GN Syncbot
5b75cf9bf8 [gn build] Port 560170fa2de5 2021-06-23 17:11:10 +00:00
Juneyoung Lee
65f02ea21f [ConstantFold] Allow propagation of poison for and/or i1
They were disallowed due to its bad interaction with select i1 -> and/or i1.
The transformation is now disabled by D101191, so let's revive this.
2021-06-24 02:03:09 +09:00
Nikita Popov
94c11807a4 [LAA] Make getPointersDiff() API compatible with opaque pointers
Make getPointersDiff() and sortPtrAccesses() compatible with opaque
pointers by explicitly passing in the element type instead of
determining it from the pointer element type.

The SLPVectorizer result is slightly non-optimal in that unnecessary
pointer bitcasts are added.

Differential Revision: https://reviews.llvm.org/D104784
2021-06-23 18:44:34 +02:00
Tomasz Miąsko
5a6e96d2d0 [Demangle][Rust] Hide implementation details NFC
Move content of the "public" header into the implementation file.

This also renames two enumerations that were previously used through
`rust_demangle::` scope, to avoid breaking a build bot with older
version of GCC that rejects uses of enumerator through `E::A` if there
is a variable with the same name as enumeration `E` in the scope.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D104362
2021-06-23 18:28:16 +02:00
Sanjay Patel
7941cb8b83 [ValueTracking] look through bitcast of vector in computeKnownBits
This borrows as much as possible from the SDAG version of the code
(originally added with D27129 and since updated with big endian support).

In IR, we can test more easily for correctness than we did in the
original patch. I'm using the simplest cases that I could find for
InstSimplify: we computeKnownBits on variable shift amounts to see if
they are zero or in range. So shuffle constant elements into a vector,
cast it, and shift it.

The motivating x86 example from https://llvm.org/PR50123 is also here.
We computeKnownBits in the caller code, but we only check if the shift
amount is in range. That could be enhanced to catch the 2nd x86 test -
if the shift amount is known too big, the result is 0.

Alive2 understands the datalayout and agrees that the tests here are
correct - example:
https://alive2.llvm.org/ce/z/KZJFMZ

Differential Revision: https://reviews.llvm.org/D104472
2021-06-23 11:46:46 -04:00
David Green
3588011fd8 [ARM] Limit v6m unrolling with multiple live outs
v6m cores only have a limited number of registers available. Unrolling
can mean we spend more on stack spills and reloads than we save from the
unrolling. This patch adds an extra heuristic to put a limit on the
unroll count for loops with multiple live out values, as measured from
the LCSSA phi nodes.

Differential Revision: https://reviews.llvm.org/D104659
2021-06-23 16:36:37 +01:00
Datta Nagraj
9ca79457ad [InstCombine] Eliminate casts to optimize ctlz operation
If a ctlz operation is performed on higher datatype and then
downcasted, then this can be optimized by doing a ctlz operation
on a lower datatype and adding the difference bitsize to the result
of ctlz to provide the same output:

https://alive2.llvm.org/ce/z/8uup9M

The original problem is shown in
https://llvm.org/PR50173

Differential Revision: https://reviews.llvm.org/D103788
2021-06-23 11:19:12 -04:00
Joel E. Denny
c4a535aaff [UpdateCCTestChecks][NFC] Permit other comments in common.py
Some parts of common.py already permit comment styles besides `;`.
Handle the remaining cases.  Specifically, a future patch will extend
update_cc_test_checks.py to call add_global_checks.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D104713
2021-06-23 11:12:42 -04:00
Craig Topper
3c67c98a41 [RISCV] Add explicit copy to V0 in the masked vmsge(u).vx intrinsic handling.
This is consistent with our other masked vector instructions.
Previously we found cases where not doing this broke fast reg
alloc.
2021-06-23 08:04:42 -07:00
Sanjay Patel
249986105f [InstCombine] convert FP min/max with negated op to fabs
This is part of improving floating-point patterns seen in:
https://llvm.org/PR39480

We don't require any FMF because the 2 potential corner cases
(-0.0 and NaN) are correctly handled without FMF:
1. -0.0 is treated as strictly less than +0.0 with
   maximum/minimum, so fabs/fneg work as expected.
2. +/- 0.0 with maxnum/minnum is indeterminate, so
   transforming to fabs/fneg is more defined.
3. The sign of a NaN may be altered by this transform,
   but that is allowed in the default FP environment.

If there are FMF, they are propagated from the min/max call to
one or both new operands which seems to agree with Alive2:
https://alive2.llvm.org/ce/z/bem_xC
2021-06-23 10:41:39 -04:00
Jinsong Ji
4cae41ddbe [DAGCombine] Check reassoc flags in aggressive fsub fusion
The is from discussion in https://reviews.llvm.org/D104247#inline-993387

The contract and reassoc flags shouldn't imply each other .

All the aggressive fsub fusion reassociate operations,
we should guard them with reassoc flag check.

Reviewed By: mcberg2017

Differential Revision: https://reviews.llvm.org/D104723
2021-06-23 13:59:40 +00:00
Roman Lebedev
d23e7cf5ba [NFC] Update arm_function_name.ll after 4de0c400317e5a92d57f2c76545061a9e7de22f8 2021-06-23 16:41:43 +03:00
Jay Foad
362fb7c790 [AMDGPU] Remove unused multiclass MUBUF_Real_gfx10_with_name 2021-06-23 14:37:28 +01:00
Roman Lebedev
3b18af59bd [NFC][ARM] Fix update_llc_test_checks for thumbv7-apple-darwin, autogenerate thumb2-ifcvt1.ll 2021-06-23 16:31:19 +03:00
Roman Lebedev
285eb4c722 [NFC][AArch64] Autogenerate a few more tests 2021-06-23 16:31:19 +03:00
Roman Lebedev
033b3a9ef6 [NFC][ARM] Fix update_llc_test_checks for aarch64-apple-ios/thumbv7s-apple-darwin, autogenerate a few tests 2021-06-23 16:31:19 +03:00
Roman Lebedev
4e033a7fbd [NFC][ARM] Fix update_llc_test_checks for thumbv7-apple-ios, autogenerate switch-minsize.ll 2021-06-23 16:31:19 +03:00
Roman Lebedev
06e1305748 [NFC][ARM] Fix update_llc_test_checks for armv7-apple-ios, autogenerate ifcvt5.ll/ifcvt6.ll 2021-06-23 16:31:19 +03:00
Nikita Popov
bc995d8257 [ARMParallelDSP] Remove unnecessary wrapper function (NFC)
AreSequentialAccesses() forwards directly to isConsecutiveAccess()
and has an unnecessary template parameter to boot.
2021-06-23 15:27:54 +02:00
Rosie Sumpter
cc55f4d4ca [AArch64] Add CodeGen tests for vector reduction intrinsics. NFC
Tests are added for vector reduce OR, AND and XOR.

Differential Revision: https://reviews.llvm.org/D104771
2021-06-23 13:46:16 +01:00
Roman Lebedev
a7fa6b8e79 [NFCI-ish][SimplifyCFGPass] Rework and generalize ret block tail-merging
This changes the approach taken to tail-merge the blocks
to always create a new block instead of trying to reuse some block,
and generalizes it to support dealing not with just the `ret` in the future.

This effectively lifts the CallBr restriction, although this isn't really intentional.
That is the only non-NFC change here, i'm not sure if it's reasonable/feasible to temporarily retain it.

Other restrictions of the transform remain.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D104598
2021-06-23 14:33:18 +03:00
Juneyoung Lee
bc3eadbb4a [InstSimplify] Add more poison folding optimizations
This adds more poison folding optimizations to InstSimplify.

Since all binary operators propagate poison, these are fine.

Also, the precondition of `select cond, undef, x` -> `x` is relaxed to allow the case when `x` is undef.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D104661
2021-06-23 20:25:24 +09:00
Joe Ellis
f07815e348 [Verifier] Fail on overrunning and invalid indices for {insert,extract} vector intrinsics
With regards to overrunning, the langref (llvm/docs/LangRef.rst)
specifies:

   (llvm.experimental.vector.insert)
   Elements ``idx`` through (``idx`` + num_elements(``subvec``) - 1)
   must be valid ``vec`` indices. If this condition cannot be determined
   statically but is false at runtime, then the result vector is
   undefined.

   (llvm.experimental.vector.extract)
   Elements ``idx`` through (``idx`` + num_elements(result_type) - 1)
   must be valid vector indices. If this condition cannot be determined
   statically but is false at runtime, then the result vector is
   undefined.

For the non-mixed cases (e.g. inserting/extracting a scalable into/from
another scalable, or inserting/extracting a fixed into/from another
fixed), it is possible to statically check whether or not the above
conditions are met. This was previously missing from the verifier, and
if the conditions were found to be false, the result of the
insertion/extraction would be replaced with an undef.

With regards to invalid indices, the langref (llvm/docs/LangRef.rst)
specifies:

    (llvm.experimental.vector.insert)
    ``idx`` represents the starting element number at which ``subvec``
    will be inserted. ``idx`` must be a constant multiple of
    ``subvec``'s known minimum vector length.

    (llvm.experimental.vector.extract)
    The ``idx`` specifies the starting element number within ``vec``
    from which a subvector is extracted. ``idx`` must be a constant
    multiple of the known-minimum vector length of the result type.

Similarly, these conditions were not previously enforced in the
verifier. In some circumstances, invalid indices were permitted
silently, and in other circumstances, an undef was spawned where a
verifier error would have been preferred.

This commit adds verifier checks to enforce the constraints above.

Differential Revision: https://reviews.llvm.org/D104468
2021-06-23 10:33:22 +00:00
Nikita Popov
3d23594a81 [TTI] Make assertion compatible with opaque pointers
Dropping the TODO here because it applies to all uses of this method.
2021-06-23 12:21:54 +02:00
Nikita Popov
5c5d90fb09 [LLParser] Remove special handling for call address space
Spin-off from D104740: I don't think this special handling is needed
anymore. Calls in textual IR are annotated with addrspace(N) (which
defaults to the program address space from data layout) and specifies
the expected pointer address space of the callee. There is no need
to special-case the program address space on top of that, as it
already is the default expected address space, and we shouldn't
allow use of the program address space if the call was explicitly
annotated with some other address space.

The IsCall parameter is retained because it will be used again soon.

Differential Revision: https://reviews.llvm.org/D104752
2021-06-23 12:07:44 +02:00
Jay Foad
4509098899 [AMDGPU] Stop using LegacyLegalizerInfo. NFCI.
Differential Revision: https://reviews.llvm.org/D103684
2021-06-23 10:50:32 +01:00
Jay Foad
7fc0f10d11 [IR] Simplify createReplacementInstr
NFCI, although the test change shows that ConstantExpr::getAsInstruction
is better than the old implementation of createReplacementInstr because
it propagates things like the sdiv "exact" flag.

Differential Revision: https://reviews.llvm.org/D104124
2021-06-23 10:47:43 +01:00
Florian Hahn
5b47031c00 [llvm] Update tests that got missed in adee485adf84ae8a. 2021-06-23 10:29:58 +01:00
Florian Hahn
9acf2cef1e [SCEV] Support signed predicates in applyLoopGuards.
This adds handling for signed predicates, similar to how unsigned
predicates are already handled.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D104732
2021-06-23 10:21:05 +01:00
Florian Hahn
71133f8ae4 [SCEV] Add tests with single-cond range check generated by InstComb. 2021-06-23 10:16:57 +01:00
Jay Foad
72abd6c7b3 [AMDGPU] Simplify collectReachableCallees. NFCI.
Don't use SCC iterators when we're only interested in reachability.
Use df_begin/df_end inline to find reachable nodes.

Differential Revision: https://reviews.llvm.org/D104704
2021-06-23 09:11:29 +01:00
Stanislav Mekhanoshin
5459f63eb4 [AMDGPU] Propagate LDS align into to instructions
Differential Revision: https://reviews.llvm.org/D104316
2021-06-23 00:57:16 -07:00
Fangrui Song
66df23eddc [llvm-objcopy][MachO] Fix namespace style issues 2021-06-23 00:31:52 -07:00
Martin Storsjö
1bc7c6b964 Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier"
This reverts commit ea011ec5ed53599305de62ca5fcfd31f4b3448c3.

This still causes some miscompiles, I'll follow up in the phabricator
review with a sample of that issue (which is part of the sample of
the previous issue).
2021-06-23 09:54:16 +03:00
Igor Kudrin
dc6a85256b [TableGen] Fix printing second PC-relative operand
If an instruction has several operands and a PC-relative one is not the
first of them, the generator may produce the code that does not pass the
'Address' parameter to the printout method. For example, for an Arm
instruction 'LE LR, $imm', it reuses the same code as for other
instructions where the second operand is not PC-relative:

void ARMInstPrinter::printInstruction(...) {
...
  case 11:
    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, ...
    printOperand(MI, 1, STI, O);
    O << ", ";
    printOperand(MI, 2, STI, O);
    break;
...

The patch fixes that by considering 'PCRel' when comparing
'AsmWriterOperand' values.

Differential Revision: https://reviews.llvm.org/D104698
2021-06-23 13:27:37 +07:00
Min-Yih Hsu
47606c47b1 [M68k] Fix incorrect #include-ed file in M68kSubtarget
In https://reviews.llvm.org/rG2193347e72fa , a cpp file is accidentally
included instead of its header file counterpart. This patch fixes this
error.
2021-06-22 23:02:21 -07:00
Jim Lin
a9ee1397f3 [M68k] Add testcases for shift and rotate instructions
Add codegen testcases for lsl, lsr, asr, rol and ror instructions.

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D104685
2021-06-23 13:26:58 +08:00
Jim Lin
155f1c4b36 [M68k] Refactor codegen patterns for logic operations and add tests for it
Refactor pat for and, or and xor operation and add missing tests for it

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D104626
2021-06-23 13:25:24 +08:00
Max Kazantsev
1073014a44 [LoopDeletion] Exploit undef Phi inputs when symbolically executing 1st iteration
Follow-up on Roman's idea expressed in D103959.
- If a Phi has undefined inputs from live blocks:
   - and no other inputs, assume it is undef itself;
   - and exactly one non-undef input, we can assume that all undefs are equal to this input.

Differential Revision: https://reviews.llvm.org/D104618
Reviewed By: lebedev.ri, nikic
2021-06-23 11:53:48 +07:00
Max Kazantsev
c87b0786bc [Test] Clear out br i1 undef from tests to avoid UB
We don't want to test possible unexpected impact of such
branches. Replacing them with regular conditions. Idea by
Nikita Popov.
2021-06-23 11:33:57 +07:00
Max Kazantsev
567fc5f75a [LSR] Filter out zero factors. PR50765
Zero factor leads to division by zero and failure of corresponding
assert as shown in PR50765. We should filter out such factors.

Differential Revision: https://reviews.llvm.org/D104702
Reviewed By: huihuiz, reames
2021-06-23 10:43:06 +07:00
Nico Weber
d6577233fa [gn build] don't build ubsan_minimal on mac
It doesn't build there, see http://45.33.8.238/macm1/12180/step_4.txt
2021-06-22 22:21:20 -04:00
River Riddle
deae9b5f50 [mlir] Add a ThreadPool to MLIRContext and refactor MLIR threading usage
This revision refactors the usage of multithreaded utilities in MLIR to use a common
thread pool within the MLIR context, in addition to a new utility that makes writing
multi-threaded code in MLIR less error prone. Using a unified thread pool brings about
several advantages:

* Better thread usage and more control
We currently use the static llvm threading utilities, which do not allow multiple
levels of asynchronous scheduling (even if there are open threads). This is due to
how the current TaskGroup structure works, which only allows one truly multithreaded
instance at a time. By having our own ThreadPool we gain more control and flexibility
over our job/thread scheduling, and in a followup can enable threading more parts of
the compiler.

* The static nature of TaskGroup causes issues in certain configurations
Due to the static nature of TaskGroup, there have been quite a few problems related to
destruction that have caused several downstream projects to disable threading. See
D104207 for discussion on some related fallout. By having a ThreadPool scoped to
the context, we don't have to worry about destruction and can ensure that any
additional MLIR thread usage ends when the context is destroyed.

Differential Revision: https://reviews.llvm.org/D104516
2021-06-23 01:29:24 +00:00
Jon Roelofs
f2b70884ff [Remarks] Make memsize remarks report as an analysis, not a missed opportunity.
Differential revision: https://reviews.llvm.org/D104078
2021-06-22 18:22:47 -07:00
Liqiang Tao
ad4dd08538 [llvm][Inliner] Make PriorityInlineOrder lazily updated
This patch makes PriorityInlineOrder lazily updated.
The PriorityInlineOrder would lazily update the desirability of a call site if it's decreasing.

Reviewed By: kazu

Differential Revision: https://reviews.llvm.org/D104654
2021-06-23 08:59:53 +08:00
Peter Collingbourne
48ca0247f9 gn build: Only build the TSan runtime on 64-bit platforms.
TSan only supports 64-bit platforms.

Differential Revision: https://reviews.llvm.org/D104755
2021-06-22 17:51:00 -07:00
Peter Collingbourne
5b5b35d51b gn build: Add support for building ubsan_minimal.
Differential Revision: https://reviews.llvm.org/D104754
2021-06-22 17:51:00 -07:00
Hongtao Yu
c6ff0d26c8 [CSSPGO][llvm-profgen] Handle return to external transition.
In a callback case, a return from internal code, say A, to external runtime can happen. The external runtime can then call back to another internal routine, say B. Making an artificial branch that looks like a return from A to B can confuse the unwinder to treat the instruction before B as the call instruction.

Reviewed By: wenlei, wmi

Differential Revision: https://reviews.llvm.org/D104546
2021-06-22 16:24:59 -07:00
Philip Reames
ae4432a64d precommit test for D104665 2021-06-22 15:52:00 -07:00
Joseph Huber
1aa9483992 [Attributor] Fix AAExecutionDomain returning true on invalid states
This patch fixes a problem with the AAExecutionDomain attributor not
checking if it is in a valid state. This can cause it to incorrectly
return that a block is executed in a single threaded context after the
attributor failed for any reason.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D103186
2021-06-22 18:12:43 -04:00