RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 22:42:46 +02:00
Code Issues Projects Releases Wiki Activity
66,317 Commits 4 Branches 5 Tags 704 MiB
7695213793
Commit Graph

42676 Commits

Author SHA1 Message Date
Michael J. Spencer
5518dda87e x86-Win32: Switch ftol2 calling convention from stdcall to C. 
llvm-svn: 117474
 2010-10-27 18:52:38 +00:00
Michael J. Spencer
bf82646290 COFF: Add IMAGE_SCN_MEM_READ to text sections. 
There are currently 100 references to COFF::IMAGE_SCN in 6 files
and 11 different functions. Section to attribute mapping really
needs to happen in one place to avoid problems like this.

llvm-svn: 117473
 2010-10-27 18:52:29 +00:00
Michael J. Spencer
fc69783598 Fix whitespace. 
llvm-svn: 117472
 2010-10-27 18:52:20 +00:00
Rafael Espindola
4db628cd34 Set default type and flags for .init and .fini. 
llvm-svn: 117471
 2010-10-27 18:45:20 +00:00
Rafael Espindola
ca302c994a Produce an error for an invalid use of .symver. 
llvm-svn: 117462
 2010-10-27 17:56:18 +00:00
Jim Grosbach
5d4415c6b0 The new LDR* instruction patterns should handle the necessary encoding of 
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461
 2010-10-27 17:52:51 +00:00
Owen Anderson
c8757eb137 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson
e64b7187a9 Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Jim Grosbach
09eab01a37 The immediate operands of an LDRi12 instruction doesn't need the addrmode2 
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

llvm-svn: 117454
 2010-10-27 16:50:31 +00:00
Jim Grosbach
ddd67f8e88 Formatting. 
llvm-svn: 117453
 2010-10-27 16:30:18 +00:00
Rafael Espindola
58a0ea80a4 Symbols defined as the difference of other two end up in the ABS section. 
llvm-svn: 117451
 2010-10-27 16:04:30 +00:00
Rafael Espindola
23d05a8675 Add support for the .symver directive. This is really ugly, but most of it is 
contained in the ELF object writer.

llvm-svn: 117448
 2010-10-27 15:18:17 +00:00
Rafael Espindola
f5b4013598 Move more logic to isInSymtab and simplify. 
llvm-svn: 117447
 2010-10-27 14:44:52 +00:00
Mikhail Glushenkov
df4eb2e516 80-col violation. 
llvm-svn: 117443
 2010-10-27 09:09:10 +00:00
Mikhail Glushenkov
5eeaebe9b8 Remove try/catch(...) from Win32/Signals.inc. 
catch(...) is used in Win32/Signals.inc for catching Win32 structured
exceptions, but according to [1], this is wrong.

We can't simply change try/catch to __try/__finally, since this syntax is not
supported by MinGW. We can use __try/__finally on MSVC and __try1/__except1
macros on MinGW [2], but I think that that solution obfuscates the code too
much.

The use of try/catch(...) in Signals.inc makes it impossible to link
MinGW-compiled libSystem with llvm-gcc compiled executables. I propose that we
just remove try/catch(...) from Signals.inc, since the meaning of the code won't
change.

[1] http://members.cox.net/doug_web/eh.htm
[2] http://article.gmane.org/gmane.comp.compilers.llvm.cvs/81315

llvm-svn: 117442
 2010-10-27 09:09:04 +00:00
Kevin Enderby
74a2614673 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Jim Grosbach
5ccda16fe2 LDRi12 machine instructions handle negative offset operands normally (simple 
integer values), not with the addrmode2 encoding.

llvm-svn: 117429
 2010-10-27 01:19:41 +00:00
Kevin Enderby
d5235bb45c Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Jakob Stoklund Olesen
66180b2c06 Handle critical loop predecessors by making both inside and outside registers 
live out.

This doesn't prevent us from inserting a loop preheader later on, if that is
better.

llvm-svn: 117424
 2010-10-27 00:39:07 +00:00
Jakob Stoklund Olesen
514eb703b8 Compute critical loop predecessors in the same way as critical loop exits. 
Critical edges going into a loop are not as bad as critical exits. We can handle
them by splitting the critical edge, or by having both inside and outside
registers live out of the predecessor.

llvm-svn: 117423
 2010-10-27 00:39:05 +00:00
Jakob Stoklund Olesen
4701c56446 Physical registers trivially have multiple connected components all the time. 
Only virtuals should be requires to be connected.

llvm-svn: 117422
 2010-10-27 00:39:01 +00:00
Jim Grosbach
6453c7cdf9 One more spot where the new arm mode LDR instruction representation 
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421
 2010-10-27 00:38:16 +00:00
Wesley Peck
854507453a Adding disassembler to the MicroBlaze backend. 
llvm-svn: 117420
 2010-10-27 00:23:01 +00:00
Jim Grosbach
4d4caf1384 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach
625e128d29 Since I parameterized this bit, I should probably actually use said parameter. 
llvm-svn: 117418
 2010-10-26 23:58:04 +00:00
Dale Johannesen
e7f07349e4 Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches 
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.

llvm-svn: 117413
 2010-10-26 23:11:10 +00:00
Andrew Trick
6363e80ded Remove the vector of live vregs. I thought we would need to track 
them, but hopefully we won't. And this is not the right data structure
to do it anyway.

llvm-svn: 117412
 2010-10-26 22:58:24 +00:00
Owen Anderson
1dc05f20e2 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Jakob Stoklund Olesen
bb4b26c42b After splitting, compute connected components of all new registers, not just for 
the remainder register.

Example:

bb0:
  x = 1
bb1:
  use(x)
  ...
  x = 2
  jump bb1

When x is isolated in bb1, the inner part breaks into two components, x1 and x2:

bb0:
  x0 = 1
bb1:
  x1 = x0
  use(x1)
  ...
  x2 = 2
  x0 = x2
  jump bb1

llvm-svn: 117408
 2010-10-26 22:36:09 +00:00
Jakob Stoklund Olesen
3bf3211458 Verify that live intervals are connected. If there are multiple connected 
components, each should get its own virtual register.

llvm-svn: 117407
 2010-10-26 22:36:07 +00:00
Jakob Stoklund Olesen
fa777d622d Call RenumberValues for all new registers created during splitting. This is 
necessary to get correct hasPHIKill flags.

llvm-svn: 117406
 2010-10-26 22:36:05 +00:00
Jakob Stoklund Olesen
0007e9a345 Preserve PHIDef bits in cloned values during splitting. 
llvm-svn: 117405
 2010-10-26 22:36:02 +00:00
Devang Patel
7796146304 Assign source ordering to nodes created for StoreInst. 
llvm-svn: 117404
 2010-10-26 22:14:52 +00:00
Owen Anderson
55c0bad37d Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00
Owen Anderson
570a4cdc45 Simplify classes for shift instructions, which are never commutable. 
llvm-svn: 117398
 2010-10-26 21:13:59 +00:00
Owen Anderson
0cecbd810e Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Jakob Stoklund Olesen
3a4c0c13eb Teach MachineBasicBlock::print() to annotate instructions and blocks with 
SlotIndexes when available.

llvm-svn: 117392
 2010-10-26 20:21:46 +00:00
Jakob Stoklund Olesen
195132633a Remmeber to print full live interval on verification error. 
llvm-svn: 117391
 2010-10-26 20:21:43 +00:00
Rafael Espindola
50d3c29c30 Add support for .ident. 
llvm-svn: 117389
 2010-10-26 19:35:47 +00:00
Jim Grosbach
04cd5e5841 Grammar. 
llvm-svn: 117388
 2010-10-26 19:34:41 +00:00
Jim Grosbach
db5b1d93c2 Nuke extraneous comment. It's applicable elsewhere, but not in this func. 
llvm-svn: 117387
 2010-10-26 19:22:23 +00:00
Andrew Trick
06fb7ed472 Jakob's review of the basic register allocator. 
llvm-svn: 117384
 2010-10-26 18:34:01 +00:00
Owen Anderson
d8e5d26a56 Add correct NEON encoding for vpadal. 
llvm-svn: 117380
 2010-10-26 18:18:03 +00:00
Rafael Espindola
adaf2ea5c6 handle X86::EH_RETURN64 and X86::EH_RETURN. 
llvm-svn: 117378
 2010-10-26 18:09:55 +00:00
Devang Patel
e544bb3842 s/beginScope/beginInstruction/g 
s/endScope/endInstruction/g

llvm-svn: 117376
 2010-10-26 17:49:02 +00:00
Owen Anderson
b7618a821f Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Jakob Stoklund Olesen
de018e2d8e Don't verify physical registers going into landing pads. 
Magic is happening that we don't understand.

llvm-svn: 117370
 2010-10-26 16:49:23 +00:00
Rafael Espindola
e38790534e Implement some relaxations for arithmetic instructions. The limitation 
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364
 2010-10-26 14:09:12 +00:00
Kalle Raiskila
64680cd5b8 Change v64 datalayout in SPU. 
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.

llvm-svn: 117360
 2010-10-26 10:45:47 +00:00
Evan Cheng
324e678bb7 Use instruction itinerary to determine what instructions are 'cheap'. 
llvm-svn: 117348
 2010-10-26 02:08:50 +00:00
Evan Cheng
59acb7e4cf NEON vmov's are in Neon domain. 
llvm-svn: 117347
 2010-10-26 02:03:05 +00:00
Nick Lewycky
f7dddd658f For statistics that are only used in functions declared in !NDEBUG, wrap the 
declarations in !NDEBUG to avoid -Wunused-variable warnings. Patch by
Matt Beaumont-Gay!

llvm-svn: 117345
 2010-10-26 00:51:57 +00:00
Jakob Stoklund Olesen
b0c10ed95a InlineSpiller can also update LiveStacks. 
llvm-svn: 117338
 2010-10-26 00:11:35 +00:00
Jakob Stoklund Olesen
3988c3fb55 Make the spiller responsible for updating the LiveStacks analysis. 
llvm-svn: 117337
 2010-10-26 00:11:33 +00:00
Bob Wilson
309484bb46 When the "true" and "false" blocks of a diamond if-conversion are the same, 
do not double-count the duplicate instructions by counting once from the
beginning and again from the end.  Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end.  Radar 8589805.

This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction.  That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.

llvm-svn: 117333
 2010-10-26 00:02:24 +00:00
Bob Wilson
685e143630 Change if-conversion to keep track of the extra cost due to microcoded 
instructions separately from the count of non-predicated instructions.  The
instruction count is used in places to determine how many instructions to
copy, predicate, etc. and things get confused if that count includes the
extra cost for microcoded ops.

llvm-svn: 117332
 2010-10-26 00:02:21 +00:00
Bob Wilson
abe62128b5 Tidy up redundant check. 
llvm-svn: 117331
 2010-10-26 00:02:19 +00:00
Evan Cheng
2439e51388 Neuter r117193 as it causes significant post-ra scheduler compile time regression. 
llvm-svn: 117329
 2010-10-25 23:56:21 +00:00
Rafael Espindola
5fecad6a27 Produce the headers directly in the Finish method. This allows us to use 
the existing streamer methods that are endian safe.

llvm-svn: 117323
 2010-10-25 22:26:55 +00:00
Dale Johannesen
2566d39d07 An stdcall function calling a non-stdcall function 
cannot use tailcall.  PR 8461.

llvm-svn: 117322
 2010-10-25 22:17:05 +00:00
Dan Gohman
ef977ab6b6 Support TBAA attachments on calls. This is somewhat experimental. 
llvm-svn: 117317
 2010-10-25 21:38:20 +00:00
Devang Patel
fa145a94d1 Simplify. 
Do not count use of sdisel for single call instruction.

llvm-svn: 117316
 2010-10-25 21:31:46 +00:00
Owen Anderson
e5e0dcd665 Add correct encodings for NEON vabal. 
llvm-svn: 117315
 2010-10-25 21:29:04 +00:00
Dan Gohman
20a3dd4ee1 Fix chaining in TBAA's pointsToConstantMemory. 
llvm-svn: 117314
 2010-10-25 21:24:55 +00:00
Devang Patel
3779ad5d59 Add counters to count basic blocks and machine basic blocks with out of order line number info. 
Add counters to count how many basic blocks are entirely selected by fastisel.

llvm-svn: 117310
 2010-10-25 20:55:43 +00:00
Owen Anderson
3eff0b86a5 Add correct NEON encodings for vaba. 
llvm-svn: 117309
 2010-10-25 20:52:57 +00:00
Devang Patel
24a6b791b6 Add simple counter to count no. of basic blocks without any line number information. At -O0, these basic block coule cause less than optimial debugging experience. 
llvm-svn: 117307
 2010-10-25 20:45:32 +00:00
Dan Gohman
cdc30324f1 Only read one bit for testing for a readonly type, leaving the other 
bits open for future uses.

llvm-svn: 117301
 2010-10-25 20:22:29 +00:00
Daniel Dunbar
5cbb066ea3 MC/AsmParser: Fix relative precedence of {+,-} and comparison ops. 
llvm-svn: 117299
 2010-10-25 20:18:56 +00:00
Daniel Dunbar
97fa30f53b MC/AsmLexer: Fix bug in source location for Slash token. 
llvm-svn: 117298
 2010-10-25 20:18:53 +00:00
Owen Anderson
61f5b3f2dc Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 
llvm-svn: 117294
 2010-10-25 20:17:22 +00:00
Owen Anderson
072692331e Provide correct NEON encodings for vbsl. 
llvm-svn: 117293
 2010-10-25 20:13:13 +00:00
Jim Grosbach
1a13b873e7 imm12 operands aren't Thumb2 only, so rename the printer helper function. 
llvm-svn: 117291
 2010-10-25 20:00:01 +00:00
Dan Gohman
3bce49a02a Add a comment. 
llvm-svn: 117288
 2010-10-25 19:47:25 +00:00
Owen Anderson
59e85cbd66 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Rafael Espindola
7f67e5ad77 Add a virtual destructor. 
llvm-svn: 117280
 2010-10-25 18:38:32 +00:00
Owen Anderson
2824342fac Provide correct NEON encodings for vand, veor, and vorr. 
llvm-svn: 117279
 2010-10-25 18:28:30 +00:00
Owen Anderson
ba261b092c Add NEON encoding tests for vcgt and vacgt. 
llvm-svn: 117276
 2010-10-25 18:03:59 +00:00
Rafael Espindola
5748458e7d Add support for emitting ARM file attributes. 
llvm-svn: 117275
 2010-10-25 17:50:35 +00:00
Owen Anderson
3a5f798790 Add tests for NEON encodings of vcge and vacge. 
llvm-svn: 117274
 2010-10-25 17:49:32 +00:00
Owen Anderson
757022131f Add a warning about our inability to test the encoding of vceq with immediate zero. 
llvm-svn: 117273
 2010-10-25 17:33:02 +00:00
Jakob Stoklund Olesen
7aeb8acd65 In which I learn how to forward declare template classes. 
llvm-svn: 117272
 2010-10-25 17:27:30 +00:00
Dan Gohman
9d63075905 Update comments; BasicAA is no longer necessarily the end of the chain. 
llvm-svn: 117268
 2010-10-25 16:29:52 +00:00
Dan Gohman
67e229bec7 Reintroduce these asserts, now that BasicAA is a normal AliasAnalysis pass. 
llvm-svn: 117266
 2010-10-25 16:28:57 +00:00
Dan Gohman
96e34e87ca Fix a case where instcombine was stripping metadata (and alignment) 
from stores when folding in bitcasts.

llvm-svn: 117265
 2010-10-25 16:16:27 +00:00
Charles Davis
42270b5d54 Add a new 'hotpatch' attribute. This attribute will insert a two-byte no-op 
instruction at the beginning of each function that has the attribute, allowing
the function to be easily hooked and/or patched.

llvm-svn: 117264
 2010-10-25 15:37:09 +00:00
Duncan Sands
8119017726 ATTRIBUTE_UNUSED has been renamed to LLVM_ATTRIBUTE_UNUSED. 
Rather than rename this instance, use the cast-to-void idiom
instead.  This will hopefully fix the windows buildbots.

llvm-svn: 117262
 2010-10-25 13:10:03 +00:00
Rafael Espindola
c6e7790c4b Add X86::reloc_global_offset_table and use it to have a single place where 
we check for _GLOBAL_OFFSET_TABLE_.

llvm-svn: 117241
 2010-10-24 17:35:42 +00:00
Duncan Sands
5b25503aab Fix PR8445: a block with no predecessors may be the entry block, in which case 
it isn't unreachable and should not be zapped.  The check for the entry block
was missing in one case: a block containing a unwind instruction.  While there,
do some small cleanups: "M" is not a great name for a Function* (it would be
more appropriate for a Module*), change it to "Fn"; use Fn in more places.

llvm-svn: 117224
 2010-10-24 12:23:30 +00:00
Benjamin Kramer
86b0370b66 SmallVectorize. 
llvm-svn: 117213
 2010-10-23 17:10:24 +00:00
Eric Christopher
0dab5810aa Move rejection of NEON parameters earlier in fast isel call processing, 
note that we can actually handle some f64 arguments.

llvm-svn: 117209
 2010-10-23 09:37:17 +00:00
Benjamin Kramer
ed68a7877c Make the disassembler tables const so they end up in read-only memory. 
llvm-svn: 117206
 2010-10-23 09:10:44 +00:00
Michael J. Spencer
87c8212d41 X86: Emit _fltused instead of __fltused on Windows x64. 
llvm-svn: 117205
 2010-10-23 09:06:59 +00:00
Chandler Carruth
7dd652736f Move the remaining attribute macros to systematic names based on the attribute 
name and prefixed with 'LLVM_'.

llvm-svn: 117203
 2010-10-23 08:40:19 +00:00
Chandler Carruth
ea67aaa252 Remove a define which is never referenced. 
llvm-svn: 117202
 2010-10-23 08:25:16 +00:00
Chandler Carruth
7799a873bb Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names 
until other LLVM projects using these are cleaned up.

llvm-svn: 117200
 2010-10-23 08:10:43 +00:00
Chandler Carruth
25324e76ae Fix a likely bug in an assertion by adding parentheses around '||'. This bug 
was found by a GCC warning. ;]

llvm-svn: 117199
 2010-10-23 07:46:14 +00:00
Evan Cheng
71b2f935db Enable ARM fastcc. 
llvm-svn: 117194
 2010-10-23 02:19:37 +00:00
Evan Cheng
030f55c496 Properly model the latency of register defs which are 1) function returns or 
2) live-outs.

Previously the post-RA schedulers completely ignore these dependencies since
returns, branches, etc. are all scheduling barriers. This patch model the
latencies between instructions being scheduled and the barriers. It also
handle calls by marking their register uses.

llvm-svn: 117193
 2010-10-23 02:10:46 +00:00
Evan Cheng
132906a2d3 Latency between CPSR def and branch is zero. 
llvm-svn: 117192
 2010-10-23 02:04:38 +00:00
Jakob Stoklund Olesen
964f6a6be6 Verify LiveIntervals against the CFG, ensuring that live-in values are live-out 
of all predecessors.

llvm-svn: 117191
 2010-10-23 00:49:09 +00:00
Jim Grosbach
6d65ad0408 Trailing whitespace. 
llvm-svn: 117188
 2010-10-22 23:48:29 +00:00
Andrew Trick
4043309a54 Nonvirtual dtor that was accessible enough to be bad. 
llvm-svn: 117180
 2010-10-22 23:33:19 +00:00
Gabor Greif
6e58dbc9e4 fix memory-layout assumption which only holds on little-endian systems 
llvm-svn: 117176
 2010-10-22 23:16:11 +00:00
Andrew Trick
7a1dadd47d This is a prototype of an experimental register allocation 
framework. It's purpose is not to improve register allocation per se,
but to make it easier to develop powerful live range splitting. I call
it the basic allocator because it is as simple as a global allocator
can be but provides the building blocks for sophisticated register
allocation with live range splitting. 

A minimal implementation is provided that trivially spills whenever it
runs out of registers. I'm checking in now to get high-level design
and style feedback. I've only done minimal testing. The next step is
implementing a "greedy" allocation algorithm that does some register
reassignment and makes better splitting decisions.

llvm-svn: 117174
 2010-10-22 23:09:15 +00:00
Jakob Stoklund Olesen
c78f761faf Add more verification of LiveIntervals. 
llvm-svn: 117170
 2010-10-22 22:48:58 +00:00
Jakob Stoklund Olesen
68258f467a Be more strict about detecting multi-use blocks for isolation. 
When a block has exactly two uses and the register is both live-in and live-out,
don't isolate the block. We would be inserting two copies, so we haven't really
made any progress.

If the live-in and live-out values separate into disconnected components after
splitting, we would be making progress. We can't detect that for now.

llvm-svn: 117169
 2010-10-22 22:48:56 +00:00
Jim Grosbach
bba77cca02 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Evan Cheng
2c2dcc69d8 Unbreak build. 
llvm-svn: 117155
 2010-10-22 21:49:09 +00:00
Bob Wilson
0290dbe7d4 Teach instcombine to set the alignment arguments for NEON load/store intrinsics. 
llvm-svn: 117154
 2010-10-22 21:41:48 +00:00
Evan Cheng
20b70697bb Transfer implicit ops when forming load multiple and return instructions. 
llvm-svn: 117151
 2010-10-22 21:29:58 +00:00
Jakob Stoklund Olesen
de1439ce2b Be more strict when detecting critical edges before loop splitting. 
An exit block with a critical edge must only have predecessors in the loop, or
just before the loop. This guarantees that the inserted copies in the loop
predecessors dominate the exit block.

llvm-svn: 117144
 2010-10-22 20:28:23 +00:00
Jakob Stoklund Olesen
967bcbf445 Add print methods 
llvm-svn: 117143
 2010-10-22 20:28:21 +00:00
Owen Anderson
424434414e Add correct NEON encodings for vqdmlal. 
llvm-svn: 117134
 2010-10-22 19:35:48 +00:00
Jim Grosbach
10195e9b73 Add the encoding information for the rest of the ARM mode multiply instructions. 
llvm-svn: 117133
 2010-10-22 19:15:30 +00:00
Owen Anderson
2bbdc62e17 Provide correct encodings for NEON vmlal. 
llvm-svn: 117131
 2010-10-22 19:05:25 +00:00
Evan Cheng
e5b7a3a09f Silence compiler warnings. 
llvm-svn: 117128
 2010-10-22 18:57:05 +00:00
Owen Anderson
ada2b33321 Provide correct NEON encodings for vmla. 
llvm-svn: 117126
 2010-10-22 18:54:37 +00:00
Jim Grosbach
ca2897a0ca More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Evan Cheng
efac5b5f8d Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now. 
llvm-svn: 117119
 2010-10-22 18:23:05 +00:00
Jim Grosbach
eabb7c5bd1 Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

llvm-svn: 117114
 2010-10-22 17:42:06 +00:00
Benjamin Kramer
9e988fe81e Make some symbols static, move classes into anonymous namespaces. 
llvm-svn: 117111
 2010-10-22 17:35:07 +00:00
Jim Grosbach
0ae6bf8095 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
Wesley Peck
488027efa3 Making the e_machine configurable by the target backend in ELFObjectWriter. 
llvm-svn: 117099
 2010-10-22 15:52:49 +00:00
Andrew Trick
b9e8700beb Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
 2010-10-22 03:58:29 +00:00
Eric Christopher
58a6e62c08 Add some basic ret instruction support to arm fast-isel. 
llvm-svn: 117085
 2010-10-22 01:28:00 +00:00
Sean Callanan
9a40554de4 Fixed handling of immediate operand sizes, which 
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084
 2010-10-22 01:24:11 +00:00
NAKAMURA Takumi
76a048b6e7 Win32/Signals.inc: DontRemoveFileOnSignal(): Please acquire the CriticalSection. 
It choked BugPoint on Mingw.

llvm-svn: 117083
 2010-10-22 01:23:50 +00:00
Jim Grosbach
d86073aa9a ARM binary encoding for some of the multiply instructions. 
llvm-svn: 117080
 2010-10-21 22:52:30 +00:00
Jim Grosbach
7c42142b71 ARM binary encodings for MVN variants. 
llvm-svn: 117076
 2010-10-21 22:19:32 +00:00
Jim Grosbach
e6d61a87e4 Trailing whitespace. 
llvm-svn: 117073
 2010-10-21 22:04:05 +00:00
Jim Grosbach
cb41e97b5c ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Dan Gohman
fe5489a0ac Add some more documentation. 
llvm-svn: 117070
 2010-10-21 21:55:35 +00:00
Eric Christopher
59683c9d71 These don't need to be virtual. 
llvm-svn: 117068
 2010-10-21 21:47:51 +00:00
Michael J. Spencer
a43c204ef7 Fix Warnings. 
llvm-svn: 117062
 2010-10-21 20:49:38 +00:00
Michael J. Spencer
08602f9803 X86: Base _fltused on the FunctionType of the called value instead of the potentially null "CalledFunction". Thanks Duncan! 
This is needed for indirect calls.

llvm-svn: 117061
 2010-10-21 20:49:23 +00:00
Owen Anderson
f84632744e Move the encoding logic for Q registers into getMachineOpValue(). 
llvm-svn: 117060
 2010-10-21 20:49:13 +00:00
Mikhail Glushenkov
55ada6816e Trailing whitespace. 
llvm-svn: 117058
 2010-10-21 20:40:39 +00:00
Owen Anderson
ba2ac80921 ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower 
half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.

llvm-svn: 117056
 2010-10-21 20:21:49 +00:00
Eric Christopher
7ded7e88c8 Handle storing args to the stack for calls. 
llvm-svn: 117055
 2010-10-21 20:09:54 +00:00
Wesley Peck
8a77999240 Adding initial AsmParser implementation for the MBlaze backend. It is 
mostly based on the ARM AsmParser at this time and is not particularly
functional.

Changed the MBlaze data layout from:
    "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
    "E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.

Cleaned up the MBlaze source code:
    1. The floating point register class has been removed. The
       MicroBlaze does not have floating point registers. Floating
       point values are simply stored in integer registers.
    2. Renaming the CPURegs register class to GPR to reflect the
       standard naming.
    3. Removing a lot of stale code from AsmPrinter after
       the conversion to InstPrinter.
    4. Simplified sign extended loads by marking them as
       expanded in ISelLowering.

llvm-svn: 117054
 2010-10-21 19:48:38 +00:00
Dan Gohman
6fb125afc8 Explain what "constant" means here. 
llvm-svn: 117053
 2010-10-21 19:45:09 +00:00
Eric Christopher
b15029ea7e More load/store refactoring, call reg+offset simplification from within 
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051
 2010-10-21 19:40:30 +00:00
Jim Grosbach
f35d3b2aa1 trailing whitespace 
llvm-svn: 117050
 2010-10-21 19:38:40 +00:00
Dan Gohman
8cb659e892 Update comments. 
llvm-svn: 117048
 2010-10-21 19:01:22 +00:00
Owen Anderson
51a6bc3b27 Add correct NEON encodings for vhadd and vrhadd. 
llvm-svn: 117047
 2010-10-21 18:55:04 +00:00
Jakob Stoklund Olesen
4794d28044 Don't include the destination interval in the union when computing 
Parent - union(Y, ...). Doh.

llvm-svn: 117042
 2010-10-21 18:47:08 +00:00