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19627 Commits

Author SHA1 Message Date
Dan Gohman
898ed35860 Change this overloaded use of Sched::Latency to be an overloaded 
use of Sched::ILP instead, as Sched::Latency is going away.

llvm-svn: 142813
 2011-10-24 17:55:11 +00:00
Dan Gohman
f742ffd7fa Remove the explicit request for "Latency" scheduling from MSP430, 
as the Latency scheduler is going away.

llvm-svn: 142811
 2011-10-24 17:53:16 +00:00
Jim Grosbach
eceea163ef Thumb2 LDM instructions can target PC. Make sure to encode it. 
PR11220

llvm-svn: 142801
 2011-10-24 17:16:24 +00:00
Craig Topper
3cb62dca0f Add X86 SARX, SHRX, and SHLX instructions. 
llvm-svn: 142779
 2011-10-23 22:18:24 +00:00
Craig Topper
0e63b4485c Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Craig Topper
7019cf1b80 Add X86 MULX instruction for disassembler. 
llvm-svn: 142738
 2011-10-23 00:33:32 +00:00
Craig Topper
c543ac0876 Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions. 
llvm-svn: 142737
 2011-10-22 23:13:53 +00:00
Benjamin Kramer
03065133c3 Move various generated tables into read-only memory, fixing up const correctness along the way. 
llvm-svn: 142726
 2011-10-22 16:50:00 +00:00
Nadav Rotem
7a79f94aad Fix pr11193. 
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.

llvm-svn: 142724
 2011-10-22 12:39:25 +00:00
Bill Wendling
66327a8d0e The different flavors of ARM have different valid subsets of registers. Check 
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2

llvm-svn: 142706
 2011-10-22 00:29:28 +00:00
Jim Grosbach
d964cf8939 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Owen Anderson
ccc76e17cc Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. 
llvm-svn: 142669
 2011-10-21 18:43:28 +00:00
Jim Grosbach
9b539fab9d Nuke an #if0 that got accidentally left in. 
llvm-svn: 142658
 2011-10-21 16:59:08 +00:00
Jim Grosbach
a1d54f2c7a whitespace. 
llvm-svn: 142657
 2011-10-21 16:56:40 +00:00
Jim Grosbach
501c72cdc5 Remove some outdated comments. 
llvm-svn: 142653
 2011-10-21 16:14:12 +00:00
Craig Topper
fd96157f13 Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. 
llvm-svn: 142642
 2011-10-21 06:55:01 +00:00
Richard Smith
80f49e9eaa Fix unused variable warning. 
llvm-svn: 142630
 2011-10-21 01:22:04 +00:00
Owen Anderson
2021ad2133 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
llvm-svn: 142626
 2011-10-20 22:23:58 +00:00
Dan Gohman
5b37d690b5 Disable the PPC hazard recognizer. It currently only supports 
top-down scheduling and top-down scheduling is going away.

llvm-svn: 142621
 2011-10-20 21:45:36 +00:00
Owen Anderson
24f04143bc Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures. 
llvm-svn: 142618
 2011-10-20 21:24:38 +00:00
Bill Wendling
3e34fd8604 Add missing operand. <rdar://problem/10313323> 
llvm-svn: 142615
 2011-10-20 20:37:11 +00:00
Lang Hames
747fa3d477 Haven't yet found a nice way to handle TargetData verification in the 
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.

llvm-svn: 142605
 2011-10-20 19:24:44 +00:00
Jim Grosbach
547dde4517 Tidy up. Trailing whitespace. 
llvm-svn: 142591
 2011-10-20 17:28:20 +00:00
Jim Grosbach
e9d1df8266 ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach
972f26d936 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Chad Rosier
38661ab3ce Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( 
llvm-svn: 142557
 2011-10-20 00:07:12 +00:00
Evan Cheng
057c12c2a0 Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355 
llvm-svn: 142550
 2011-10-19 22:22:54 +00:00
James Molloy
73a2a8a45e Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size. 
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530
 2011-10-19 14:11:07 +00:00
Bill Wendling
aebac9fc6c Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool. 
llvm-svn: 142485
 2011-10-19 09:24:02 +00:00
Bill Wendling
0da8817ea2 Remove some dead code. 
llvm-svn: 142484
 2011-10-19 09:04:11 +00:00
Craig Topper
b1fa647871 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
llvm-svn: 142480
 2011-10-19 07:48:35 +00:00
Bill Wendling
bc96b4c75a Emit the MOVT instruction only if the # LPads is > 64K. 
llvm-svn: 142460
 2011-10-18 23:19:55 +00:00
Bill Wendling
72d4e0a695 For Thumb mode, we need to use a constant pool if the value is too large to be 
used with the CMP instruction.

llvm-svn: 142458
 2011-10-18 23:11:05 +00:00
Eric Christopher
d9e0c89f55 Revert "Turn on the vzeroupper pass by default." 
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.

llvm-svn: 142455
 2011-10-18 23:10:11 +00:00
Jim Grosbach
6a932d6ad1 ARM VTBL (one register) assembly parsing and encoding. 
llvm-svn: 142441
 2011-10-18 23:02:30 +00:00
Bill Wendling
da2d6a83c8 Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142440
 2011-10-18 22:52:20 +00:00
Eric Christopher
4046de9d18 Turn on the vzeroupper pass by default. 
I'll remove/rename the option in a few days.

llvm-svn: 142439
 2011-10-18 22:50:17 +00:00
Bill Wendling
f200722cbc Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142437
 2011-10-18 22:49:07 +00:00
Lang Hames
ccf186dd30 Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>. 
llvm-svn: 142432
 2011-10-18 22:11:33 +00:00
Bill Wendling
6900914506 The value we're comparing against may be too large for the ARM CMP 
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>

llvm-svn: 142431
 2011-10-18 22:11:18 +00:00
Bill Wendling
198609713e The immediate may be too large for the CMP instruction. Move it into a register 
and use that in the CMP.
<rdar://problem/10305266>

llvm-svn: 142429
 2011-10-18 21:55:58 +00:00
Jim Grosbach
d748cf251f Yet more ARM NEON assembly parsing for the lane index operand. 
llvm-svn: 142416
 2011-10-18 20:21:17 +00:00
Jim Grosbach
ff8c26a53f ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2 ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Andrew Trick
1b84db85e7 Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. 
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.

llvm-svn: 142397
 2011-10-18 19:18:52 +00:00
Bob Wilson
bb191a9fef Use isIntN and isUIntN to check for valid signed/unsigned numbers. 
llvm-svn: 142395
 2011-10-18 18:46:49 +00:00
Andrew Trick
5e61a8e533 whitespace 
llvm-svn: 142394
 2011-10-18 18:40:53 +00:00
Bill Wendling
92050387bb A landing pad could have more than one predecessor. In that case, we want that 
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>

llvm-svn: 142390
 2011-10-18 18:30:49 +00:00
Jim Grosbach
988b8dd4ce ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Jim Grosbach
2752e0b869 ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach
b56577b650 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Bruno Cardoso Lopes
edc2e30d42 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Bob Wilson
f78f688c02 Fix incorrect check for sign-extended constant BUILD_VECTOR. 
<rdar://problem/10298332>

llvm-svn: 142371
 2011-10-18 17:34:51 +00:00
Jim Grosbach
4a138cb8d9 ARM vqdmlal assembly parsing for the lane index operand. 
llvm-svn: 142365
 2011-10-18 17:16:30 +00:00
Jim Grosbach
5cc37c406d Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it. 
llvm-svn: 142363
 2011-10-18 17:09:35 +00:00
Jim Grosbach
031bb99231 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Justin Holewinski
361b3c9ff2 PTX: Fix disabling of MAD instruction selection 
llvm-svn: 142352
 2011-10-18 13:39:20 +00:00
Duncan Sands
2faab7dd2a Fix a bunch of unused variable warnings when doing a release 
build with gcc-4.6.

llvm-svn: 142350
 2011-10-18 12:44:00 +00:00
Bill Wendling
aea682a6fe Coding style cleanups. No functionality change. 
llvm-svn: 142341
 2011-10-18 07:40:22 +00:00
David Meyer
c50cb2f15a Remove NaClMode 
llvm-svn: 142338
 2011-10-18 05:29:23 +00:00
Chad Rosier
eb469f466b Add support for dynamic stack realignment when in thumb1 mode. 
rdar://10288916

llvm-svn: 142337
 2011-10-18 05:28:00 +00:00
Joe Abbey
cebf5dc822 Commit test, capitalizing store... keep it simple. 
llvm-svn: 142336
 2011-10-18 04:44:36 +00:00
Eli Friedman
f43710f4a8 Fix misc warnings. Patch by Joe Abbey. 
llvm-svn: 142332
 2011-10-18 03:17:34 +00:00
Lang Hames
dfb145da26 Backing out patch. Will refactor to remove the AsmParser dependency on Target. 
llvm-svn: 142323
 2011-10-18 00:23:49 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Lang Hames
4370882b22 Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies. 
Thanks to Raphael Espindola for tracking down the CMake issues.

llvm-svn: 142306
 2011-10-17 23:24:48 +00:00
Jim Grosbach
1e994e76a7 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
llvm-svn: 142303
 2011-10-17 23:09:09 +00:00
Nick Lewycky
c551c1c5f9 Add support for a new extension to the .file directive: 
.file filenumber "directory" "filename"

This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.

llvm-svn: 142300
 2011-10-17 23:05:28 +00:00
Chad Rosier
ef5ee1892c Add a few FIXME comments. 
llvm-svn: 142299
 2011-10-17 22:54:23 +00:00
Jim Grosbach
8e9ca16af6 Tidy up. 
llvm-svn: 142297
 2011-10-17 22:41:42 +00:00
Rafael Espindola
a40b412c70 142288 broke the build: 
Linking CXX executable ../../bin/llvm-as
../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)'
clang-3: error: linker command failed with exit code 1 (use -v to see invocation)

Revert "Validate target data layout strings."

This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e.

llvm-svn: 142296
 2011-10-17 22:37:51 +00:00
Bill Wendling
8390d96c1a Now Igor, throw the switch...give my creation life! 
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.

It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.

Neat, huh?
<rdar://problem/10116753>

llvm-svn: 142294
 2011-10-17 22:26:23 +00:00
Jim Grosbach
f3d495fbbd ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Lang Hames
416d4f3f36 Validate target data layout strings. 
Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion.

llvm-svn: 142288
 2011-10-17 22:05:34 +00:00
Benjamin Kramer
bc2d3cbf7e Use a SmallVector for intrinsic argument types. 
llvm-svn: 142259
 2011-10-17 21:33:26 +00:00
Bill Wendling
8f01b6c71d Don't renumber the blocks here. This could cause problems later on if another 
pass renumbers the blocks again.

llvm-svn: 142258
 2011-10-17 21:32:56 +00:00
Cameron Zwarich
4f62e0c1e3 Pseudoinstructions should not be less constrained than the instruction they are 
lowered to. This fixes a lot of verifier failures on the test suite.

llvm-svn: 142254
 2011-10-17 21:20:13 +00:00
Jim Grosbach
eeb05f7532 Tidy up organization. 
llvm-svn: 142248
 2011-10-17 21:00:11 +00:00
Bill Wendling
5d4f239d0a Add a call to EmitSjLjDispatchBlock. 
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.

llvm-svn: 142245
 2011-10-17 20:37:20 +00:00
Jim Grosbach
22167dc73c Fix improperly formed assert() call. 
llvm-svn: 142239
 2011-10-17 20:22:59 +00:00
Akira Hatanaka
4939842b5a Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
 2011-10-17 18:53:29 +00:00
Hal Finkel
f61af0e4b0 Revert change to function alignment b/c existing logic was fine 
llvm-svn: 142224
 2011-10-17 18:53:03 +00:00
Chad Rosier
8247682aba Removed set, but unused variables. 
Patch by Joe Abbey <jabbey@arxan.com>.

llvm-svn: 142223
 2011-10-17 18:48:30 +00:00
Akira Hatanaka
e8cb50da87 Move class and instruction definitions for conditional moves to a seperate file. 
llvm-svn: 142220
 2011-10-17 18:43:19 +00:00
Akira Hatanaka
9045499a59 Revert change made in r142205. 
llvm-svn: 142217
 2011-10-17 18:33:24 +00:00
Akira Hatanaka
0ab0d4d1f4 Redefine count-leading 0s and 1s instructions. 
llvm-svn: 142216
 2011-10-17 18:26:37 +00:00
Akira Hatanaka
f81b089ac3 Redefine mfhi/lo and mthi/lo instructions. 
llvm-svn: 142214
 2011-10-17 18:24:15 +00:00
Akira Hatanaka
4243d8876b Redefine multiply and divide instructions. 
llvm-svn: 142211
 2011-10-17 18:21:24 +00:00
Akira Hatanaka
6b17ee5b50 Add definition of a base class for logical shift/rotate instructions with two 
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
 2011-10-17 18:17:58 +00:00
Hal Finkel
df4af2dd0b Remove >80-col line and unicode 
llvm-svn: 142209
 2011-10-17 18:10:08 +00:00
Akira Hatanaka
3b8c93eda7 Add definition of a base class for logical shift/rotate immediate instructions 
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
 2011-10-17 18:06:56 +00:00
Akira Hatanaka
82a1bab4ab Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. 
llvm-svn: 142205
 2011-10-17 18:01:00 +00:00
Michael J. Spencer
7ce30d63fd Fix CMake build. 
llvm-svn: 142204
 2011-10-17 17:50:39 +00:00
Devang Patel
8f9c569a13 svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp 
There is no reason to have simple IR level pass in lib/Target.

llvm-svn: 142200
 2011-10-17 17:17:43 +00:00
Hal Finkel
f5b7d5ea68 Instructions for Book E PPC should be word aligned, set function alignment to reflect this 
llvm-svn: 142194
 2011-10-17 17:01:41 +00:00
Craig Topper
29c4a473d0 Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. 
llvm-svn: 142177
 2011-10-17 05:33:10 +00:00