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Author SHA1 Message Date
Evan Cheng
a647318eb3 Re-apply 91623 now that I actually know what I was trying to do. 
llvm-svn: 91655
 2009-12-18 01:59:21 +00:00
Bob Wilson
a9f20f9f6e Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.

llvm-svn: 91649
 2009-12-18 01:03:29 +00:00
John McCall
923cb2d8d7 Pass the error string directly to llvm_unreachable instead of the residual 
(0 && "error").  Rough consensus seems to be that g++ *should* be diagnosing
this because the pointer makes it not an ICE in c++03.  Everyone agrees that
the current standard is silly and null-pointer-ness should not be based on
ICE-ness.  Excellent fight scene in Act II, denouement weak, two stars.

llvm-svn: 91644
 2009-12-18 00:27:18 +00:00
Sean Callanan
06b6feb2e1 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Jeffrey Yasskin
f39a138a7c Revert r91623 to unbreak the buildbots. 
llvm-svn: 91632
 2009-12-17 22:44:34 +00:00
Evan Cheng
d765952b17 Remove an unused option. 
llvm-svn: 91623
 2009-12-17 21:23:58 +00:00
Chris Lattner
b944c6eca5 finish cleaning up StructLayoutMap. 
llvm-svn: 91612
 2009-12-17 20:00:21 +00:00
Ken Dyck
319b2ed194 In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of 
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.

llvm-svn: 91602
 2009-12-17 15:31:52 +00:00
Johnny Chen
04b3259f9d Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings. 
llvm-svn: 91571
 2009-12-16 23:36:52 +00:00
John McCall
8ee507f0f5 Silence a clang warning about the deprecated (but perfectly reasonable in 
context) increment-of-bool idiom.

llvm-svn: 91564
 2009-12-16 20:31:50 +00:00
Jim Grosbach
666c19db99 Mark STREX* as earlyclobber for the success result register. 
llvm-svn: 91555
 2009-12-16 19:44:06 +00:00
Johnny Chen
7339b74117 Add encoding bits for some Thumb instructions. Plus explicitly set the top two 
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496
 2009-12-16 02:32:54 +00:00
Evan Cheng
aaf2f58a04 Re-enable 91381 with fixes. 
llvm-svn: 91489
 2009-12-16 00:53:11 +00:00
John McCall
e3df19422d Every anonymous namespace is different. Caught by clang++. 
llvm-svn: 91481
 2009-12-16 00:15:28 +00:00
Jeffrey Yasskin
d50951dc1e Change indirect-globals to use a dedicated allocIndirectGV. This lets us 
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.

llvm-svn: 91464
 2009-12-15 22:42:46 +00:00
Johnny Chen
8ef481b5d7 Added encoding bits for the Thumb ISA. Initial checkin. 
llvm-svn: 91434
 2009-12-15 17:24:14 +00:00
Evan Cheng
32946d6aae Fix an encoding bug. 
llvm-svn: 91417
 2009-12-15 06:49:02 +00:00
Kenneth Uildriks
c0ab5a6e88 For fastcc on x86, let ECX be used as a return register after EAX and EDX 
llvm-svn: 91410
 2009-12-15 03:27:52 +00:00
Evan Cheng
4adb4acc7b Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp. 
llvm-svn: 91405
 2009-12-15 03:07:11 +00:00
Evan Cheng
cd8f0de016 Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
llvm-svn: 91381
 2009-12-15 00:53:42 +00:00
Jim Grosbach
76d722dd6c nand atomic requires opposite operand ordering 
llvm-svn: 91371
 2009-12-15 00:12:35 +00:00
Dan Gohman
57dc006590 Fix integer cast code to handle vector types. 
llvm-svn: 91362
 2009-12-14 23:40:38 +00:00
Johnny Chen
61b6d221d2 Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate 
between BR_JTr and STREXD.

llvm-svn: 91339
 2009-12-14 21:51:34 +00:00
Jim Grosbach
dc0006c895 v6 sync insn copy/paste error 
llvm-svn: 91333
 2009-12-14 21:33:32 +00:00
Jim Grosbach
09167e5bbb Add ARMv6 memory and sync barrier instructions 
llvm-svn: 91329
 2009-12-14 21:24:16 +00:00
Johnny Chen
80b7b55eea Fixed encoding bits typo of ldrexd/strexd. 
llvm-svn: 91327
 2009-12-14 21:01:46 +00:00
Jim Grosbach
266c2d59e6 Thumb2 atomic operations 
llvm-svn: 91321
 2009-12-14 20:14:59 +00:00
Chris Lattner
81c6d73285 fix an obvious bug found by clang++ and collapse a redundant if. 
Here's the diagnostic from clang:

/Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context
        printConstant(gv);
                      ^
1 diagnostic generated.

llvm-svn: 91318
 2009-12-14 19:34:32 +00:00
Jim Grosbach
c7285dc721 correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics 
llvm-svn: 91313
 2009-12-14 19:24:11 +00:00
Jim Grosbach
723a7aa4e9 add Thumb2 atomic and memory barrier instruction definitions 
llvm-svn: 91310
 2009-12-14 18:56:47 +00:00
Jim Grosbach
99ace7c9ff whitespace 
llvm-svn: 91307
 2009-12-14 18:36:32 +00:00
Jim Grosbach
aaf39891f4 ARM memory barrier instructions are not predicable 
llvm-svn: 91305
 2009-12-14 18:31:20 +00:00
Jim Grosbach
5741d33c74 add ldrexd/strexd instructions 
llvm-svn: 91284
 2009-12-14 17:02:55 +00:00
Bill Wendling
e4328758f9 Whitespace changes, comment clarification. No functional changes. 
llvm-svn: 91274
 2009-12-14 06:51:19 +00:00
Jim Grosbach
87975f6229 atomic binary operations up to 32-bits wide. 
llvm-svn: 91260
 2009-12-14 04:22:04 +00:00
Anton Korobeynikov
fddfe4d096 Do not allow uninitialize access during debug printing 
llvm-svn: 91232
 2009-12-13 01:00:32 +00:00
Eli Friedman
392adbdd7d More info on this transformation. 
llvm-svn: 91230
 2009-12-12 23:23:43 +00:00
Eli Friedman
38a7d3b32e Remove some stuff that's already implemented. Also, remove the note about 
merging x >u 5 and x <s 20 because it's impossible to implement.

llvm-svn: 91228
 2009-12-12 21:41:48 +00:00
Evan Cheng
ee5b5917fd Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. 
llvm-svn: 91223
 2009-12-12 20:03:14 +00:00
Anton Korobeynikov
5cd169e17e Implement variable-width shifts. 
No testcase yet - it seems we're exposing generic codegen bugs.

llvm-svn: 91221
 2009-12-12 18:55:37 +00:00
Evan Cheng
5cd8cd2a5c Add comment about potential partial register stall. 
llvm-svn: 91220
 2009-12-12 18:55:26 +00:00
Evan Cheng
53e863f152 Fix an obvious bug. No test case since LEA16r is not being used. 
llvm-svn: 91219
 2009-12-12 18:51:56 +00:00
Jim Grosbach
187ad02a4f Framework for atomic binary operations. The emitter for the pseudo instructions 
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200
 2009-12-12 01:40:06 +00:00
Anton Korobeynikov
724c82337f Lower setcc branchless, if this is profitable. 
Based on the patch by Brian Lucas!

llvm-svn: 91175
 2009-12-11 23:01:29 +00:00
Dan Gohman
2e616e859b Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. 
llvm-svn: 91158
 2009-12-11 21:31:27 +00:00
Jim Grosbach
0cfc544e97 memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around. 
llvm-svn: 91150
 2009-12-11 20:29:53 +00:00
Anton Korobeynikov
f8b2e2868e Honour setHasCalls() set from isel. 
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

llvm-svn: 91144
 2009-12-11 19:39:55 +00:00
Johnny Chen
5d6f117ed5 Store Register Exclusive should leave the source register Inst{3-0} unspecified. 
llvm-svn: 91143
 2009-12-11 19:37:26 +00:00
Jim Grosbach
89e51fb5ff Update properties. 
llvm-svn: 91140
 2009-12-11 18:52:41 +00:00
Evan Cheng
01a56041a5 Add support to 3-addressify 16-bit instructions. 
llvm-svn: 91104
 2009-12-11 06:01:48 +00:00
Jim Grosbach
5a1c16e5bb Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. 
llvm-svn: 91090
 2009-12-11 01:42:04 +00:00
Jim Grosbach
608ef114aa Add instruction encoding for DMB/DSB 
llvm-svn: 91053
 2009-12-10 18:35:32 +00:00
Jim Grosbach
be89da9845 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. 
llvm-svn: 91003
 2009-12-10 00:11:09 +00:00
Evan Cheng
9e2442c0be Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. 
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).

llvm-svn: 90984
 2009-12-09 21:00:30 +00:00
Evan Cheng
41c13e41fe Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code. 
llvm-svn: 90925
 2009-12-09 01:53:58 +00:00
Evan Cheng
7941695285 Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes. 
llvm-svn: 90922
 2009-12-09 01:36:00 +00:00
Evan Cheng
edcc21919f - Support inline asm 'w' constraint for 128-bit vector types. 
- Also support the 'q' NEON registers asm code.

llvm-svn: 90894
 2009-12-08 23:06:22 +00:00
Anton Korobeynikov
0ace515a4c Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas! 
llvm-svn: 90819
 2009-12-08 01:03:04 +00:00
Dan Gohman
44e25ed254 Don't enable the post-RA scheduler on x86 except at -O3. In its 
current form, it is too expensive in compile time.

llvm-svn: 90781
 2009-12-07 19:04:31 +00:00
Anton Korobeynikov
615499bd84 Some pretty-printing 
llvm-svn: 90742
 2009-12-07 02:28:41 +00:00
Anton Korobeynikov
d01ed4146b Add lowering of returnaddr and frameaddr intrinsics. Shamelessly stolen from x86 :) 
llvm-svn: 90740
 2009-12-07 02:28:10 +00:00
Anton Korobeynikov
71b92ae4e0 Initial codegen support for MSP430 ISRs 
llvm-svn: 90739
 2009-12-07 02:27:53 +00:00
Anton Korobeynikov
02fa40119e Add ability to select hw multiplier mode and select appropriate libcalls. 
llvm-svn: 90737
 2009-12-07 02:27:08 +00:00
Anton Korobeynikov
eee906f4f0 Dynamic stack realignment use of sp register as source/dest register 
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

llvm-svn: 90724
 2009-12-06 22:39:50 +00:00
Bill Wendling
60e15336be Calling InvalidateEntry during the refinement was breaking the bootstrap. 
llvm-svn: 90656
 2009-12-05 07:59:04 +00:00
Bill Wendling
a24fa4e67b Final cleanups: 
- Privatize a typedef.
- Call the InvalidateEntry when refining a type.

llvm-svn: 90655
 2009-12-05 07:46:49 +00:00
Bill Wendling
fb8e8f8bd7 Inline methods which are called only once. 
llvm-svn: 90640
 2009-12-05 01:46:01 +00:00
Bill Wendling
7871b8a922 Refactor some code. No functionality change. 
llvm-svn: 90639
 2009-12-05 01:43:33 +00:00
Dan Gohman
f9654e9258 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of 
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634
 2009-12-05 00:44:40 +00:00
David Greene
755852d0c3 Remove an unneeded include. 
llvm-svn: 90625
 2009-12-04 23:55:07 +00:00
David Greene
cb0611ec3b Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand. 
llvm-svn: 90608
 2009-12-04 22:38:46 +00:00
Bill Wendling
168e8cb33b Some code cleanup. No functionality change. 
llvm-svn: 90588
 2009-12-04 21:03:02 +00:00
Jim Grosbach
891c545129 remove out of date FIXME. 
llvm-svn: 90490
 2009-12-03 21:55:01 +00:00
Chris Lattner
b46655e25c expand note. 
llvm-svn: 90429
 2009-12-03 07:43:46 +00:00
Chris Lattner
6b86618a2b add a note 
llvm-svn: 90428
 2009-12-03 07:41:54 +00:00
Chris Lattner
b3cc713378 fix a build problem with VC++, PR5664, patch by Alp Toker! 
llvm-svn: 90419
 2009-12-03 06:58:32 +00:00
Bob Wilson
b53c801366 Recognize canonical forms of vector shuffles where the same vector is used for 
both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417
 2009-12-03 06:40:55 +00:00
Bill Wendling
4dbdfa814e Revert r90371. It was causing build failures. 
llvm-svn: 90383
 2009-12-03 01:54:07 +00:00
Bill Wendling
b01be4b16d Further improvements: refactoring code that does the same thing into one 
function, converting "dyn_cast" to "cast", asserting the correct things, and
other general cleanups.

llvm-svn: 90371
 2009-12-03 01:15:46 +00:00
Chris Lattner
29e2e60be6 yay for case insensitive file systems (?) 
llvm-svn: 90370
 2009-12-03 01:10:05 +00:00
Chris Lattner
09df97d257 remove some dead std::ostream using code. 
llvm-svn: 90366
 2009-12-03 00:55:04 +00:00
Chris Lattner
9ce833945e improve portability to avoid conflicting with std::next in c++'0x. 
Patch by Howard Hinnant!

llvm-svn: 90365
 2009-12-03 00:50:42 +00:00
Bill Wendling
db54e8c67c This initial code is meant to convert TargetData to use an AbstractTypesUser so 
that it doesn't have dangling pointers when abstract types are resolved. This
modifies it somewhat to address comments: making the "StructLayoutMap" an
anonymous structure, calling "removeAbstractTypeUser" when appropriate, and
adding asserts where helpful.

llvm-svn: 90362
 2009-12-03 00:17:12 +00:00
Jim Grosbach
0e1230b23b Factor the stack alignment calculations out into a target independent pass. 
No functionality change.

llvm-svn: 90336
 2009-12-02 19:30:24 +00:00
Jim Grosbach
5541b5f793 Thumb1 exception handling setjmp 
llvm-svn: 90246
 2009-12-01 18:10:36 +00:00
Johnny Chen
e3171163da For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011. 
llvm-svn: 90243
 2009-12-01 17:37:06 +00:00
Johnny Chen
7f7f23087c For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified. 
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.

Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
 2009-12-01 00:02:02 +00:00
Dan Gohman
e573c59c90 Minor whitespace fixes. 
llvm-svn: 90166
 2009-11-30 23:33:53 +00:00
Dan Gohman
af05157fde Fix a minor inconsistency. 
llvm-svn: 90165
 2009-11-30 23:33:37 +00:00
Bob Wilson
b293fe32cb Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable 
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low.  The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.

llvm-svn: 90144
 2009-11-30 18:35:03 +00:00
Bob Wilson
f893a19df9 Fix some more ARM unified syntax warnings. 
llvm-svn: 90141
 2009-11-30 17:47:19 +00:00
Mon P Wang
27bce4e285 Added support to allow clients to custom widen. For X86, custom widen vectors for 
divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.

llvm-svn: 90108
 2009-11-30 02:42:02 +00:00
Chris Lattner
40d74cea6b update and consolidate the load pre notes. 
llvm-svn: 90050
 2009-11-29 02:19:52 +00:00
Chris Lattner
0df78ea645 add a deadargelim note. 
llvm-svn: 90009
 2009-11-27 17:12:30 +00:00
Chris Lattner
c0b92ff385 This testcase is actually only partially redundant, and requires 
the FIXME I added yesterday to be implemented.

llvm-svn: 90008
 2009-11-27 16:53:57 +00:00
Chris Lattner
225a88f4ab this (and probably several others) are now done. 
llvm-svn: 89982
 2009-11-27 00:35:04 +00:00
Chris Lattner
4824ebfded Teach memdep to phi translate bitcasts. This allows us to compile 
the example in GCC PR16799 to:

LBB1_2:                                                     ## %bb1
	movl	%eax, %eax
	subq	%rax, %rdi
	movq	%rdi, (%rcx)
	movl	(%rdi), %eax
	testl	%eax, %eax
	je	LBB1_2

instead of:

LBB1_2:                                                     ## %bb1
	movl	(%rdi), %ecx
	subq	%rcx, %rdi
	movq	%rdi, (%rax)
	cmpl	$0, (%rdi)
	je	LBB1_2

llvm-svn: 89978
 2009-11-26 23:41:07 +00:00
Chris Lattner
9c88c96b3f Teach basicaa that x|c == x+c when the c bits of x are clear. This 
allows us to compile the example in readme.txt into:

LBB1_1:                                                     ## %bb
	movl	4(%rdx,%rax), %ecx
	movl	%ecx, %esi
	imull	(%rdx,%rax), %esi
	imull	%esi, %ecx
	movl	%esi, 8(%rdx,%rax)
	imull	%ecx, %esi
	movl	%ecx, 12(%rdx,%rax)
	movl	%esi, 16(%rdx,%rax)
	imull	%ecx, %esi
	movl	%esi, 20(%rdx,%rax)
	addq	$16, %rax
	cmpq	$4000, %rax
	jne	LBB1_1

instead of:

LBB1_1: 
	movl	(%rdx,%rax), %ecx
	imull	4(%rdx,%rax), %ecx
	movl	%ecx, 8(%rdx,%rax)
	imull	4(%rdx,%rax), %ecx
	movl	%ecx, 12(%rdx,%rax)
	imull	8(%rdx,%rax), %ecx
	movl	%ecx, 16(%rdx,%rax)
	imull	12(%rdx,%rax), %ecx
	movl	%ecx, 20(%rdx,%rax)
	addq	$16, %rax
	cmpq	$4000, %rax
	jne	LBB1_1

GCC (4.2) doesn't seem to be able to eliminate the loads in this 
testcase either, it generates:

L2:
	movl	(%rdx), %eax
	imull	4(%rdx), %eax
	movl	%eax, 8(%rdx)
	imull	4(%rdx), %eax
	movl	%eax, 12(%rdx)
	imull	8(%rdx), %eax
	movl	%eax, 16(%rdx)
	imull	12(%rdx), %eax
	movl	%eax, 20(%rdx)
	addl	$4, %ecx
	addq	$16, %rdx
	cmpl	$1002, %ecx
	jne	L2

llvm-svn: 89952
 2009-11-26 16:26:43 +00:00
Chris Lattner
677b93d4c8 teach basicaa that A[i] != A[i+1]. 
llvm-svn: 89951
 2009-11-26 16:18:10 +00:00
Chris Lattner
0b862edca3 update some notes slightly 
llvm-svn: 89913
 2009-11-26 01:51:18 +00:00
Viktor Kutuzov
c0799914a1 Rollback changes r89516: Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods. 
llvm-svn: 89893
 2009-11-25 22:44:18 +00:00
Bob Wilson
b1cce5329e Tail duplicate indirect branches for PowerPC, too. 
With the testcase for pr3120, the "threaded interpreter" runtime decreases
from 1788 to 1413 with this change.

llvm-svn: 89877
 2009-11-25 19:57:14 +00:00
Benjamin Kramer
fbac37018a Avoid some possibly unsafe uses of StringRef::data(). 
llvm-svn: 89873
 2009-11-25 18:26:09 +00:00
Devang Patel
d50fc13c19 Use StringRef (again) in DebugInfo interface. 
llvm-svn: 89866
 2009-11-25 17:36:49 +00:00
Bob Wilson
aee7a9e676 Based on the testcase for pr3120, running on my MacPro with Xeon processors, 
it is definitely profitable to tail duplicate indirect branches for x86.
This is likely to be true to various degrees for all modern x86 processors.

llvm-svn: 89865
 2009-11-25 17:27:53 +00:00
Bruno Cardoso Lopes
038281c523 Support PIC loading of constant pool entries 
llvm-svn: 89863
 2009-11-25 12:17:58 +00:00
Daniel Dunbar
ffe6484b7c Sketch structure for X86 disassembler. 
llvm-svn: 89850
 2009-11-25 06:53:08 +00:00
Bruno Cardoso Lopes
974ab18d0e Use endianess dependent offsets for load/store of doubles when 
using two swc/lwc instead of sdc/ldc.

llvm-svn: 89826
 2009-11-25 01:05:25 +00:00
Dale Johannesen
916d90c926 Fix compiler warnings. 
llvm-svn: 89824
 2009-11-25 00:58:21 +00:00
Bruno Cardoso Lopes
6d23fc8097 Only include in the callee saved regs the sub registers to avoid 
unnecessary save/restore.

llvm-svn: 89823
 2009-11-25 00:47:43 +00:00
Bruno Cardoso Lopes
7316c984a5 Add proper emission of load/store double to stack slots for mips1 targets! 
llvm-svn: 89821
 2009-11-25 00:36:00 +00:00
Devang Patel
4c7b5eaf23 Revert r89803. 
llvm-svn: 89819
 2009-11-25 00:31:13 +00:00
Bob Wilson
c5fa56c805 Refactor target hook for tail duplication as requested by Chris. 
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation.  I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size.  ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.

llvm-svn: 89814
 2009-11-24 23:35:49 +00:00
Dale Johannesen
5809ff0e58 Do not store R31 into the caller's link area on PPC. 
This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into.  Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not.  7311323.

llvm-svn: 89811
 2009-11-24 22:59:02 +00:00
Devang Patel
c68c2293a7 Enable debug info for ppc-darwin. 
llvm-svn: 89803
 2009-11-24 21:38:54 +00:00
Evan Cheng
b81878ed80 Enable predication of NEON instructions in Thumb2 mode. 
llvm-svn: 89748
 2009-11-24 08:06:15 +00:00
Dale Johannesen
ee890316d5 Make capitalization of names starting "is" more consistent. 
No functional change.

llvm-svn: 89724
 2009-11-24 01:09:07 +00:00
Evan Cheng
179a11776c Data type suffix must come after predicate. 
llvm-svn: 89723
 2009-11-24 01:05:23 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
 2009-11-24 00:44:37 +00:00
Jim Grosbach
a142a709c8 80 column violations 
llvm-svn: 89718
 2009-11-24 00:20:27 +00:00
Jeffrey Yasskin
0a0b21f8c5 * Move stub allocation inside the JITEmitter, instead of exposing a 
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.

* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.

llvm-svn: 89715
 2009-11-23 23:35:19 +00:00
Dan Gohman
b5ec39e2dc Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. 
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711
 2009-11-23 23:20:51 +00:00
Jeffrey Yasskin
ed6d1ce9ae Allow more than one stub to be being generated at the same time. 
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.

llvm-svn: 89708
 2009-11-23 22:49:00 +00:00
Evan Cheng
8c9f6147cd Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations. 
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.

llvm-svn: 89706
 2009-11-23 21:57:23 +00:00
Jim Grosbach
76b545e988 move fconst[sd] to UAL. <rdar://7414913> 
llvm-svn: 89700
 2009-11-23 21:08:25 +00:00
Johnny Chen
e59a67f527 Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying 
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup.  VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.

llvm-svn: 89699
 2009-11-23 21:00:43 +00:00
Jim Grosbach
bbb786facf fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate. 
llvm-svn: 89694
 2009-11-23 20:35:53 +00:00
Johnny Chen
9999d2524e Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify 
{?,?,?,?} as op11_8 for VEXTd and VEXTq.

llvm-svn: 89693
 2009-11-23 20:09:13 +00:00
Johnny Chen
b49fe624e7 Partially revert r89377 by removing NLdStLN class definition from 
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.

llvm-svn: 89684
 2009-11-23 18:16:16 +00:00
Johnny Chen
1116f46301 Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane 
should be left unspecified now that Bob Wilson has fixed pr5470.

llvm-svn: 89676
 2009-11-23 17:48:17 +00:00
David Goodwin
07713477dc Minor itinerary fixes for FP instructions. 
llvm-svn: 89672
 2009-11-23 17:34:12 +00:00
Jim Grosbach
928cb87167 Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values. 
llvm-svn: 89618
 2009-11-22 20:05:32 +00:00
Jim Grosbach
33f06ed72e Generate more correct debug info for frame indices. 
llvm-svn: 89576
 2009-11-22 02:32:29 +00:00
Anton Korobeynikov
5511c0260f Minor optimization: when doing eq/ne comparions and RHS is a constant - swap operands, this will allow us to fold imm into comparison. 
llvm-svn: 89574
 2009-11-22 01:14:08 +00:00
Anton Korobeynikov
10669b8c42 Drop unsupported imm operands 
llvm-svn: 89573
 2009-11-22 01:13:54 +00:00
Anton Korobeynikov
44886c9a90 Use 2-byte alignment for functions. 4 bytes are clear overkill here. 
llvm-svn: 89572
 2009-11-22 01:13:39 +00:00
Anton Korobeynikov
9cea2b264c Use semicolon as assembler comment string 
llvm-svn: 89571
 2009-11-22 01:12:49 +00:00
Jim Grosbach
99c5b49c61 Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.

llvm-svn: 89568
 2009-11-21 23:34:09 +00:00
Jim Grosbach
d4603a5c4e Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.

llvm-svn: 89562
 2009-11-21 21:40:08 +00:00
Evan Cheng
a7496ef9a6 Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. 
llvm-svn: 89542
 2009-11-21 06:21:52 +00:00
Devang Patel
327919890c We are not using DBG_STOPPOINT anymore. 
llvm-svn: 89536
 2009-11-21 02:46:55 +00:00
Viktor Kutuzov
ac8f027245 Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods. 
llvm-svn: 89516
 2009-11-21 00:00:02 +00:00
Dan Gohman
e5eddcd606 Fix a thinko that caused spurious @GOTOFFs. 
llvm-svn: 89509
 2009-11-20 23:30:32 +00:00
Dan Gohman
ca4026afec Update for new getBlockAddress signature. 
llvm-svn: 89507
 2009-11-20 23:21:00 +00:00
Dan Gohman
3517f425b8 Target-independent support for TargetFlags on BlockAddress operands, 
and support for blockaddresses in x86-32 PIC mode.

llvm-svn: 89506
 2009-11-20 23:18:13 +00:00
Sean Callanan
78ee7f5d57 Recommitting PALIGNR shift width fixes. 
Thanks to Daniel Dunbar for fixing clang intrinsics:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=89499

llvm-svn: 89500
 2009-11-20 22:28:42 +00:00
Dale Johannesen
45f80d39f6 Remove an incorrect overaggressive optimization 
(PPC specific).

llvm-svn: 89496
 2009-11-20 22:16:40 +00:00
Sean Callanan
d92626fc0d Reverting PALIGNR fix until I figure out how this 
broke the Clang testsuite.

llvm-svn: 89495
 2009-11-20 22:09:28 +00:00
Sean Callanan
0da77167d3 Fixed PALIGNR to take 8-bit rotations in all cases. 
Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).

llvm-svn: 89491
 2009-11-20 21:40:28 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Jim Grosbach
8371342c89 The verify() call of CPEIsInRange() isn't right for the assertion check of 
constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.

llvm-svn: 89473
 2009-11-20 19:37:38 +00:00
Jim Grosbach
0057f45c31 Remove verifySizes() since it's not adding much value. 
llvm-svn: 89443
 2009-11-20 02:32:06 +00:00
Evan Cheng
5fe8b0b3c5 Also CSE non-pic load from constant pools. 
llvm-svn: 89440
 2009-11-20 02:10:27 +00:00
Evan Cheng
405012b096 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
llvm-svn: 89423
 2009-11-20 00:54:03 +00:00
Eric Christopher
fd3b2deb8f Update comment to reflect instruction. 
llvm-svn: 89414
 2009-11-20 00:21:55 +00:00
Jim Grosbach
9a19252df2 When placing constant islands and adjusting for alignment padding, inline 
assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.

llvm-svn: 89403
 2009-11-19 23:10:28 +00:00
Evan Cheng
af22254deb Refactor cmov selection code out to a separate function. No functionality change. 
llvm-svn: 89396
 2009-11-19 21:45:22 +00:00
Bill Wendling
fcbf6174ab Reverting the EH table patches. 
$ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89279 into '.':
U    lib/CodeGen/AsmPrinter/DwarfException.cpp
U    lib/Target/TargetLoweringObjectFile.cpp
$ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89270 into '.':
G    lib/CodeGen/AsmPrinter/DwarfException.cpp
G    lib/Target/TargetLoweringObjectFile.cpp

llvm-svn: 89379
 2009-11-19 19:21:09 +00:00
Johnny Chen
346e6b6cac Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not 
fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.

llvm-svn: 89377
 2009-11-19 19:20:17 +00:00
Jim Grosbach
75111632ca fix typo 
llvm-svn: 89369
 2009-11-19 18:23:19 +00:00
Dan Gohman
133120de6d Fix a typo in a comment. 
llvm-svn: 89360
 2009-11-19 16:35:11 +00:00
Evan Cheng
9730c9113e 80 col violation. 
llvm-svn: 89337
 2009-11-19 08:16:50 +00:00
Evan Cheng
987b8c3d9a More consistent thumb1 asm printing. 
llvm-svn: 89328
 2009-11-19 06:57:41 +00:00
Evan Cheng
c2e359a418 Shrink ldr / str [sp, imm0-1024] to 16-bit instructions. 
llvm-svn: 89326
 2009-11-19 06:32:27 +00:00
Evan Cheng
aaccd1d07b Eliminate more * 4 in Thumb1 asm printing for consistency sake. 
llvm-svn: 89325
 2009-11-19 06:31:26 +00:00
Bruno Cardoso Lopes
bf95b9699e - Add sugregister logic to handle f64=(f32,f32). 
- Support mips1 like load/store of doubles:

Instead of:
  sdc $f0, X($3)
Generate:
  swc $f0, X($3)
  swc $f1, X+4($3)

llvm-svn: 89322
 2009-11-19 06:06:13 +00:00
Bruno Cardoso Lopes
2cb8938a96 Only use small sections for non linux targets! 
llvm-svn: 89316
 2009-11-19 05:28:18 +00:00
Bill Wendling
b396532e98 The "ReadOnlyWithRel" enum seems to apply more to what Darwin does with the EH 
exception table than DataRel.

llvm-svn: 89279
 2009-11-19 00:09:14 +00:00
Richard Osborne
fc2d5141a4 Add XCore support for indirectbr / blockaddress. 
llvm-svn: 89273
 2009-11-18 23:20:42 +00:00
Bill Wendling
5ab3ea88a2 Attempt #2: 
Place the EH table in the __TEXT section on MachO. It saves space.

llvm-svn: 89270
 2009-11-18 23:18:46 +00:00
Viktor Kutuzov
036656936e Added getDefaultSubtargetFeatures method to SubtargetFeatures class which returns a correct feature string for given triple. 
llvm-svn: 89236
 2009-11-18 20:20:05 +00:00
David Goodwin
6b56e77397 Add ARMv6 itineraries. 
llvm-svn: 89218
 2009-11-18 18:39:57 +00:00
Bob Wilson
6993e5d049 Fix a few places that were missed when we converted to unified syntax. 
llvm-svn: 89214
 2009-11-18 18:10:35 +00:00
Bob Wilson
6b68bd153a Add a target hook to allow changing the tail duplication limit based on the 
contents of the block to be duplicated.  Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.

llvm-svn: 89187
 2009-11-18 03:34:27 +00:00
Bill Wendling
03a196010e The llvm-gcc front-end and the pass manager use two separate TargetData objects. 
This is probably not confined to *just* these two things.

Anyway, the llvm-gcc front-end may look up the structure layout information for
an abstract type. That information will be stored into a table with the FE's
TD. Instruction combine can come along and also ask for information on that
abstract type, but for a separate TD (the one associated with the pass manager).

After the type is refined, the old structure layout information in the pass
manager's TD file is out of date. If a new type is allocated in the same space
as the old-unrefined type, then the structure type information in the pass
manager's TD file will be wrong, but won't know it.

Fix this by making the TD's structure type information an abstract type user.

llvm-svn: 89176
 2009-11-18 01:03:56 +00:00
Jim Grosbach
d4db2d58ae Enable arm jumpt table adjustment. 
llvm-svn: 89143
 2009-11-17 21:24:11 +00:00
Anton Korobeynikov
f8557956d7 Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6 
alignment imm (in the same way). Fix asmprinting for non-darwin platforms.

llvm-svn: 89137
 2009-11-17 20:04:59 +00:00
Johnny Chen
81b3815eb2 Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to 
distinguish between them and the more generic instructions (add, mov, and ldr).

llvm-svn: 89108
 2009-11-17 17:17:50 +00:00
Evan Cheng
d7cf6167f1 Re-apply 89011. It's not to be blamed. 
llvm-svn: 89081
 2009-11-17 09:51:18 +00:00
Evan Cheng
52159ba00a Revert 89011. Buildbot thinks it might be breaking stuff. 
llvm-svn: 89076
 2009-11-17 09:20:28 +00:00
Jim Grosbach
7fc73a45da When moving a block for table jumps, make sure the prior block terminator 
is analyzable so it can be updated. If it's not, be safe and don't move the
block.

llvm-svn: 89022
 2009-11-17 01:21:04 +00:00
Evan Cheng
6e4430374e MOV64rm should be marked isReMaterializable. 
llvm-svn: 89019
 2009-11-17 00:55:55 +00:00
Evan Cheng
382a91041b A few more instructions that should be marked re-materializable. 
llvm-svn: 89011
 2009-11-17 00:23:22 +00:00
Johnny Chen
d530046ed3 Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to 
0b1110 (ALways).  This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.

llvm-svn: 89000
 2009-11-16 23:57:56 +00:00
Jeffrey Yasskin
0f846dbb3e Make X86-64 in the Large model always emit 64-bit calls. 
The large code model is documented at
http://www.x86-64.org/documentation/abi.pdf and says that calls should
assume their target doesn't live within the 32-bit pc-relative offset
that fits in the call instruction.

To do this, we turn off the global-address->target-global-address
conversion in X86TargetLowering::LowerCall(). The first attempt at
this broke the lazy JIT because it can separate the movabs(imm->reg)
from the actual call instruction. The lazy JIT receives the address of
the movabs as a relocation and needs to record the return address from
the call; and then when that call happens, it needs to patch the
movabs with the newly-compiled target. We could thread the call
instruction into the relocation and record the movabs<->call mapping
explicitly, but that seems to require at least as much new
complication in the code generator as this change.

To fix this, we make lazy functions _always_ go through a call
stub. You'd think we'd only have to force lazy calls through a stub on
difficult platforms, but that turns out to break indirect calls
through a function pointer. The right fix for that is to distinguish
between calls and address-of operations on uncompiled functions, but
that's complex enough to leave for someone else to do.

Another attempt at this defined a new CALL64i pseudo-instruction,
which expanded to a 2-instruction sequence in the assembly output and
was special-cased in the X86CodeEmitter's emitInstruction()
function. That broke indirect calls in the same way as above.

This patch also removes a hack forcing Darwin to the small code model.
Without far-call-stubs, the small code model requires things of the
JITMemoryManager that the DefaultJITMemoryManager can't provide.

Thanks to echristo for lots of testing!

llvm-svn: 88984
 2009-11-16 22:41:33 +00:00
Evan Cheng
78be20d62e - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. 
- Mark MOVUPSrm re-materializable.

llvm-svn: 88974
 2009-11-16 21:56:03 +00:00
Jim Grosbach
2c6e8c5ccc Make the pass class name more explicit. 
llvm-svn: 88964
 2009-11-16 21:13:22 +00:00
Jim Grosbach
736ee00309 make pass name a bit more clear 
llvm-svn: 88961
 2009-11-16 21:03:58 +00:00
Jim Grosbach
62cd0707dd Simplify thumb2 jump table adjustments. Remove unnecessary calculation and 
usage of block sizes and offsets.

llvm-svn: 88935
 2009-11-16 18:58:52 +00:00
Jim Grosbach
eef0542edc clarify comment 
llvm-svn: 88933
 2009-11-16 18:55:47 +00:00
Jim Grosbach
2d074ac39b back off for a bit. tracking down weirdness 
llvm-svn: 88919
 2009-11-16 17:17:48 +00:00
Jim Grosbach
71539bfab0 Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior. 
llvm-svn: 88917
 2009-11-16 17:10:56 +00:00
Bruno Cardoso Lopes
f87fd996e2 Disable ldc1/sdc1 instructions for mips1 targets. 
llvm-svn: 88887
 2009-11-16 04:35:29 +00:00
Bruno Cardoso Lopes
21ca44ba49 - Fix a small bug while handling target constant pools (one param was missing). 
- Add a smarter constant pool loading, instead of:

lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)

Generate:

lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)

llvm-svn: 88886
 2009-11-16 04:33:42 +00:00
Jim Grosbach
1aa571da3c Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874
 2009-11-15 21:45:34 +00:00
Jim Grosbach
8e55bb8826 set the def of the VLD1q64 properly 
llvm-svn: 88873
 2009-11-15 21:05:07 +00:00
Nick Lewycky
b73208f294 Add a complex missed optimization opportunity I came across while investigating 
bug 5438.

llvm-svn: 88855
 2009-11-15 17:51:23 +00:00
Jim Grosbach
4882bbfe05 cleanup. 
llvm-svn: 88812
 2009-11-14 21:33:37 +00:00
Jim Grosbach
4175b4fbf2 Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB. 
llvm-svn: 88805
 2009-11-14 20:10:18 +00:00
Richard Osborne
8748f55236 Add XCore support for arbitrary-sized aggregate returns. 
llvm-svn: 88802
 2009-11-14 19:33:35 +00:00
Anton Korobeynikov
b290c6b8f7 Temporary disable the error - it seems to be too conservative. 
llvm-svn: 88800
 2009-11-14 18:01:41 +00:00
Daniel Dunbar
59040c2825 Add llvm::sys::getHostCPUName, for detecting the LLVM name for the host CPU. 
- This is an initial step towards -march=native support in Clang, and towards
   eliminating host dependencies in the targets. See PR5389.

 - Patch by Roman Divacky!

llvm-svn: 88768
 2009-11-14 10:09:12 +00:00
Sanjiv Gupta
b38d6287b8 revert 88761 as it fails builds. 
llvm-svn: 88762
 2009-11-14 07:22:25 +00:00
Sanjiv Gupta
3db18af363 Fix debug info crashes for PIC16. 
llvm-svn: 88761
 2009-11-14 06:19:49 +00:00
Evan Cheng
9b46e74f42 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745
 2009-11-14 02:55:43 +00:00
Evan Cheng
e43198c166 When expanding t2STRDi8 r, r to two stores, add kill markers correctly. 
llvm-svn: 88734
 2009-11-14 01:50:00 +00:00
Jakob Stoklund Olesen
a077364caa The instruction pointer %RIP is a reserved register on x86_64. 
llvm-svn: 88705
 2009-11-13 21:56:01 +00:00
David Greene
97a1f550d1 Move DebugInfo checks into EmitComments and remove them from 
target-specific AsmPrinters.  Not all comments need DebugInfo.

Re-enable the line numbers comment test.

llvm-svn: 88697
 2009-11-13 21:34:57 +00:00
David Goodwin
e1d06f2239 Allow target to specify regclass for which antideps will only be broken along the critical path. 
llvm-svn: 88682
 2009-11-13 19:52:48 +00:00
Bruno Cardoso Lopes
e3686712f7 Support fp64 immediate zero, this fixes only part of PR5445 
because the testcase is triggering one more bug.

llvm-svn: 88674
 2009-11-13 18:49:59 +00:00
Dale Johannesen
f57a58c4fe Adjust isConstantSplat to allow for big-endian targets. 
PPC is such a target; make it work.

llvm-svn: 87060
 2009-11-13 01:45:18 +00:00
Jim Grosbach
c15c777f81 Block renumbering 
llvm-svn: 87056
 2009-11-13 01:19:24 +00:00
Jim Grosbach
85faa3cff1 use lower case for readability 
llvm-svn: 87054
 2009-11-13 01:17:22 +00:00
David Greene
1a5969d74c Fix a bootstrap failure. 
Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE
interfaces to explicitly request checking for post-frame ptr elimination
operands.  This uses a heuristic so it isn't reliable for correctness.

llvm-svn: 87047
 2009-11-13 00:29:53 +00:00
David Greene
9934b1d063 Make the MachineFunction argument of getFrameRegister const. 
This also fixes a build error.

llvm-svn: 87027
 2009-11-12 21:00:03 +00:00
David Greene
ea251ed2b9 Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a 
machine instruction loads or stores from/to a stack slot.  Unlike
isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be
something other than a pure load/store (e.g. it may be an arithmetic
operation with a memory operand).  This helps AsmPrinter determine when
to print a spill/reload comment.

This is only a hint since we may not be able to figure this out in all
cases.  As such, it should not be relied upon for correctness.

Implement for X86.  Return false by default for other architectures.

llvm-svn: 87026
 2009-11-12 20:55:29 +00:00
David Greene
58e7c6145b Add a bool flag to StackObjects telling whether they reference spill 
slots.  The AsmPrinter will use this information to determine whether to
print a spill/reload comment.

Remove default argument values.  It's too easy to pass a wrong argument
value when multiple arguments have default values.  Make everything
explicit to trap bugs early.

Update all targets to adhere to the new interfaces..

llvm-svn: 87022
 2009-11-12 20:49:22 +00:00
Benjamin Kramer
da70783da7 Add compare_lower and equals_lower methods to StringRef. Switch all users of 
StringsEqualNoCase (from StringExtras.h) to it.

llvm-svn: 87020
 2009-11-12 20:36:59 +00:00
Jim Grosbach
79f45fa2e6 Update TB[BH] layout optimization. Add support for moving the target block 
to directly follow the jump table. Move the layout changes to prior to any
constant island handling.

llvm-svn: 86999
 2009-11-12 17:25:07 +00:00
Evan Cheng
a47f2ea71d Use table to separate opcode from operands. 
llvm-svn: 86965
 2009-11-12 07:16:34 +00:00
Evan Cheng
af90768b3c isLegalICmpImmediate should take a signed integer; code clean up. 
llvm-svn: 86964
 2009-11-12 07:13:11 +00:00
Jim Grosbach
66e301e3ca Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway. 
llvm-svn: 86945
 2009-11-12 03:28:35 +00:00
Bruno Cardoso Lopes
99e65b8707 A real solution for the first part of PR5445 
llvm-svn: 86895
 2009-11-11 23:09:33 +00:00
Evan Cheng
a11308742c Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions. 
llvm-svn: 86858
 2009-11-11 19:05:52 +00:00
Jim Grosbach
9ecdde2be4 Do jump table adjustment before constant island allocation 
llvm-svn: 86857
 2009-11-11 19:04:24 +00:00
Dan Gohman
4631d78a3b Set isBarrier = 1 on return instructions, as they are control barriers. 
llvm-svn: 86851
 2009-11-11 18:11:07 +00:00
Dan Gohman
3045fc7514 Use a tab in INT3's asm string, for consistency. 
llvm-svn: 86850
 2009-11-11 18:07:16 +00:00
Chris Lattner
0dd2fe1e1e another const prop failure. 
llvm-svn: 86848
 2009-11-11 17:54:02 +00:00
Chris Lattner
20da198cb6 add a note 
llvm-svn: 86847
 2009-11-11 17:51:27 +00:00
Jim Grosbach
d7aab5323b The TBB and TBH instructions for Thumb2 are really handy for jump tables, but 
can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.

llvm-svn: 86791
 2009-11-11 02:47:19 +00:00
Daniel Dunbar
9789af1797 llvm-gcc/clang don't (won't?) need this hack. 
llvm-svn: 86769
 2009-11-11 00:28:38 +00:00
Chris Lattner
bc9996444e add a note 
llvm-svn: 86756
 2009-11-10 23:47:45 +00:00
Chris Lattner
67aac80393 I did this a week or two ago 
llvm-svn: 86754
 2009-11-10 23:40:49 +00:00
Dan Gohman
b937f9d590 Don't mark conditional branch instructions as control barriers. 
llvm-svn: 86732
 2009-11-10 22:16:57 +00:00
Bill Wendling
1176227990 Modify how the prologue encoded the "move" information for the FDE. GCC 
generates a sequence similar to this:

__Z4funci:
LFB2:
        mflr r0
LCFI0:
        stmw r30,-8(r1)
LCFI1:
        stw r0,8(r1)
LCFI2:
        stwu r1,-80(r1)
LCFI3:
        mr r30,r1
LCFI4:

where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:

Leh_func_begin1:
        mflr r0
        stw r31, 20(r1)
        stw r0, 8(r1)
Llabel1:
        stwu r1, -80(r1)
Llabel2:
        mr r31, r1

Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.

llvm-svn: 86729
 2009-11-10 22:14:04 +00:00
Evan Cheng
58fbf886bb Change Thumb1 address mode printing, instead of 
[r0, #2 * 4]
Now
[r0, #8]

This makes Thumb2 assembly more uniform and frankly the scale doesn't add much.

llvm-svn: 86707
 2009-11-10 19:48:13 +00:00
Evan Cheng
2c0fc2e713 Add a comment. 
llvm-svn: 86706
 2009-11-10 19:44:56 +00:00
Daniel Dunbar
d8e09f2f13 Add a monstrous hack to improve X86ISelDAGToDAG compile time. 
- Force NDEBUG on in any Release build. This drops the compile time to ~100s
   from ~600s, in Release mode.

 - This may just be a temporary workaround, I don't know the true nature of the
   gcc-4.2 compile time performance problem.

llvm-svn: 86695
 2009-11-10 18:24:37 +00:00
Bruno Cardoso Lopes
b662991460 Fix PR5445 
llvm-svn: 86651
 2009-11-10 02:35:13 +00:00
Jeffrey Yasskin
23ac706aab Fix DenseMap iterator constness. 
This patch forbids implicit conversion of DenseMap::const_iterator to
DenseMap::iterator which was possible because DenseMapIterator inherited
(publicly) from DenseMapConstIterator. Conversion the other way around is now
allowed as one may expect.

The template DenseMapConstIterator is removed and the template parameter
IsConst which specifies whether the iterator is constant is added to
DenseMapIterator.

Actually IsConst parameter is not necessary since the constness can be
determined from KeyT but this is not relevant to the fix and can be addressed
later.

Patch by Victor Zverovich!

llvm-svn: 86636
 2009-11-10 01:02:17 +00:00
David Goodwin
93a4f29c67 Fixed to address code review. No functional changes. 
llvm-svn: 86634
 2009-11-10 00:48:55 +00:00
David Goodwin
538f9c25f8 Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 
llvm-svn: 86628
 2009-11-10 00:15:47 +00:00
Jim Grosbach
ed9f847274 Now that the default is 'enabled,' a separate command line option for ARM is 
not necessary.

llvm-svn: 86621
 2009-11-09 23:11:45 +00:00
Jim Grosbach
b934f9ccd4 Enable dynamic stack realignment by default. 
llvm-svn: 86604
 2009-11-09 22:32:40 +00:00
Jim Grosbach
3e2968ee4b Set dynamic stack realignment to real values. 
llvm-svn: 86602
 2009-11-09 22:32:03 +00:00
Bill Wendling
86f32da164 Similar to r86588, but for Darwin this time. 
llvm-svn: 86592
 2009-11-09 21:45:26 +00:00
Bill Wendling
fab993b096 The jump table was being generated before the end label for exception handling 
was generated. This caused code like this:

## The asm code for the function
        .section        __TEXT,__const
        .align  2
lJTI11_0:
LJTI11_0:
        .long    LBB11_16
        .long    LBB11_4
        .long    LBB11_5
        .long    LBB11_6
        .long    LBB11_7
        .long    LBB11_8
        .long    LBB11_9
        .long    LBB11_10
        .long    LBB11_11
        .long    LBB11_12
        .long    LBB11_13
        .long    LBB11_14
Leh_func_end11:   ## <---now in the wrong section!

The `Leh_func_end11' would then end up in the wrong section, causing the
resulting EH frame information to be wrong:

__ZL11CheckRightsjPKcbRbRP6NSData.eh:
    .set    Lset500eh,Leh_frame_end11-Leh_frame_begin11
    .long   Lset500eh  ; Length of Frame Information Entry                                                                                                                   
Leh_frame_begin11:
    .long   Leh_frame_begin11-Leh_frame_common
    .long   Leh_func_begin11-.
    .set    Lset501eh,Leh_func_end11-Leh_func_begin11
    .long   Lset501eh                                   ; FDE address range                                                                                                                                   
`Lset501eh' is now something huge instead of the real value.

The X86 back-end generates the jump table after the EH information is
emitted. Do the same here.

llvm-svn: 86588
 2009-11-09 21:20:14 +00:00
Jim Grosbach
5b33ce12e3 Work around assembler not recognizing #0.0 form immediate for vmcp 
llvm-svn: 86548
 2009-11-09 15:27:51 +00:00
Bruno Cardoso Lopes
8bedc8bf3b Fix PR5149. 
http://llvm.org/bugs/show_bug.cgi?id=5149

llvm-svn: 86543
 2009-11-09 14:27:49 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00