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Author SHA1 Message Date
Chris Lattner
c025bec9e1 this isn't a memset, we do convert dest[i] to one though :) 
llvm-svn: 124097
 2011-01-24 02:32:00 +00:00
Chris Lattner
1f9ed3b437 with recent work, we now optimize this into: 
define i32 @foo(i32 %x) nounwind readnone ssp {
entry:
  %tobool = icmp eq i32 %x, 0
  %tmp5 = select i1 %tobool, i32 2, i32 1
  ret i32 %tmp5
}

llvm-svn: 124091
 2011-01-24 01:12:18 +00:00
Anders Carlsson
ba7114ef4c Add a memset loop that LoopIdiomRecognize doesn't recognize. 
llvm-svn: 124082
 2011-01-23 20:31:00 +00:00
Rafael Espindola
47bc703c55 Initialize MCNoExecStack. 
llvm-svn: 124079
 2011-01-23 18:50:12 +00:00
Rafael Espindola
547873da60 Add support for the --noexecstack option. 
llvm-svn: 124077
 2011-01-23 17:55:27 +00:00
Ted Kremenek
880c19c032 Null initialize a few variables flagged by 
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.

llvm-svn: 124073
 2011-01-23 17:05:06 +00:00
Rafael Espindola
aefd549139 Delay the creation of eh_frame so that the user can change the defaults. 
Add support for SHT_X86_64_UNWIND.

llvm-svn: 124059
 2011-01-23 05:43:40 +00:00
Rafael Espindola
492ad6ca06 Remove more duplicated code. 
llvm-svn: 124056
 2011-01-23 04:43:11 +00:00
Rafael Espindola
59c1246cee Remove duplicated code. 
llvm-svn: 124054
 2011-01-23 04:28:49 +00:00
Venkatraman Govindaraju
66369057ae Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 
llvm-svn: 124030
 2011-01-22 13:05:16 +00:00
Venkatraman Govindaraju
3c37c9914f Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used. 
llvm-svn: 124027
 2011-01-22 11:36:24 +00:00
Venkatraman Govindaraju
c20beed917 Sparc backend: 
Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.

llvm-svn: 123997
 2011-01-21 22:00:00 +00:00
Evan Cheng
0dfe28a9b5 Last round of fixes for movw + movt global address codegen. 
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991
 2011-01-21 18:55:51 +00:00
Bruno Cardoso Lopes
2f96371a7a Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975
 2011-01-21 14:07:40 +00:00
Venkatraman Govindaraju
6a083c355b Implement support for byval arguments in Sparc backend. 
llvm-svn: 123974
 2011-01-21 14:00:01 +00:00
Andrew Trick
7155e98904 Convert -enable-sched-cycles and -enable-sched-hazard to -disable 
flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.

llvm-svn: 123969
 2011-01-21 05:51:33 +00:00
Evan Cheng
52fe62c996 Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative 
value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.

llvm-svn: 123949
 2011-01-20 23:55:07 +00:00
Bruno Cardoso Lopes
6aeb2e320f Fix the encoding and parsing of clrex instruction 
llvm-svn: 123936
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
c0f87c11d6 Change instruction names for consistency 
llvm-svn: 123930
 2011-01-20 18:36:07 +00:00
Bruno Cardoso Lopes
5f06c0aa3b Add cdp/cdp2 instructions for thumb/thumb2 
llvm-svn: 123929
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
3584c02d83 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
75712e8a7a Add mcr*2 and mr*c2 support to thumb2 targets 
llvm-svn: 123919
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
f377d1721e Add mcr* and mr*c support to thumb targets 
llvm-svn: 123917
 2011-01-20 16:35:57 +00:00
Kalle Raiskila
070fb5e54d Allow sign-extending of i8 and i16 to i128 on SPU. 
llvm-svn: 123912
 2011-01-20 15:49:06 +00:00
Bruno Cardoso Lopes
0312bb222e Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. 
llvm-svn: 123910
 2011-01-20 13:17:59 +00:00
Evan Cheng
d9fdc9771e Correct itinerary entry for t2MOV_pic_ga_add_pc. 
llvm-svn: 123907
 2011-01-20 08:43:03 +00:00
Evan Cheng
6dc21c7358 Sorry, several patches in one. 
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905
 2011-01-20 08:34:58 +00:00
Venkatraman Govindaraju
5280b2876f Sparc backend: Implements a delay slot filler that attempt to fill delay slots 
with useful instructions.

llvm-svn: 123884
 2011-01-20 05:08:26 +00:00
Bruno Cardoso Lopes
0f7a30b1cb Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
llvm-svn: 123837
 2011-01-19 16:56:52 +00:00
Daniel Dunbar
dd1dd698f0 ARM/ISel: Factor out isScaledConstantInRange() helper. 
llvm-svn: 123823
 2011-01-19 15:12:16 +00:00
Andrew Trick
305613b87a For ARM subtargets with useNEONForSinglePrecisionFP, double count uses 
of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.

llvm-svn: 123811
 2011-01-19 02:35:27 +00:00
Andrew Trick
cf6999ed86 whitespace 
llvm-svn: 123810
 2011-01-19 02:26:13 +00:00
Evan Cheng
7e2b414953 Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols. 
llvm-svn: 123809
 2011-01-19 02:16:49 +00:00
Bruno Cardoso Lopes
e0f8fee637 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes
82c6fe3dfe Fix MRS encoding for arm and thumb. 
llvm-svn: 123778
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
6e4c5af01e Fix the encoding of t2ISB by using the right class and also parse it correctly 
llvm-svn: 123776
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes
c1e21b06b9 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
llvm-svn: 123772
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes
94247155c4 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
llvm-svn: 123770
 2011-01-18 20:45:56 +00:00
Jim Grosbach
6de3a4f76f Add a FIXME. 
llvm-svn: 123769
 2011-01-18 19:59:19 +00:00
Bruno Cardoso Lopes
13cefe452d Ensure Mips::GP is properly reloaded after a function call. Patch by Sasa Stankovic 
llvm-svn: 123768
 2011-01-18 19:50:18 +00:00
Bruno Cardoso Lopes
2d509b8b40 Negative zero is not legal on mips. Patch by Sasa Stankovic 
llvm-svn: 123766
 2011-01-18 19:41:41 +00:00
Bruno Cardoso Lopes
542853bcd7 Handle (i32,i32) => f64 in a cleaner way. Patch by Sasa Stankovic 
llvm-svn: 123763
 2011-01-18 19:38:25 +00:00
Bruno Cardoso Lopes
6c5db0236a Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka 
llvm-svn: 123760
 2011-01-18 19:29:17 +00:00
Chris Lattner
08e1bf567f add a note 
llvm-svn: 123752
 2011-01-18 07:47:48 +00:00
Venkatraman Govindaraju
ecf49c6279 SPARC backend: Modified LowerCall and LowerFormalArguments so that they use CallingConv assignments. 
llvm-svn: 123749
 2011-01-18 06:09:55 +00:00
Daniel Dunbar
12dd48769d McARM: Use accessors where appropriate. 
llvm-svn: 123746
 2011-01-18 05:55:27 +00:00
Daniel Dunbar
51fef8d445 McARM: Fill in ASMOperand::dump() for memory operands. 
llvm-svn: 123745
 2011-01-18 05:55:21 +00:00
Daniel Dunbar
f966e16cb0 McARM: Make ARMOperand use a union where appropriate. 
llvm-svn: 123744
 2011-01-18 05:55:15 +00:00
Daniel Dunbar
0cff3f953b McARM: Unify ParseMemory() successfull return. 
llvm-svn: 123740
 2011-01-18 05:34:24 +00:00
Daniel Dunbar
3cb5e8b0cb McARM: Early exit on failure (NEFC). 
llvm-svn: 123739
 2011-01-18 05:34:17 +00:00
Daniel Dunbar
9ea6873c89 McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic. 
Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb().

llvm-svn: 123738
 2011-01-18 05:34:11 +00:00
Daniel Dunbar
8d7ed1f6a8 McARM: Add a variety of asserts on the sanity of memory operands. 
llvm-svn: 123737
 2011-01-18 05:34:05 +00:00
Daniel Dunbar
aa5e17f3a7 McARM: Use a consistent marker for not-set OffsetRegNum. 
llvm-svn: 123736
 2011-01-18 05:33:57 +00:00
Daniel Dunbar
ba39b2fdc1 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
llvm-svn: 123722
 2011-01-18 03:06:03 +00:00
Eric Christopher
e8aa8b114f The stub routine that we're calling uses test and so clobbers 
the flags.

llvm-svn: 123712
 2011-01-18 01:37:20 +00:00
Chris Lattner
047388c197 minor change to rafael's recent patches: if something is 
constant but requires a unique address, we can still put it in a
readonly section, just not a mergable one.

llvm-svn: 123711
 2011-01-18 01:23:44 +00:00
Jeffrey Yasskin
5f5e1f5ef1 Remove unused variables found by gcc-4.6's -Wunused-but-set-variable. 
llvm-svn: 123707
 2011-01-18 00:51:23 +00:00
Douglas Gregor
49f7d8c38c Add a missing <cctype> include, from Joerg Sonnenberger! 
llvm-svn: 123670
 2011-01-17 19:17:01 +00:00
Kalle Raiskila
7401b2a1db Split up RotateShift itinerary in SPU. 
'rotq*' and 'shlq*' instructions go to the odd pipeline,
wheras the inter-vector equivalents 'rot*', 'shl*' go 
to the even.

llvm-svn: 123622
 2011-01-17 13:33:19 +00:00
Kalle Raiskila
8eaf0e83d5 Don't crash SPU BE with memory accesses with big alignmnet. 
llvm-svn: 123620
 2011-01-17 11:59:20 +00:00
Evan Cheng
53ec6fc591 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. 
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
 2011-01-17 08:03:18 +00:00
Anton Korobeynikov
2a9d9ef36f Provide instruction sizes for ARMv5 variants of MUL instructions. 
This fixes PR8987

llvm-svn: 123598
 2011-01-16 21:28:33 +00:00
Anders Carlsson
d0103ebf92 Update README.txt to remove the DAE enhancement. 
llvm-svn: 123597
 2011-01-16 21:26:15 +00:00
Rafael Espindola
7933fffe38 Only put unnamed_addr constants in mergeable sections. Fixes PR8297. 
llvm-svn: 123585
 2011-01-16 17:19:34 +00:00
Chris Lattner
dde85de90f fix PR8514, a bug where the "heroic" transformation of shift/and 
into and/shift would cause nodes to move around and a dangling pointer
to happen.  The code tried to avoid this with a HandleSDNode, but 
got the details wrong.

llvm-svn: 123578
 2011-01-16 08:48:11 +00:00
Chris Lattner
91f1b21cf1 add some commentary 
llvm-svn: 123572
 2011-01-16 06:39:44 +00:00
Evan Cheng
144b435a15 Spill R4 if it's going to be used to restore SP from FP. 
llvm-svn: 123567
 2011-01-16 05:14:33 +00:00
Venkatraman Govindaraju
fe346f6cba Implement AnalyzeBranch in Sparc Backend. 
llvm-svn: 123561
 2011-01-16 03:15:11 +00:00
Chris Lattner
24ea7f696e fix PR8981, a crash trying to form a conditional inc with a floating point compare. 
llvm-svn: 123560
 2011-01-16 02:56:53 +00:00
Chris Lattner
c4d1d86d3e reapply my fix for PR8961 with a tweak to properly handle 
multi-instruction sequences like calls.  Many thanks to Jakob for
finding a testcase.

llvm-svn: 123559
 2011-01-16 02:27:38 +00:00
Chandler Carruth
a3261fcca5 Simplify a README.txt entry significantly to expose the core issue. 
llvm-svn: 123556
 2011-01-16 01:40:23 +00:00
Eric Christopher
d675e0b362 80-col. 
llvm-svn: 123505
 2011-01-15 00:25:09 +00:00
Bob Wilson
e6b8ba1ae4 Fix a comment. 
llvm-svn: 123497
 2011-01-15 00:09:18 +00:00
Eric Christopher
b00cef51d8 Fix 80-cols. 
llvm-svn: 123494
 2011-01-14 23:50:53 +00:00
Ted Kremenek
4b09cdedb2 'HiReg' is written but never read. Nuke its 
declaration and its assignments.

Found by clang static analyzer.

llvm-svn: 123486
 2011-01-14 22:34:13 +00:00
Anton Korobeynikov
1f9df99db1 Add a possibility to switch between CFI directives- and table-based frame description emission. Currently all the backends use table-based stuff. 
llvm-svn: 123476
 2011-01-14 21:58:08 +00:00
Anton Korobeynikov
6b2f110a3d Cleanup 
llvm-svn: 123475
 2011-01-14 21:57:58 +00:00
Chris Lattner
eba719204c revert my fastisel patch again which apparently still gives the 
llvm-gcc-i386-linux-selfhost buildbot heartburn...

llvm-svn: 123431
 2011-01-14 06:14:33 +00:00
Chris Lattner
ee950eeb24 reapply r123414 now that the botz are calmed down and the fix is already in. 
llvm-svn: 123427
 2011-01-14 04:24:28 +00:00
Evan Cheng
0cdd5547f1 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. 
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.

llvm-svn: 123424
 2011-01-14 02:38:49 +00:00
Chris Lattner
349735530b r123414 broke llvm-gcc bootstrap apparently, revert 
llvm-svn: 123422
 2011-01-14 02:07:32 +00:00
Chris Lattner
5baec05809 fix PR8961 - a fast isel miscompilation where we'd insert a new instruction 
after sext's generated for addressing that got folded.  Previously we compiled
test5 into:

_test5:                                 ## @test5
## BB#0:
        movq    -8(%rsp), %rax          ## 8-byte Reload
        movq    (%rdi,%rax), %rdi
        addq    %rdx, %rdi
        movslq  %esi, %rax
        movq    %rax, -8(%rsp)          ## 8-byte Spill
        movq    %rdi, %rax
        ret

which is insane and wrong.  Now we produce:

_test5:                                 ## @test5
## BB#0:
	movslq	%esi, %rax
	movq	(%rdi,%rax), %rax
	addq	%rdx, %rax
	ret

llvm-svn: 123414
 2011-01-14 00:01:01 +00:00
Owen Anderson
58bcb5d7f2 Recognize alternative register names like ip -> r12. 
Fixes <rdar://problem/8857982>.

llvm-svn: 123409
 2011-01-13 22:50:36 +00:00
Jakob Stoklund Olesen
918de3a3b8 Fix a few more places that should use MBB::getLastNonDebugInstr(). 
llvm-svn: 123408
 2011-01-13 22:47:43 +00:00
Chris Lattner
d2d217dc46 typo 
llvm-svn: 123406
 2011-01-13 22:11:56 +00:00
Chris Lattner
6745cd150c memcpy + metadata = bliss :) 
llvm-svn: 123405
 2011-01-13 22:08:15 +00:00
Owen Anderson
18dfab2332 Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting 
the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.

With this, we can properly pretty-print and encode assembly like:
	mrc p15, #0, r3, c13, c0, #3

Fixes <rdar://problem/8857858>.

llvm-svn: 123404
 2011-01-13 21:46:02 +00:00
Jakob Stoklund Olesen
0f2b9d9dc4 Teach frame lowering to ignore debug values after the terminators. 
llvm-svn: 123399
 2011-01-13 21:28:52 +00:00
Bob Wilson
569cd41943 Tidy comments, indentation, and 80-column violations. 
llvm-svn: 123397
 2011-01-13 21:10:12 +00:00
Kevin Enderby
eee2f3489b Fix ARMAsmParser::ParseOperand() to allow it to parse . as a branch target and 
directional local labels like 1f and 2b.

llvm-svn: 123393
 2011-01-13 20:32:36 +00:00
Jim Grosbach
767dfbf685 When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctly 
set up the source operands. The original instr has an immediate operand that
should be replaced with the frame reg operand rather than just adding the
reg operand. Previously, the instruction ended up with too many operands
causing an assert() when adding the default predicate. rdar://8825456

llvm-svn: 123387
 2011-01-13 19:16:48 +00:00
Evan Cheng
cc474b4864 Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step 
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369
 2011-01-13 07:58:56 +00:00
Eric Christopher
3821f63f4b Experiment with changing the default 32-bit linux stack alignment to 
16 bytes for PR8969. Update all testcases accordingly.

llvm-svn: 123367
 2011-01-13 06:47:10 +00:00
Kevin Enderby
1f82daa2d8 Add a FIXME and two asserts for now in the ARMAsmParser when it sees .code 16 or 
.code 32 if the TargetMachine's isThumb() boolean does not match.  The correct
fix is to switch ARM subtargets at that point and is tracked by rdar://8856789
which is bigger task.

llvm-svn: 123353
 2011-01-13 01:07:01 +00:00
Jason W Kim
af9782e470 Change call to Error() to assert() 
llvm-svn: 123350
 2011-01-13 00:27:00 +00:00
Jason W Kim
5c1d7cc0ca Added clarifying comment 
llvm-svn: 123341
 2011-01-12 23:25:02 +00:00
Jason W Kim
6464be5b92 JimG sez: "The value-kinds look like masks, but they're not consistently used 
that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.

llvm-svn: 123340
 2011-01-12 23:21:49 +00:00
Bill Wendling
e82361731d Sort the register list based on the *actual* register numbers rather than the 
enum values we give to them. <rdar://problem/8823730>

llvm-svn: 123321
 2011-01-12 21:20:59 +00:00
Matt Beaumont-Gay
fc76b0ce6e Mostly undo r123297, but move the default case in EvaluateAsPCRel to the top 
of the switch block to appease GCC.

llvm-svn: 123317
 2011-01-12 18:02:55 +00:00
Nick Lewycky
fb3f7c11f1 Add another note taken from the gcc bugzilla. 
llvm-svn: 123315
 2011-01-12 09:06:19 +00:00