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20395 Commits

Author SHA1 Message Date
Craig Topper
4cbe88ceba Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path. 
llvm-svn: 147335
 2011-12-29 03:09:33 +00:00
Eli Friedman
db54b4b68f Fix type-checking for load transformation which is not legal on floating-point types. PR11674. 
llvm-svn: 147323
 2011-12-28 21:24:44 +00:00
Elena Demikhovsky
9b4613ff14 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. 
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.

llvm-svn: 147308
 2011-12-28 08:14:01 +00:00
Benjamin Kramer
c64fcf4a95 Clean up some Release build warnings. 
llvm-svn: 147289
 2011-12-27 11:41:05 +00:00
Craig Topper
9c07745da9 Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. 
llvm-svn: 147287
 2011-12-27 06:27:23 +00:00
Venkatraman Govindaraju
d9c90c9fa5 Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks. 
llvm-svn: 147269
 2011-12-25 18:50:24 +00:00
Rafael Espindola
504588a7a3 Section relative fixups are a coff concept, not a x86 one. Replace the 
x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4.

llvm-svn: 147252
 2011-12-24 14:47:52 +00:00
Chandler Carruth
7a5c52fadf Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the 
LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type

We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]

llvm-svn: 147251
 2011-12-24 12:12:34 +00:00
Chandler Carruth
82b7a7478b Add systematic testing for cttz as well, and fix the bug I spotted by 
inspection earlier.

llvm-svn: 147250
 2011-12-24 11:46:10 +00:00
Benjamin Kramer
facca1025b Chandler fixed this. 
llvm-svn: 147247
 2011-12-24 11:23:32 +00:00
Chandler Carruth
48f5be6ce0 Expand more when we have a nice 'tzcnt' instruction, to avoid generating 
'bsf' instructions here.

This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.

llvm-svn: 147246
 2011-12-24 11:11:38 +00:00
Chandler Carruth
9ef50ef1f7 Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the 
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:

  (sizeof(x)*8 - 1) ^ __builtin_clz(x)

Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.

The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.

Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.

These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.

llvm-svn: 147244
 2011-12-24 10:55:54 +00:00
Jakob Stoklund Olesen
5ab8f2cf5f Fix Comments. 
llvm-svn: 147238
 2011-12-24 04:17:01 +00:00
Akira Hatanaka
d810aba662 Add MachineMemOperands to instructions generated in storeRegToStackSlot or 
loadRegFromStackSlot. 

llvm-svn: 147235
 2011-12-24 03:11:18 +00:00
Akira Hatanaka
7cb229496e Detect unaligned loads/stores that have been added for Mips64 support. 
llvm-svn: 147234
 2011-12-24 03:07:37 +00:00
Akira Hatanaka
f88c8c8d68 If target ABI is N64, LEA should be daddiu. 
llvm-svn: 147232
 2011-12-24 02:59:27 +00:00
Rafael Espindola
2fc741dfac Move x86 specific bits of the COFF writer to lib/Target/X86. 
llvm-svn: 147231
 2011-12-24 02:14:02 +00:00
Jakob Stoklund Olesen
c97d7d26bd Experimental support for aligned NEON spills. 
ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.

Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.

This feature is off by default, controlled by an -align-neon-spills
command line option.

llvm-svn: 147211
 2011-12-23 00:36:18 +00:00
Bob Wilson
310117c1ea Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138> 
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used.  This
caused massive failures on the testsuite when compiling for Thumb1.  While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.

llvm-svn: 147204
 2011-12-22 23:39:48 +00:00
Chad Rosier
32c63b4265 Fix 80-column violations. 
llvm-svn: 147192
 2011-12-22 22:35:21 +00:00
Jim Grosbach
a678ad9ecc ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

llvm-svn: 147189
 2011-12-22 22:19:05 +00:00
Bob Wilson
63bc016e30 Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp. 
Noticed by inspection; I don't have a testcase for this.

llvm-svn: 147188
 2011-12-22 22:12:44 +00:00
Jim Grosbach
59fccb5809 Tidy up. Use predicate function a bit more liberally. 
llvm-svn: 147184
 2011-12-22 22:02:35 +00:00
Rafael Espindola
eba1c0eb00 Fix incorrect relocation generation. Patch by Kristof Beyls. 
Fixes PR11214.

llvm-svn: 147180
 2011-12-22 21:36:43 +00:00
Jim Grosbach
06dffd2643 ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns. 
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

llvm-svn: 147170
 2011-12-22 19:55:21 +00:00
Jim Grosbach
5824007e4d Remove some bogus comments. 
llvm-svn: 147169
 2011-12-22 19:45:01 +00:00
Jim Grosbach
970c4cab9e ARM pre-UAL aliases. fcmp[sd]. 
llvm-svn: 147158
 2011-12-22 19:20:45 +00:00
Rafael Espindola
1c75ae90fa Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting 
it. It does need some some tests...

llvm-svn: 147154
 2011-12-22 18:38:06 +00:00
Jim Grosbach
100e3aaffa ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

llvm-svn: 147153
 2011-12-22 18:04:04 +00:00
Jim Grosbach
90f8398ee6 ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. 
llvm-svn: 147152
 2011-12-22 17:37:00 +00:00
Jim Grosbach
8ca95cbf58 Tidy up. Trailing whitespace. 
llvm-svn: 147151
 2011-12-22 17:17:10 +00:00
Jim Grosbach
65cd6c7acc Nuke invalid comment from copy/paste. 
llvm-svn: 147150
 2011-12-22 17:04:50 +00:00
Rafael Espindola
3ed0f04e50 Move the Mips only bits of the ELF writer to lib/Target/Mips. 
llvm-svn: 147133
 2011-12-22 03:03:17 +00:00
Rafael Espindola
57dea1bf84 Make the virtual methods in ARMELFObjectWriter public. 
llvm-svn: 147132
 2011-12-22 02:58:12 +00:00
Rafael Espindola
82d61c8b38 Move the MBlaze ELF writer bits to lib/Target/MBlaze. 
llvm-svn: 147129
 2011-12-22 02:28:24 +00:00
Rafael Espindola
b3756d8e4d Fix cmake. 
llvm-svn: 147126
 2011-12-22 02:06:17 +00:00
Rafael Espindola
9c71db357e Move PPC bits to lib/Target/PowerPC. 
llvm-svn: 147124
 2011-12-22 01:57:09 +00:00
Rafael Espindola
6f3a1698f3 Hopefully fix the cmake build. 
llvm-svn: 147121
 2011-12-22 01:11:01 +00:00
Rafael Espindola
6f21886d7e Fix name in comments. 
llvm-svn: 147119
 2011-12-22 01:06:53 +00:00
Akira Hatanaka
e7bcf63d98 Local dynamic TLS model for direct object output. Create the correct TLS MIPS 
ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118
 2011-12-22 01:05:17 +00:00
Richard Smith
9b355262f5 Unbreak cmake build after r147115. 
llvm-svn: 147117
 2011-12-22 01:03:35 +00:00
Rafael Espindola
ee837037ee Move the ARM specific parts of the ELF writer to Target/ARM. 
llvm-svn: 147115
 2011-12-22 00:37:50 +00:00
Jim Grosbach
1b11b334a4 ARM NEON mnemonic aliase for vrecpeq. 
llvm-svn: 147109
 2011-12-21 23:52:37 +00:00
Jim Grosbach
7d31680e2d ARM VFP optional data type on VMOV GPR<-->SPR. 
llvm-svn: 147104
 2011-12-21 23:24:15 +00:00
Jim Grosbach
35b5afad26 ARM NEON optional data type on VSWP instructions. 
llvm-svn: 147103
 2011-12-21 23:09:28 +00:00
Jim Grosbach
64df852f5b ARM NEON mnemonic aliases for vzipq and vswpq. 
llvm-svn: 147102
 2011-12-21 23:04:33 +00:00
Jim Grosbach
88eacffd72 ARM asm parser should be more lenient w/ .thumb_func directive. 
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

llvm-svn: 147100
 2011-12-21 22:30:16 +00:00
Jim Grosbach
2bbc41fa26 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096
 2011-12-21 21:04:19 +00:00
Chad Rosier
98251404f7 Fix 80-column violations. 
llvm-svn: 147095
 2011-12-21 20:59:09 +00:00
Jim Grosbach
91faf5d15f Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094
 2011-12-21 20:54:00 +00:00
Jakob Stoklund Olesen
893037ce23 Move common code into an MRI function. 
llvm-svn: 147071
 2011-12-21 19:50:05 +00:00
Jim Grosbach
f7236d1084 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
llvm-svn: 147069
 2011-12-21 19:40:55 +00:00
Chad Rosier
4e4bfcaa90 No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't 
necessary.  Please chime in if I'm mistaken.

llvm-svn: 147065
 2011-12-21 19:14:52 +00:00
Chad Rosier
c2f31859cc Fix a couple of copy-n-paste bugs. Noticed by George Russell! 
llvm-svn: 147064
 2011-12-21 18:56:22 +00:00
Rafael Espindola
8c9b0dea02 Move the X86 specific bits of the ELF writer to the Target/X86 directory. 
Other targets will follow shortly.

llvm-svn: 147060
 2011-12-21 17:30:17 +00:00
Rafael Espindola
f9c7f9e3f3 Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059
 2011-12-21 17:00:36 +00:00
Craig Topper
496932a88a Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. 
llvm-svn: 147046
 2011-12-21 08:06:52 +00:00
Craig Topper
e2e670bee5 Fix typo in a couple comments 
llvm-svn: 147045
 2011-12-21 06:30:53 +00:00
Evan Cheng
fb22f64814 Fix a couple of copy-n-paste bugs. Noticed by George Russell. 
llvm-svn: 147032
 2011-12-21 03:04:10 +00:00
Jim Grosbach
2c2140a128 ARM assembly parsing allows constant expressions for lane indices. 
llvm-svn: 147028
 2011-12-21 01:19:23 +00:00
Jim Grosbach
6bd1044b03 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Akira Hatanaka
4ab17eaca0 Fix bug in zero-store peephole pattern reported in pr11615. 
The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024
 2011-12-21 00:31:10 +00:00
Akira Hatanaka
0af792d12b Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.

llvm-svn: 147022
 2011-12-21 00:20:27 +00:00
Akira Hatanaka
6454b0ffc1 Expand 64-bit CTPOP and CTTZ. 
llvm-svn: 147021
 2011-12-21 00:14:05 +00:00
Akira Hatanaka
0cc0498ea1 Expand 64-bit atomic load and store. 
llvm-svn: 147019
 2011-12-21 00:02:58 +00:00
Akira Hatanaka
2d293d2f4c Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
 2011-12-20 23:56:43 +00:00
Akira Hatanaka
fa96454cb4 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015
 2011-12-20 23:47:44 +00:00
Akira Hatanaka
6f31d220e7 64-bit uint-fp conversion nodes are expanded. 
llvm-svn: 147014
 2011-12-20 23:40:56 +00:00
Akira Hatanaka
02fe8adb97 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
llvm-svn: 147013
 2011-12-20 23:35:46 +00:00
Akira Hatanaka
507cdacdde Set the correct stack pointer register that should be saved or restored. 
llvm-svn: 147012
 2011-12-20 23:28:36 +00:00
Jim Grosbach
7baaa0fc64 ARM .req register name aliases are case insensitive, just like regnames. 
llvm-svn: 147009
 2011-12-20 23:11:00 +00:00
Akira Hatanaka
2e4f1786b1 Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008
 2011-12-20 23:10:57 +00:00
Akira Hatanaka
8e3e6b14c8 Fix indentation. 
llvm-svn: 147007
 2011-12-20 22:58:01 +00:00
Akira Hatanaka
f728a1b2c5 64-bit data directive. 
llvm-svn: 147005
 2011-12-20 22:52:19 +00:00
Akira Hatanaka
ad193d95ae 32-to-64-bit sext_inreg pattern. 
llvm-svn: 147004
 2011-12-20 22:40:40 +00:00
Akira Hatanaka
13f23f5895 Add 64-bit extload patterns. 
llvm-svn: 147003
 2011-12-20 22:36:08 +00:00
Akira Hatanaka
ed1a29d5c2 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.

llvm-svn: 147001
 2011-12-20 22:33:53 +00:00
Jim Grosbach
ff31b81fe2 Move comment to appropriate place. 
llvm-svn: 147000
 2011-12-20 22:26:38 +00:00
Akira Hatanaka
8728f4ed69 Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999
 2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
2b24e1eac4 Heed spill slot alignment on ARM. 
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

llvm-svn: 146997
 2011-12-20 22:15:04 +00:00
Akira Hatanaka
1af9c41014 Revert part of r146995 that was accidentally commmitted. 
llvm-svn: 146996
 2011-12-20 22:09:36 +00:00
Akira Hatanaka
9c5e4d3b90 32-to-64-bit sign extension pattern. 
llvm-svn: 146995
 2011-12-20 22:06:20 +00:00
Akira Hatanaka
dba6358adc Add a pattern for matching zero-store with 64-bit address. The pattern is enabled 
only when the target ABI is N64. 

llvm-svn: 146992
 2011-12-20 21:50:49 +00:00
Jim Grosbach
8978194025 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Jim Grosbach
8156a5dcee ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Evan Cheng
46b085721a ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
llvm-svn: 146981
 2011-12-20 18:26:50 +00:00
Jason W Kim
139dd49440 First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

llvm-svn: 146977
 2011-12-20 17:38:12 +00:00
Elena Demikhovsky
b37883fe87 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]

llvm-svn: 146975
 2011-12-20 13:34:28 +00:00
Chandler Carruth
7564e8371a Begin teaching the X86 target how to efficiently codegen patterns that 
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

llvm-svn: 146974
 2011-12-20 11:19:37 +00:00
Chandler Carruth
1663697160 Fix up the CMake build for the new files added in r146960, they're 
likely to stay either way that discussion ends up resolving itself.

llvm-svn: 146966
 2011-12-20 08:42:11 +00:00
David Blaikie
576aba04f1 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 
llvm-svn: 146960
 2011-12-20 02:50:00 +00:00
Bob Wilson
8439df9506 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. 
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers.  But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore.  Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early.  This also more accurately reflects
when the registers are clobbered.

llvm-svn: 146949
 2011-12-20 01:29:27 +00:00
Jim Grosbach
3f5493c136 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

llvm-svn: 146937
 2011-12-20 00:59:38 +00:00
Dan Gohman
7940e4e81d Add basic generic CodeGen support for half. 
llvm-svn: 146927
 2011-12-20 00:02:33 +00:00
Jim Grosbach
b1b83d2f58 ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

llvm-svn: 146925
 2011-12-19 23:51:07 +00:00
Jim Grosbach
343f270350 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

llvm-svn: 146921
 2011-12-19 23:06:24 +00:00
Akira Hatanaka
e54da3bfa2 Add patterns for matching immediates whose lower 16-bit is cleared. These 
patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900
 2011-12-19 20:21:18 +00:00
Akira Hatanaka
5ac6df52af Tidy up. Simplify logic. No functional change intended. 
llvm-svn: 146896
 2011-12-19 19:52:25 +00:00
Jim Grosbach
797a88284c ARM NEON two-operand aliases for VPADD. 
rdar://10602276

llvm-svn: 146895
 2011-12-19 19:51:03 +00:00
Akira Hatanaka
804863071f Remove definitions of double word shift plus 32 instructions. Assembler or 
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893
 2011-12-19 19:44:09 +00:00
Jim Grosbach
f9910809c5 ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
llvm-svn: 146892
 2011-12-19 19:43:50 +00:00
Akira Hatanaka
ea1f905123 Remove unused predicate. 
llvm-svn: 146889
 2011-12-19 19:32:20 +00:00
Akira Hatanaka
b7ebcb2ded Remove the restriction on the first operand of the add node in SelectAddr. 
This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)

llvm-svn: 146888
 2011-12-19 19:28:37 +00:00
Jim Grosbach
6e9471925b ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd]. 
llvm-svn: 146887
 2011-12-19 19:02:41 +00:00
Jim Grosbach
520db82971 ARM NEON implied destination aliases for VMAX/VMIN. 
llvm-svn: 146885
 2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
 2011-12-19 18:31:43 +00:00
Jim Grosbach
2a0ced60a5 Tidy up. 
llvm-svn: 146882
 2011-12-19 18:11:17 +00:00
Jakob Stoklund Olesen
7b1b08eb77 Remove a register class that can just as well be synthesized. 
Add the new TableGen register class synthesizer feature to the release
notes.

llvm-svn: 146875
 2011-12-19 16:53:40 +00:00
Jakob Stoklund Olesen
0aa2f7755a Emit a getMatchingSuperRegClass() implementation for every target. 
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

llvm-svn: 146873
 2011-12-19 16:53:34 +00:00
Benjamin Kramer
942f1bd653 Another variadics tweak. 
llvm-svn: 146852
 2011-12-18 20:51:31 +00:00
Benjamin Kramer
e16533eded Use the fancy new VariadicFunction template instead of a plain variadic function. 
Some compilers were complaining about passing StringRef to it.

llvm-svn: 146850
 2011-12-18 19:59:20 +00:00
Benjamin Kramer
dd2a4b1e4f Hexagon: Remove unused variables. 
llvm-svn: 146846
 2011-12-18 12:00:09 +00:00
Craig Topper
9696094d07 Remove an unused X86ISD node type. 
llvm-svn: 146833
 2011-12-17 19:16:44 +00:00
Benjamin Kramer
65c1236c63 X86: Factor the bswap asm matching to be slightly less horrible to read. 
llvm-svn: 146831
 2011-12-17 14:36:05 +00:00
Evan Cheng
23574ec02a Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. 
llvm-svn: 146805
 2011-12-17 01:25:34 +00:00
Rafael Espindola
549d0683b1 Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

llvm-svn: 146801
 2011-12-17 01:14:52 +00:00
Lang Hames
e32ef23ba8 Make sure that the lower bits on the VSELECT condition are properly set. 
llvm-svn: 146800
 2011-12-17 01:08:46 +00:00
Jakob Stoklund Olesen
7d7ba18ad7 Preserve more memory operands in ARMExpandPseudo. 
I don't think this affects anything but verbose assembly.

llvm-svn: 146787
 2011-12-17 00:07:02 +00:00
Jakob Stoklund Olesen
445cdbb987 Fix off-by-one error in bucket sort. 
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

llvm-svn: 146767
 2011-12-16 23:00:05 +00:00
Jakob Stoklund Olesen
d0c1eb9dd2 Don't adjust for alignment padding in OffsetIsInRange. 
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.

When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.

llvm-svn: 146751
 2011-12-16 19:10:00 +00:00
Benjamin Kramer
04d6a4c456 Hexagon: Fix a nasty order-of-initialization bug. 
Reenable the tests.

llvm-svn: 146750
 2011-12-16 19:08:59 +00:00
Jakob Stoklund Olesen
3d0382e29d Note ARM constant island alignment in the release notes. 
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

llvm-svn: 146739
 2011-12-16 16:07:41 +00:00
Craig Topper
88e2bfef0a Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
llvm-svn: 146726
 2011-12-16 08:06:31 +00:00
NAKAMURA Takumi
1aaed909ae Target/Hexagon: Fix CMake build. 
llvm-svn: 146724
 2011-12-16 06:21:02 +00:00
Jim Grosbach
42bf8d8526 ARM NEON aliases for vmovq.f* 
llvm-svn: 146714
 2011-12-16 00:12:22 +00:00
Jim Grosbach
5f14a4c5d4 Thumb2 ADR assembly parsing w/o the .w suffix. 
llvm-svn: 146710
 2011-12-15 23:52:17 +00:00
Eli Friedman
f626b19bda Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
llvm-svn: 146709
 2011-12-15 23:46:18 +00:00
Nick Lewycky
88e64bacfa Move parts of lib/Target that use CodeGen into lib/CodeGen. 
llvm-svn: 146702
 2011-12-15 22:58:58 +00:00
Eli Friedman
7e3cbd0db2 Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) 
llvm-svn: 146700
 2011-12-15 22:56:53 +00:00
Jim Grosbach
30f4b285a6 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Tony Linthicum
31c6f9b096 Add MCTargetDesc library to Hexagon target 
llvm-svn: 146692
 2011-12-15 22:29:08 +00:00
Jim Grosbach
b79d2a8f50 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Jakob Stoklund Olesen
cd03c93e33 Enable proper constant island alignment by default. 
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690
 2011-12-15 22:14:45 +00:00
Chad Rosier
62ebee9859 Add missing zmovl AVX patterns which were causing crashes. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689
 2011-12-15 22:11:31 +00:00
Jim Grosbach
3ee3c6dc3e Silence warning. 
llvm-svn: 146686
 2011-12-15 21:54:55 +00:00
Jim Grosbach
8ed1253ef3 ARM NEON two-register double spaced register list parsing support. 
llvm-svn: 146685
 2011-12-15 21:44:33 +00:00
Chad Rosier
e74b3b1469 Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684
 2011-12-15 21:34:44 +00:00
Lang Hames
d86b47a279 Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>. 
llvm-svn: 146671
 2011-12-15 18:57:27 +00:00
Hal Finkel
f480143f08 Ensure that the nop that should follow a bl call in PPC64 ELF actually does 
llvm-svn: 146664
 2011-12-15 17:54:01 +00:00
Richard Osborne
5f2d0e64e0 Pass optLevel to XCoreDAGToDAGISel. 
Patch by Kyriakos Georgiou.

llvm-svn: 146656
 2011-12-15 15:18:35 +00:00
Chad Rosier
dcfc5e1dd0 Use SmallVector/assign(), rather than std::vector/push_back(). 
llvm-svn: 146627
 2011-12-15 01:16:09 +00:00
Chad Rosier
b93733686c Add support for lowering fneg when AVX is enabled. 
rdar://10566486

llvm-svn: 146625
 2011-12-15 01:02:25 +00:00
Bill Wendling
e9bd145105 The saved registers weren't being processed in the correct order. This lead to 
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.

llvm-svn: 146612
 2011-12-14 23:53:24 +00:00
Jakob Stoklund Olesen
215059cb96 Consider CPE alignment in CreateNewWater(). 
An aligned constant pool entry may require extra alignment padding where
the new water is created.  Take that into account when computing offset.

Also consider the alignment of other constant pool entries when
splitting a basic block.  Alignment padding may make it necessary to
move the split point higher.

llvm-svn: 146609
 2011-12-14 23:48:54 +00:00
Jim Grosbach
b09a003fa6 ARM NEON better assembly operand range checking for lane indices of VLD/VST. 
llvm-svn: 146608
 2011-12-14 23:35:06 +00:00
Jim Grosbach
75db252aee ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
llvm-svn: 146605
 2011-12-14 23:25:46 +00:00
Jim Grosbach
83520a5b70 ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594
 2011-12-14 21:49:24 +00:00
Jim Grosbach
4c0d6081a1 Nuke old code. Missed in last commit. 
llvm-svn: 146590
 2011-12-14 21:41:32 +00:00
Jim Grosbach
2dac770227 ARM NEON refactor VST2 w/ writeback instructions. 
In addition to improving the representation, this adds support for assembly
parsing of these instructions.

llvm-svn: 146588
 2011-12-14 21:32:11 +00:00
Jim Grosbach
7fe9f4b949 ARM NEON improve factoring a bit. No functional change. 
llvm-svn: 146585
 2011-12-14 20:59:15 +00:00