RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 14:33:02 +02:00
Code Issues Projects Releases Wiki Activity
46,668 Commits 4 Branches 5 Tags 704 MiB
d4f9668eb7
Commit Graph

10018 Commits

Author SHA1 Message Date
Anton Korobeynikov
9dc98b6a85 Separate MIPS asmprinter 
llvm-svn: 68383
 2009-04-03 10:41:41 +00:00
Anton Korobeynikov
ae60cc4eba Fix target library name 
llvm-svn: 68382
 2009-04-03 10:41:17 +00:00
Anton Korobeynikov
dbc41d2422 Fix comment 
llvm-svn: 68381
 2009-04-03 10:41:00 +00:00
Anton Korobeynikov
b2c736f296 Move IA64 asmprinter to separate library 
llvm-svn: 68380
 2009-04-03 10:38:51 +00:00
Mon P Wang
f829fb5cab Added a x86 dag combine to increase the chances to use a 
movq for v2i64 on x86-32.

llvm-svn: 68368
 2009-04-03 02:43:30 +00:00
Sanjiv Gupta
7ec088a3de Fixed build warnings. 
llvm-svn: 68333
 2009-04-02 18:33:12 +00:00
Sanjiv Gupta
01fb90085c To convert the StopPoint insn into an assembler directive by ISel, we need to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize. 
llvm-svn: 68329
 2009-04-02 18:03:10 +00:00
Sanjiv Gupta
1555a0a503 Params are not being generated as static globals now. The caller passes them onto the callee's stack directly and the callee loads the argvals from its own stack. Clang generated frameindexes validatd by recalculating the stack as if all frameindexes represent 1-byte slots. 
llvm-svn: 68327
 2009-04-02 17:42:00 +00:00
Chris Lattner
f1719bf7b5 silence warning in release-asserts build. 
llvm-svn: 68253
 2009-04-01 22:14:45 +00:00
Dan Gohman
770f4158e5 Use CHAR_BIT instead of hard-coding 8 in several places where it 
is appropriate. This helps visually differentiate host-oriented
calculations from target-oriented calculations.

llvm-svn: 68227
 2009-04-01 18:45:54 +00:00
Dan Gohman
818a08f22e Use LLVM type names instead of C type names in comments, to be 
less ambiguous and less C-specific.

llvm-svn: 68219
 2009-04-01 18:10:16 +00:00
Bob Wilson
5b42ebe6a9 Fix PR3862: Recognize some ARM-specific constraints for immediates in inline 
assembly.

llvm-svn: 68218
 2009-04-01 17:58:54 +00:00
Evan Cheng
44fdb5d570 i128 shift libcalls are not available on x86. 
llvm-svn: 68133
 2009-03-31 19:38:51 +00:00
Dan Gohman
86e4d0130c Reapply 68073, with fixes. EH Landing-pad basic blocks are not 
entered via fall-through. Don't miss fallthroughs from blocks
terminated by conditional branches. Also, move
isOnlyReachableByFallthrough out of line.

llvm-svn: 68129
 2009-03-31 18:39:13 +00:00
Rafael Espindola
3d866ac20c remove unused arguments. 
llvm-svn: 68109
 2009-03-31 16:16:57 +00:00
Bill Wendling
28fad6fcc1 Really temporarily revert r68073. 
llvm-svn: 68100
 2009-03-31 08:42:40 +00:00
Bill Wendling
1c40c8c242 Oy! When reverting r68073, I added in experimental code. Sorry... 
llvm-svn: 68099
 2009-03-31 08:41:31 +00:00
Bill Wendling
4706abded2 Revert r68073. It's causing a failure in the Apple-style builds. 
llvm-svn: 68092
 2009-03-31 08:26:26 +00:00
Evan Cheng
5c02e62620 X86 address mode isel tweak. If the base of the address is also used by a CopyToReg (i.e. it's likely live-out), do not fold the sub-expressions into the addressing mode to avoid computing the address twice. The CopyToReg use will be isel'ed to a LEA, re-use it for address instead. 
This is not yet enabled.

llvm-svn: 68082
 2009-03-31 01:13:53 +00:00
Dan Gohman
29694088d3 Except in asm-verbose mode, avoid printing labels for blocks that are 
only reachable via fall-through edges. This dramatically reduces the
number of labels printed, and thus also the number of labels the
assembler must parse and remember.

llvm-svn: 68073
 2009-03-30 22:55:17 +00:00
Evan Cheng
3e30bcbd69 When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. 
llvm-svn: 68066
 2009-03-30 21:36:47 +00:00
Bob Wilson
d59a64d436 Fix comment to match function name. 
llvm-svn: 68050
 2009-03-30 18:49:37 +00:00
Anton Korobeynikov
880f98920c Fix thinko: put stuff with both global and local relocations into data.rel{.ro}, not .local 
llvm-svn: 68036
 2009-03-30 17:37:43 +00:00
Anton Korobeynikov
0404baca28 Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness. 
llvm-svn: 68032
 2009-03-30 15:27:43 +00:00
Anton Korobeynikov
2ea565a37b Add data.rel stuff 
llvm-svn: 68031
 2009-03-30 15:27:03 +00:00
Anton Korobeynikov
424bf7a0b5 IA64 is as weird as Alpha wrt r/o relocs :) 
llvm-svn: 68007
 2009-03-29 17:14:35 +00:00
Anton Korobeynikov
55097e65d6 Alpha always requires global relocations to be r/w regardless of PIC. 
llvm-svn: 68006
 2009-03-29 17:14:14 +00:00
Anton Korobeynikov
ec131d94ff Honour relocation behaviour stuff for ro objects 
llvm-svn: 68005
 2009-03-29 17:13:49 +00:00
Chris Lattner
9b435e06e4 add a note 
llvm-svn: 67953
 2009-03-28 19:26:55 +00:00
Rafael Espindola
34f59009d1 Use array_lengthof 
llvm-svn: 67950
 2009-03-28 19:02:18 +00:00
Rafael Espindola
37522e768a Have only one definition of X86AddrNumOperands. 
llvm-svn: 67949
 2009-03-28 18:55:31 +00:00
Rafael Espindola
884992a7e9 Make code a bit less brittle by no hardcoding the number 
of operands in an address in so many places.

llvm-svn: 67945
 2009-03-28 17:03:24 +00:00
Evan Cheng
a15fdaa292 Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g. 
x * 40
=>
shlq    $3, %rdi
leaq    (%rdi,%rdi,4), %rax

This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq    (%rdi,%rdi,2), %rax
leaq    (%rsi,%rax,8), %rax

llvm-svn: 67917
 2009-03-28 05:57:29 +00:00
Jim Grosbach
93b0fc3ba8 remove trailing whitespace 
llvm-svn: 67874
 2009-03-27 23:06:27 +00:00
Rafael Espindola
83ee99d7b0 Avoid hardcoding that X86 addresses have 4 operands. 
llvm-svn: 67848
 2009-03-27 15:57:50 +00:00
Rafael Espindola
7c113e5354 Use less hard coded constants to make the code less brittle. 
llvm-svn: 67846
 2009-03-27 15:45:05 +00:00
Rafael Espindola
38604d9598 I am trying to add a segment to the X86 addresses matching to 
improve TLS support (see http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075220.html), but that code is VERY brittle.

This patch just makes it a bit more resistant.

llvm-svn: 67843
 2009-03-27 15:26:30 +00:00
Evan Cheng
ab6e38c88d -no-implicit-float means explicit fp operations are legal. 
llvm-svn: 67784
 2009-03-26 23:06:32 +00:00
Evan Cheng
1343fa32dc tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode. 
llvm-svn: 67765
 2009-03-26 19:09:01 +00:00
Bill Wendling
f4247ff478 Pull transform from target-dependent code into target-independent code. 
llvm-svn: 67742
 2009-03-26 06:14:09 +00:00
Chris Lattner
cefed33f04 fix warning in -asserts mode. 
llvm-svn: 67739
 2009-03-26 05:29:34 +00:00
Chris Lattner
fd5356e4a9 fix some warnings in release-asserts mode. 
llvm-svn: 67738
 2009-03-26 05:28:26 +00:00
Chris Lattner
4f992250bf fix an apparently real bug exposed by a warning in -asserts mode. 
llvm-svn: 67737
 2009-03-26 05:28:14 +00:00
Chris Lattner
fc26089eb4 fix warning in -asserts build. 
llvm-svn: 67736
 2009-03-26 05:25:59 +00:00
Bill Wendling
f79eccc675 Match this pattern so that we can generate simpler code: 
%a = ...
  %b = and i32 %a, 2
  %c = srl i32 %b, 1
  %d = br i32 %c, 

into

  %a = ...
  %b = and %a, 2
  %c = X86ISD::CMP %b, 0
  %d = X86ISD::BRCOND %c ...

This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.

llvm-svn: 67728
 2009-03-26 01:47:50 +00:00
Bill Wendling
40ac545f38 Doxygen-ify comments. 
llvm-svn: 67727
 2009-03-26 01:46:56 +00:00
Gabor Greif
9ac00d10ea do not rely on callee being operand 0 
llvm-svn: 67681
 2009-03-25 06:32:59 +00:00
Evan Cheng
3a7489a4cc CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. 
llvm-svn: 67668
 2009-03-25 01:47:28 +00:00
Evan Cheng
6ff8cea903 Don't print global names twice with -asm-verbose. 
llvm-svn: 67667
 2009-03-25 01:08:42 +00:00
Dan Gohman
7a9e8cbf79 I was convinced that it's ok to allow a second i8 return value 
to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.

llvm-svn: 67588
 2009-03-24 01:04:34 +00:00
Evan Cheng
b3196f1298 Do not emit comments unless -asm-verbose. 
llvm-svn: 67580
 2009-03-24 00:17:40 +00:00
Dale Johannesen
34123aba43 Fix internal representation of fp80 to be the 
same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.

llvm-svn: 67562
 2009-03-23 21:16:53 +00:00
Dan Gohman
18daca0895 Now that errs() is properly non-buffered, there's no need to 
explicitly flush it.

llvm-svn: 67526
 2009-03-23 15:57:19 +00:00
Dan Gohman
e9cf3083d2 Correct some comments. Operand numbers start at 0. 
llvm-svn: 67518
 2009-03-23 15:40:10 +00:00
Evan Cheng
2ec94dd447 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. 
llvm-svn: 67512
 2009-03-23 08:01:15 +00:00
Dan Gohman
745c0acc79 Fix a grammaro in a comment that Bill noticed. 
llvm-svn: 67507
 2009-03-23 05:02:44 +00:00
Dan Gohman
16b4a33039 Add comments explaining why there's only one register for 
i8 return values.

llvm-svn: 67502
 2009-03-23 04:28:24 +00:00
Bruno Cardoso Lopes
fb1cd21342 Removed AFGR32 register class 
Handle odd registers allocation in FGR32.

llvm-svn: 67422
 2009-03-21 00:05:07 +00:00
Bob Wilson
8aaf1c6085 Fix a few more indentation problems and an 80-column violation. 
llvm-svn: 67416
 2009-03-20 23:16:43 +00:00
Bob Wilson
49a4ec2e00 No functional changes. Fix indentation and whitespace only. 
llvm-svn: 67412
 2009-03-20 22:42:55 +00:00
Sanjiv Gupta
d5c51dc50c Fixed comment for libcalls. 
llvm-svn: 67373
 2009-03-20 14:10:20 +00:00
Sanjiv Gupta
19dc27b7cf Reformatting. Inserted code comments. Cleaned interfaces. 
Removed unncessary code. No functionality change.

llvm-svn: 67371
 2009-03-20 13:42:20 +00:00
Mon P Wang
6ac3a9ac9d Added option to enable generating less precise mad (multiply addition) 
for those architectures that support the instruction.

llvm-svn: 67363
 2009-03-20 05:06:58 +00:00
Nick Lewycky
a0dcd7e173 Remove strange extra semicolons. 
llvm-svn: 67287
 2009-03-19 05:51:39 +00:00
Nate Begeman
0eed59a7df Add support to tablegen for naming the nodes themselves, not just the operands, 
in selectiondag patterns.  This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.

llvm-svn: 67286
 2009-03-19 05:21:56 +00:00
Bruno Cardoso Lopes
3402d4260c Added support for Mips O32 Calling Convention 
llvm-svn: 67280
 2009-03-19 02:12:28 +00:00
Chris Lattner
205380a4e4 Disable the "call to immediate" optimization on x86-64. It is 
not safe in general because the immediate could be an arbitrary
value that does not fit in a 32-bit pcrel displacement.  
Conservatively fall back to loading the value into a register
and calling through it.

We still do the optzn on X86-32.

llvm-svn: 67142
 2009-03-18 00:43:52 +00:00
Scott Michel
a023598ad3 CellSPU: 
Revert inadvertent mis-fix of fneg.

llvm-svn: 67084
 2009-03-17 16:45:16 +00:00
Dan Gohman
f6c57d0fe7 Recognize bswapl as bswap too. 
llvm-svn: 67072
 2009-03-17 02:45:40 +00:00
Dan Gohman
4efda2b52b Recognize "bswapq" as an alternate spelling for the bswap instruction. 
llvm-svn: 67071
 2009-03-17 02:17:27 +00:00
Scott Michel
2c4ac99ef8 CellSPU: 
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
  to the constant pool when they correspond to SPU's shufb instruction's
  special mask values. This avoids the overhead of performing a shuffle on a
  zero-filled vector just to get the special constant when the memory load
  suffices.

llvm-svn: 67067
 2009-03-17 01:15:45 +00:00
Scott Michel
2e2bccf754 CellSPU: 
Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the
llvm-gcc bootstrap a bit further along.

llvm-svn: 67048
 2009-03-16 18:47:25 +00:00
Bruno Cardoso Lopes
2aada0dc02 This causes incorrect stack frame allocation when the last object is an array allocated on the stack which would lead 
the compiled program to run over its stack. Thanks to Gil Dogon

llvm-svn: 67034
 2009-03-15 23:28:07 +00:00
Dan Gohman
fd6debff99 Use %rip-relative addressing on x86-64 whenever practical, as 
it has a smaller encoding than absolute addressing.

llvm-svn: 67002
 2009-03-14 02:33:41 +00:00
Dan Gohman
e7495ef7aa Don't forego folding of loads into 64-bit adds when the other 
operand is a signed 32-bit immediate. Unlike with the 8-bit
signed immediate case, it isn't actually smaller to fold a
32-bit signed immediate instead of a load. In fact, it's
larger in the case of 32-bit unsigned immediates, because
they can be materialized with movl instead of movq.

llvm-svn: 67001
 2009-03-14 02:07:16 +00:00
Dan Gohman
fa0a3504ba Improve FastISel's handling of truncates to i1, and implement 
ptrtoint and inttoptr in X86FastISel. These casts aren't always
handled in the generic FastISel code because X86 sometimes needs
custom code to do truncation and zero-extension.

llvm-svn: 66988
 2009-03-13 23:53:06 +00:00
Dan Gohman
790659c0d6 Fix FastISel's assumption that i1 values are always zero-extended 
by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.

llvm-svn: 66941
 2009-03-13 20:42:20 +00:00
Rafael Espindola
aadb9af093 add 8 and 16 bit TLS moves. 
add a fixme note on how to remove code duplication.

llvm-svn: 66932
 2009-03-13 19:39:55 +00:00
Rafael Espindola
ff17d02271 Improve sext and zext of TLS variables. 
llvm-svn: 66922
 2009-03-13 18:37:06 +00:00
Chris Lattner
63569fa327 generalize this code so that fast isel handles integer truncates to i1, which 
codegen to the same thing as integer truncates to i8 (the top bits are 
just undefined).  This implements rdar://6667338

llvm-svn: 66902
 2009-03-13 16:36:42 +00:00
Bill Wendling
2fe64f48aa These instructions have special lowering that may lower them to SSE 
instructions. Prevent that if we don't want implicit uses of SSE.

llvm-svn: 66877
 2009-03-13 08:41:47 +00:00
Evan Cheng
f9951d1557 Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.


Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.

llvm-svn: 66875
 2009-03-13 07:51:59 +00:00
Chris Lattner
cbbdd230dd generalize the previous code to use the full generality of LEA 
for i32/i64 expressions (we could also do i16 on cpus where
i16 lea is fast, but I didn't add this).  On the example, we now
generate:

_test:
	movl	4(%esp), %eax
	cmpl	$42, (%eax)
	setl	%al
	movzbl	%al, %eax
	leal	4(%eax,%eax,8), %eax
	ret

instead of:

_test:
	movl	4(%esp), %eax
	cmpl	$41, (%eax)
	movl	$4, %ecx
	movl	$13, %eax
	cmovg	%ecx, %eax
	ret

llvm-svn: 66869
 2009-03-13 05:53:31 +00:00
Chris Lattner
878d951f8f optimize the case of cond ? 42 : 41 and friends. This compiles the 
example to:

_test:
	movl	4(%esp), %eax
	cmpl	$41, (%eax)
	setg	%al
	movzbl	%al, %eax
	orl	$4294967294, %eax
	ret

instead of:

        movl    4(%esp), %eax
        cmpl    $41, (%eax)
	movl	$4294967294, %ecx
	movl	$4294967295, %eax
	cmova	%ecx, %eax
	ret

which is smaller in code size and faster. rdar://6668608

llvm-svn: 66868
 2009-03-13 05:22:11 +00:00
Dan Gohman
37d843c129 Enhance address-mode folding of ISD::ADD to handle cases where the 
operands can't both be fully folded at the same time. For example,
in the included testcase, a global variable is being added with
an add of two values. The global variable wants RIP-relative
addressing, so it can't share the address with another base
register, but it's still possible to fold the initial add.

llvm-svn: 66865
 2009-03-13 02:25:09 +00:00
Evan Cheng
d112c41d95 Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative. 
llvm-svn: 66803
 2009-03-12 18:15:39 +00:00
Chris Lattner
26a971c4ec Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))" 
related transformations out of target-specific dag combine into the
ARM backend.  These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).

Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0  -> (zext(cond) << 3).  This happens frequently
with the recently added cp constant select optimization, but is a
very general xform.  For example, we now compile the second example
in const-select.ll to:

_test:
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        seta    %al
        movzbl  %al, %eax
        movl    4(%esp), %ecx
        movsbl  (%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl    4(%esp), %eax
        leal    4(%eax), %ecx
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        cmovbe  %eax, %ecx
        movsbl  (%ecx), %eax
        ret

This passes multisource and dejagnu.

llvm-svn: 66779
 2009-03-12 06:52:53 +00:00
Chris Lattner
b904fac1b8 improve comment. 
llvm-svn: 66778
 2009-03-12 06:46:02 +00:00
Evan Cheng
46e903d2f6 On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead. 
llvm-svn: 66776
 2009-03-12 05:59:15 +00:00
Sanjiv Gupta
09e6929cc5 Forgot to check-in this as part of 7761. 
llvm-svn: 66763
 2009-03-12 03:20:07 +00:00
Sanjiv Gupta
85826620f1 Banksel optimization is now based on the section names of symbols, since the symbols in one section will always be put into one bank. 
llvm-svn: 66761
 2009-03-12 02:10:45 +00:00
Dan Gohman
d30e108f0e Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the 
assembly text output uses an indirect call ("call *") instead of a direct call.

llvm-svn: 66735
 2009-03-11 23:01:47 +00:00
Rafael Espindola
a8fe373200 optimize i8 and i16 tls values. 
llvm-svn: 66725
 2009-03-11 22:40:04 +00:00
Bill Wendling
fca05e3a5c Add a -no-implicit-float flag. This acts like -soft-float, but may generate 
floating point instructions that are explicitly specified by the user.

llvm-svn: 66719
 2009-03-11 22:30:01 +00:00
Duncan Sands
b27c523449 It makes no sense to have a ODR version of common 
linkage, so remove it.

llvm-svn: 66690
 2009-03-11 20:14:15 +00:00
Mon P Wang
287e422039 For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits. 
llvm-svn: 66684
 2009-03-11 18:47:57 +00:00
Chris Lattner
5bf3e7dc27 fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.ll 
llvm-svn: 66660
 2009-03-11 16:14:25 +00:00
Duncan Sands
aadb34c357 Remove the one-definition-rule version of extern_weak 
linkage: this linkage type only applies to declarations,
but ODR is only relevant to globals with definitions.

llvm-svn: 66650
 2009-03-11 08:08:06 +00:00
Mon P Wang
2867737ad2 Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw. 
llvm-svn: 66645
 2009-03-11 06:35:11 +00:00
Chris Lattner
eb9327f335 formatting change, reduce indentation. No functionality change. 
llvm-svn: 66642
 2009-03-11 05:48:52 +00:00
Sanjiv Gupta
766590cde2 Mark the Defs and Uses of STATUS register correctly, plus some reformatting. 
llvm-svn: 66540
 2009-03-10 10:35:34 +00:00
Dan Gohman
e15d8f03c3 Add more information to the EFLAGS note. 
llvm-svn: 66515
 2009-03-10 00:26:23 +00:00
Dan Gohman
995c3dd344 Add a note about EFLAGS optimization. 
llvm-svn: 66508
 2009-03-09 23:47:02 +00:00
Evan Cheng
8d01b15f19 ARM target now also recognize triplets like thumbv6-apple-darwin and set thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes. 
llvm-svn: 66435
 2009-03-09 20:25:39 +00:00
Evan Cheng
3c9a084a1b ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types. 
llvm-svn: 66429
 2009-03-09 19:15:00 +00:00
Chris Lattner
b89dbcd448 do not export all the X86FastISel symbols, ever. 
llvm-svn: 66382
 2009-03-08 18:44:31 +00:00
Evan Cheng
67ccd79e39 Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly. 
llvm-svn: 66365
 2009-03-08 04:02:49 +00:00
Chris Lattner
3342ba06d4 add a note. 
llvm-svn: 66360
 2009-03-08 03:04:26 +00:00
Chris Lattner
8ace06fdda add a note. 
llvm-svn: 66359
 2009-03-08 01:54:43 +00:00
Duncan Sands
5ab54d488f Introduce new linkage types linkonce_odr, weak_odr, common_odr 
and extern_weak_odr.  These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global.  In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time.   This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function.  If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body.  The
code generators on the other hand map weak and weak_odr linkage
to the same thing.

llvm-svn: 66339
 2009-03-07 15:45:40 +00:00
Dan Gohman
b9c32f1aca Arithmetic instructions don't set EFLAGS bits OF and CF bits 
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.

llvm-svn: 66318
 2009-03-07 01:58:32 +00:00
Dan Gohman
f9599e6c5f Don't use plain INC32 and DEC32 on x86-64; it needs 
INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.

llvm-svn: 66207
 2009-03-05 21:32:23 +00:00
Dan Gohman
1e9db7c1a1 When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand. 
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.

llvm-svn: 66206
 2009-03-05 21:29:28 +00:00
Dan Gohman
f6f684b206 Fix the "test" optimization to recognize "dec" as an add of 
negative one, as subtracts of immediates are canonicalized
to adds.

llvm-svn: 66180
 2009-03-05 19:32:48 +00:00
Dan Gohman
31fb085c2e Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. 
llvm-svn: 66058
 2009-03-04 19:44:21 +00:00
Dan Gohman
f41e54c5af Correct this comment. 
llvm-svn: 66057
 2009-03-04 19:24:25 +00:00
Dan Gohman
04453ca36c When using MachineInstr operand indices on SDNodes, the number 
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.

llvm-svn: 66056
 2009-03-04 19:23:38 +00:00
Evan Cheng
7d9019d0f3 Fix PR3666: isel calls to constant addresses. 
llvm-svn: 66024
 2009-03-04 06:48:53 +00:00
Dan Gohman
6831e2c2a6 Revert r66004 for now; it's causing a variety of test failures. 
llvm-svn: 66008
 2009-03-04 03:54:19 +00:00
Dan Gohman
c6c669cc1e Teach the x86 backend to eliminate "test" instructions by using the EFLAGS 
result from add, sub, inc, and dec instructions in simple cases.

llvm-svn: 66004
 2009-03-04 02:33:24 +00:00
Evan Cheng
db402a7a49 Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. 
llvm-svn: 65996
 2009-03-04 01:41:49 +00:00
Dan Gohman
3c6c7754b2 Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC 
instructions. These aren't used yet.

llvm-svn: 65965
 2009-03-03 19:53:46 +00:00
Bob Wilson
17cf012d93 Use early exit to reduce indentation. No functional change. 
llvm-svn: 65962
 2009-03-03 19:26:27 +00:00
Dan Gohman
51d4e8db6a Fix a bunch of Doxygen syntax issues. Escape special characters, 
and put @file directives on their own comment line.

llvm-svn: 65920
 2009-03-03 02:55:14 +00:00
Bob Wilson
5b276b6bc9 Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle 
arbitrary vector sizes.  Add an optional MinSplatBits parameter to specify
a minimum for the splat element size.  Update the PPC target to use the
revised interface.

llvm-svn: 65899
 2009-03-02 23:24:16 +00:00
Bob Wilson
7482f84ae6 Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new 
method in a BuildVectorSDNode "pseudo-class".

llvm-svn: 65747
 2009-03-01 01:13:55 +00:00
Mon P Wang
0258a27c5a Added another darwin subtarget 
llvm-svn: 65662
 2009-02-28 00:25:30 +00:00
Rafael Espindola
880e63bf01 Refactor TLS code and add some tests. The tests and expected results are: 
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.

llvm-svn: 65632
 2009-02-27 13:37:18 +00:00
Dale Johannesen
8f76578347 Alignment values for i64 and f64 on ppc64 were wrong, 
possibly for the reason suggested by the comment.
No wonder it didn't work very well.  This unblocks
bootstrap with assertions on ppc.

llvm-svn: 65601
 2009-02-27 00:56:35 +00:00
Evan Cheng
4014a9a5b8 ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. 
llvm-svn: 65499
 2009-02-26 03:12:02 +00:00
Evan Cheng
ec34226c2b Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. 
llvm-svn: 65482
 2009-02-25 22:49:59 +00:00
Nick Lewycky
8672fb675c Add a totally synthetic situation I came up with while looking at a bug in 
related code.

llvm-svn: 65437
 2009-02-25 06:52:48 +00:00
Scott Michel
29d7559c09 Remove all "cached" data from BuildVectorSDNode, preferring to retrieve 
results via reference parameters.

This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.

llvm-svn: 65426
 2009-02-25 03:12:50 +00:00
Bill Wendling
9d4eb136da Overhaul my earlier submission due to feedback. It's a large patch, but most of 
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.

llvm-svn: 65379
 2009-02-24 08:30:20 +00:00
Dan Gohman
3766eeea36 Fast-isel can't do TLS yet, so it should fall back to SDISel 
if it sees TLS addresses.

llvm-svn: 65341
 2009-02-23 22:03:08 +00:00
Evan Cheng
dd139e795c Only v1i16 (i.e. _m64) is returned via RAX / RDX. 
llvm-svn: 65313
 2009-02-23 09:03:22 +00:00
Nate Begeman
e0093d2501 Generate better code for v8i16 shuffles on SSE2 
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
  cleanups.
New tests that test the above.

Examples:

New:
_shuf2:
	pextrw	$7, %xmm0, %eax
	punpcklqdq	%xmm1, %xmm0
	pshuflw	$128, %xmm0, %xmm0
	pinsrw	$2, %eax, %xmm0

Old:
_shuf2:
	pextrw	$2, %xmm0, %eax
	pextrw	$7, %xmm0, %ecx
	pinsrw	$2, %ecx, %xmm0
	pinsrw	$3, %eax, %xmm0
	movd	%xmm1, %eax
	pinsrw	$4, %eax, %xmm0
	ret

=========

New:
_shuf4:
	punpcklqdq	%xmm1, %xmm0
	pshufb	LCPI1_0, %xmm0

Old:
_shuf4:
	pextrw	$3, %xmm0, %eax
	movsd	%xmm1, %xmm0
	pextrw	$3, %xmm1, %ecx
	pinsrw	$4, %ecx, %xmm0
	pinsrw	$5, %eax, %xmm0

========

New:
_shuf1:
	pushl	%ebx
	pushl	%edi
	pushl	%esi
	pextrw	$1, %xmm0, %eax
	rolw	$8, %ax
	movd	%xmm0, %ecx
	rolw	$8, %cx
	pextrw	$5, %xmm0, %edx
	pextrw	$4, %xmm0, %esi
	pextrw	$3, %xmm0, %edi
	pextrw	$2, %xmm0, %ebx
	movaps	%xmm0, %xmm1
	pinsrw	$0, %ecx, %xmm1
	pinsrw	$1, %eax, %xmm1
	rolw	$8, %bx
	pinsrw	$2, %ebx, %xmm1
	rolw	$8, %di
	pinsrw	$3, %edi, %xmm1
	rolw	$8, %si
	pinsrw	$4, %esi, %xmm1
	rolw	$8, %dx
	pinsrw	$5, %edx, %xmm1
	pextrw	$7, %xmm0, %eax
	rolw	$8, %ax
	movaps	%xmm1, %xmm0
	pinsrw	$7, %eax, %xmm0
	popl	%esi
	popl	%edi
	popl	%ebx
	ret

Old:
_shuf1:
	subl	$252, %esp
	movaps	%xmm0, (%esp)
	movaps	%xmm0, 16(%esp)
	movaps	%xmm0, 32(%esp)
	movaps	%xmm0, 48(%esp)
	movaps	%xmm0, 64(%esp)
	movaps	%xmm0, 80(%esp)
	movaps	%xmm0, 96(%esp)
	movaps	%xmm0, 224(%esp)
	movaps	%xmm0, 208(%esp)
	movaps	%xmm0, 192(%esp)
	movaps	%xmm0, 176(%esp)
	movaps	%xmm0, 160(%esp)
	movaps	%xmm0, 144(%esp)
	movaps	%xmm0, 128(%esp)
	movaps	%xmm0, 112(%esp)
	movzbl	14(%esp), %eax
	movd	%eax, %xmm1
	movzbl	22(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	42(%esp), %eax
	movd	%eax, %xmm1
	movzbl	50(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm1, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	77(%esp), %eax
	movd	%eax, %xmm1
	movzbl	84(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	104(%esp), %eax
	movd	%eax, %xmm1
	punpcklbw	%xmm1, %xmm0
	punpcklbw	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	punpcklbw	%xmm3, %xmm1
	movzbl	127(%esp), %eax
	movd	%eax, %xmm0
	movzbl	135(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	155(%esp), %eax
	movd	%eax, %xmm0
	movzbl	163(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm0, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	188(%esp), %eax
	movd	%eax, %xmm0
	movzbl	197(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	217(%esp), %eax
	movd	%eax, %xmm4
	movzbl	225(%esp), %eax
	movd	%eax, %xmm0
	punpcklbw	%xmm4, %xmm0
	punpcklbw	%xmm2, %xmm0
	punpcklbw	%xmm3, %xmm0
	punpcklbw	%xmm1, %xmm0
	addl	$252, %esp
	ret

llvm-svn: 65311
 2009-02-23 08:49:38 +00:00
Bill Wendling
3151437f5c Propagate debug loc info through prologue/epilogue. 
llvm-svn: 65298
 2009-02-23 00:42:30 +00:00
Scott Michel
3f8637305f Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR 
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.

llvm-svn: 65296
 2009-02-22 23:36:09 +00:00
Evan Cheng
3ea8bd42f3 Add a note. 
llvm-svn: 65275
 2009-02-22 08:13:45 +00:00
Evan Cheng
4385f393f7 Be bug compatible with gcc by returning MMX values in RAX. 
llvm-svn: 65274
 2009-02-22 08:05:12 +00:00
Evan Cheng
9d9688ec15 Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible. 
llvm-svn: 65273
 2009-02-22 08:04:23 +00:00
Anton Korobeynikov
5df82e3e25 Drop bunch of half-working stuff in the ext_weak linkage support. 
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).

The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)

llvm-svn: 65230
 2009-02-21 11:53:32 +00:00
Bill Wendling
bfc216c45a Make sure this doesn't access .end() too. 
llvm-svn: 65213
 2009-02-21 01:11:36 +00:00
Bill Wendling
96430050a5 Make sure we don't dereference the .end() of the container. 
llvm-svn: 65211
 2009-02-21 01:07:26 +00:00
Bill Wendling
66c3ffa2de Propagate more debug loc infos. This also includes some code cleaning. 
llvm-svn: 65207
 2009-02-21 00:43:56 +00:00
Bill Wendling
09289bc433 We need to propagate the debug location information even when dealing with the 
prologue/epilogue.

llvm-svn: 65206
 2009-02-21 00:32:08 +00:00
Evan Cheng
c40c3e28f7 Support return of MMX values in 64-bit mode. 
llvm-svn: 65152
 2009-02-20 20:43:02 +00:00
Torok Edwin
b399b47942 add note about sin 
llvm-svn: 65137
 2009-02-20 18:42:06 +00:00
Bill Wendling
306b992133 Put code that generates debug labels into TableGen so that it can be used by 
everyone.

llvm-svn: 64978
 2009-02-18 23:12:06 +00:00
Dan Gohman
30770ee7b3 Add explicit keywords. 
llvm-svn: 64915
 2009-02-18 16:37:45 +00:00
Nate Begeman
5e78e558ff Add support to the JIT for true non-lazy operation. When a call to a function 
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.

llvm-svn: 64906
 2009-02-18 08:31:02 +00:00
Dan Gohman
9c258bd2ec Factor out the code to add a MachineOperand to a MachineInstrBuilder. 
llvm-svn: 64891
 2009-02-18 05:45:50 +00:00
Evan Cheng
bd63a1f40d GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well. 
llvm-svn: 64877
 2009-02-18 02:19:52 +00:00
Scott Michel
4c5fa6c982 Remove trailing whitespace to reduce later commit patch noise. 
(Note: Eventually, commits like this will be handled via a pre-commit hook that
 does this automagically, as well as expand tabs to spaces and look for 80-col
 violations.)

llvm-svn: 64827
 2009-02-17 22:15:04 +00:00
Chris Lattner
3b67310686 add a horrible note 
llvm-svn: 64719
 2009-02-17 01:16:14 +00:00
Bill Wendling
266c8bc98f --- Merging (from foreign repository) r64714 into '.': 
U    include/llvm/CodeGen/DebugLoc.h
U    lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp

Enable debug location generation at -Os. This goes with the reapplication of the
r63639 patch.

llvm-svn: 64715
 2009-02-17 01:04:54 +00:00
Dan Gohman
f23a24ce3d Delete trailing whitespace. 
llvm-svn: 64694
 2009-02-16 23:14:14 +00:00
Dan Gohman
856736a187 MachineLICM now handles these cases. 
llvm-svn: 64620
 2009-02-15 23:24:52 +00:00
Dan Gohman
684359ea96 The x86-64 red zone is now being used. 
llvm-svn: 64535
 2009-02-14 03:30:05 +00:00
Evan Cheng
9041a71923 Teach x86 target -soft-float. 
llvm-svn: 64496
 2009-02-13 22:36:38 +00:00
Dale Johannesen
329e01b91b Remove non-DebugLoc versions of BuildMI from IA64, Mips. 
llvm-svn: 64438
 2009-02-13 02:34:39 +00:00
Dale Johannesen
560b03bbcd Remove non-DebugLoc versions of BuildMI from X86. 
There were some that might even matter in X86FastISel.

llvm-svn: 64437
 2009-02-13 02:33:27 +00:00
Dale Johannesen
0336a2cfd0 missed file 
llvm-svn: 64436
 2009-02-13 02:32:04 +00:00
Dale Johannesen
bf9e91b0b9 Remove non-DebugLoc versions of buildMI from Sparc. 
llvm-svn: 64435
 2009-02-13 02:31:35 +00:00
Dale Johannesen
a0069695df Remove non-DebugLoc versions of BuildMI from Alpha and Cell. 
llvm-svn: 64433
 2009-02-13 02:30:42 +00:00
Dale Johannesen
9c596981ed Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16. 
llvm-svn: 64432
 2009-02-13 02:29:03 +00:00
Dale Johannesen
428a8fcc3d Remove refs to non-DebugLoc version of BuildMI from PowerPC. 
llvm-svn: 64431
 2009-02-13 02:27:39 +00:00
Dale Johannesen
986cfc3338 and one more file 
llvm-svn: 64430
 2009-02-13 02:26:21 +00:00
Dale Johannesen
a91dca7b45 Remove refs to non-DebugLoc versions of BuildMI from ARM. 
llvm-svn: 64429
 2009-02-13 02:25:56 +00:00
Bill Wendling
40e4b271af Revert this. It was breaking stuff. 
llvm-svn: 64428
 2009-02-13 02:16:35 +00:00
Bill Wendling
83b6edd760 Turn off the old way of handling debug information in the code generator. Use 
the new way, where all of the information is passed on SDNodes and machine
instructions.

llvm-svn: 64427
 2009-02-13 02:01:04 +00:00
Dale Johannesen
df5d8dfbcb Check in missing file. 
llvm-svn: 64410
 2009-02-12 23:24:44 +00:00
Dale Johannesen
5a21722625 Eliminate a couple of non-DebugLoc BuildMI variants. 
Modify callers.

llvm-svn: 64409
 2009-02-12 23:08:38 +00:00
Dale Johannesen
47321cf01f Arrange to print constants that match "n" and "i" constraints 
in inline asm as signed (what gcc does).  Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.

llvm-svn: 64400
 2009-02-12 20:58:09 +00:00
Chris Lattner
c1488eea4b fix PR3538 for ARM. 
llvm-svn: 64384
 2009-02-12 17:38:23 +00:00
Chris Lattner
aeec838015 fix PR3538 for PPC 
llvm-svn: 64383
 2009-02-12 17:37:15 +00:00
Chris Lattner
1174b80823 fix the X86 backend to just drop llvm.declare nodes for VLAs instead of 
leaving them in the DAG and then getting selection errors.  This is a 
fix for PR3538.

llvm-svn: 64382
 2009-02-12 17:33:11 +00:00
Bill Wendling
d31cb3d5aa Move debug loc info along when the spiller creates new instructions. 
llvm-svn: 64342
 2009-02-12 00:02:55 +00:00
Bill Wendling
49baa5465c Propagate DebugLoc info for spiller call-backs. 
llvm-svn: 64329
 2009-02-11 21:51:19 +00:00
Dan Gohman
2decb4495d Don't try to set an EFLAGS operand to dead if no instruction was created. 
This fixes a bug introduced by r61215.

llvm-svn: 64316
 2009-02-11 19:50:24 +00:00
Evan Cheng
cdb35e3f0f Handle llvm.x86.sse2.maskmov.dqu in 64-bit. 
llvm-svn: 64240
 2009-02-10 22:06:28 +00:00
Evan Cheng
a1b9cf3143 80 col violations. 
llvm-svn: 64237
 2009-02-10 21:39:44 +00:00
Sanjiv Gupta
abf1d4e9db Function temporaries can not overlap with retval or args.See the comment in source code to know the reason. Anything having .auto. in its name is local to a function in nature irrespective of the linkage specified. print static local variables in module level IDATA section. 
llvm-svn: 64199
 2009-02-10 04:20:26 +00:00
Evan Cheng
3b84024598 Implement FpSET_ST1_*. 
llvm-svn: 64186
 2009-02-09 23:32:07 +00:00
Dan Gohman
548d7c9145 Use doxygen comment syntax. 
llvm-svn: 64150
 2009-02-09 18:12:09 +00:00
Evan Cheng
9dc1507838 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.

llvm-svn: 64124
 2009-02-09 07:14:22 +00:00
Chris Lattner
a50a554333 add a note. 
llvm-svn: 64093
 2009-02-08 20:44:19 +00:00
Dale Johannesen
b22cb23f6f Use getDebugLoc forwarder instead of getNode()->getDebugLoc. 
No functional change.

llvm-svn: 64026
 2009-02-07 19:59:05 +00:00
Dan Gohman
4105a38248 Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing 
ScheduleDAG's TLI member to use const.

llvm-svn: 64018
 2009-02-07 16:15:20 +00:00
Dale Johannesen
a068079e5f Needs this file too. 
llvm-svn: 63993
 2009-02-07 00:56:46 +00:00
Dale Johannesen
a259483aae Get rid of the last non-DebugLoc versions of getNode! 
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base.  There's no
sensible way to associate debug info with these.  I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. 
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.

llvm-svn: 63992
 2009-02-07 00:55:49 +00:00
Dan Gohman
8437b9efa1 Refactor some repeated logic into a separate function. 
llvm-svn: 63989
 2009-02-07 00:43:41 +00:00
Dan Gohman
8aeae15ebd Make a comment a doxygen comment. 
llvm-svn: 63988
 2009-02-07 00:42:54 +00:00
Dale Johannesen
1580ab6b7f Remove more non-DebugLoc getNode variants. Use 
getCALLSEQ_{END,START} to permit passing no DebugLoc
there.  UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.

llvm-svn: 63978
 2009-02-06 23:05:02 +00:00
Dale Johannesen
c405486235 Remove more non-DebugLoc versions of getNode. 
llvm-svn: 63969
 2009-02-06 21:50:26 +00:00
Bill Wendling
2c7f47d1d4 Record debug location information in the Dwarf writer. 
A simple test program shows that debugging works. :-)

llvm-svn: 63968
 2009-02-06 21:45:08 +00:00
Dan Gohman
a2f300f26d Use .size and .type on ELF systems; this helps tools that map 
addresses to symbols.

llvm-svn: 63962
 2009-02-06 21:15:52 +00:00
Dale Johannesen
7099fa18a4 Eliminate remaining non-DebugLoc version of getTargetNode. 
llvm-svn: 63951
 2009-02-06 19:16:40 +00:00
Sanjiv Gupta
90fd43f44d Print globl directive for variables with external linkage (global variables). 
llvm-svn: 63943
 2009-02-06 18:24:59 +00:00
Evan Cheng
e00df1d39c Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. 
llvm-svn: 63938
 2009-02-06 17:43:24 +00:00
Evan Cheng
381b2df5ff Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. 
llvm-svn: 63936
 2009-02-06 17:17:30 +00:00
Dale Johannesen
cda84103ff get rid of some non-DebugLoc getTargetNode variants. 
llvm-svn: 63909
 2009-02-06 02:08:06 +00:00
Dale Johannesen
e95c76b65e Get rid of one more non-DebugLoc getNode and 
its corresponding getTargetNode.  Lots of
caller changes.

llvm-svn: 63904
 2009-02-06 01:31:28 +00:00
Dale Johannesen
c96091a672 Remove a non-DebugLoc version of getNode. 
llvm-svn: 63889
 2009-02-05 22:07:54 +00:00
Evan Cheng
87def37f67 A few more isAsCheapAsAMove. 
llvm-svn: 63852
 2009-02-05 08:42:55 +00:00
Dale Johannesen
fa28929927 Reapply 63765. Patches for clang and llvm-gcc to follow. 
llvm-svn: 63812
 2009-02-05 01:49:45 +00:00
Dale Johannesen
c901d013fb Get rid of 3 non-DebugLoc getNode variants. 
llvm-svn: 63808
 2009-02-05 01:01:16 +00:00
Dale Johannesen
c2896f9310 Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg. 
llvm-svn: 63800
 2009-02-05 00:20:09 +00:00
Dale Johannesen
d27bc65e74 Remove non-DebugLoc forms of CopyToReg and CopyFromReg. 
Adjust callers.

llvm-svn: 63789
 2009-02-04 23:02:30 +00:00
Dale Johannesen
f6e1822ccd Reverting 63765. This broke the build of both clang 
and llvm-gcc.

llvm-svn: 63786
 2009-02-04 22:47:25 +00:00
Dale Johannesen
15a801f11d Remove non-DebugLoc versions of getLoad and getStore. 
Adjust the many callers of those versions.

llvm-svn: 63767
 2009-02-04 20:06:27 +00:00
Nate Begeman
66f10b55ed New feature: add support for target intrinsics being defined in the 
target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.

llvm-svn: 63765
 2009-02-04 19:47:21 +00:00
Chris Lattner
feb6b56242 Bill implemented this. 
llvm-svn: 63752
 2009-02-04 19:09:07 +00:00
Chris Lattner
eae4653469 add a note, this is why we're faster at SciMark-MonteCarlo with 
SSE disabled.

llvm-svn: 63751
 2009-02-04 19:08:01 +00:00
Dan Gohman
1cd89d625c Minor code cleanups; no functionality change. 
llvm-svn: 63740
 2009-02-04 17:28:58 +00:00
Dale Johannesen
19fc835580 Remove non-DebugLoc forms of the exotic forms 
of Lod and Sto; patch uses.

llvm-svn: 63716
 2009-02-04 02:34:38 +00:00
Dale Johannesen
52d1d8d5a0 Remove some more non-DebugLoc versions of construction 
functions, with callers adjusted to fit.

llvm-svn: 63705
 2009-02-04 01:48:28 +00:00
Dale Johannesen
2c4af04551 Remove a few non-DebugLoc versions of node creation 
functions.

llvm-svn: 63703
 2009-02-04 01:17:06 +00:00
Mon P Wang
430525dc4f Fixes a case where we generate an incorrect mask for pshfhw in the presence 
of undefs and incorrectly determining if we have punpckldq.

llvm-svn: 63702
 2009-02-04 01:16:59 +00:00
Dale Johannesen
fa244d6e2d Patch up omissions in DebugLoc propagation. 
llvm-svn: 63693
 2009-02-04 00:33:20 +00:00
Dale Johannesen
f9b2746030 Need this file too. 
llvm-svn: 63674
 2009-02-03 22:26:34 +00:00
Dale Johannesen
b7f2857776 Add some DL propagation to places that didn't 
have it yet.  More coming.

llvm-svn: 63673
 2009-02-03 22:26:09 +00:00
Dale Johannesen
45009f127b DebugLoc propgation 
llvm-svn: 63664
 2009-02-03 21:48:12 +00:00
Dale Johannesen
358418bb3d DebugLoc propagation. done with file. 
llvm-svn: 63656
 2009-02-03 20:21:25 +00:00
Dale Johannesen
6c8c315519 DebugLoc propagation. 2/3 through file. 
llvm-svn: 63650
 2009-02-03 19:33:06 +00:00
Dan Gohman
7d19e6cd6d Tevert part of the x86 subtarget logic changes: when -march=x86-64 
is given, override the subtarget settings and enable 64-bit support.
This restores the earlier behavior, and fixes regressions on
Non-64-bit-capable x86-32 hosts.

This isn't necessarily the best approach, but the most obvious
alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used
with -march=x86-64 when the host doesn't have 64-bit support. This
makes things little more consistent, but it's less convenient, and
it has the practical drawback of requiring lots of test changes, so
I opted for the above approach for now.

llvm-svn: 63642
 2009-02-03 18:53:21 +00:00
Bill Wendling
5b177df8e9 Create DebugLoc information in FastISel. Several temporary methods were 
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.

llvm-svn: 63584
 2009-02-03 00:55:04 +00:00
Dan Gohman
2170150035 Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has 
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.

Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.

llvm-svn: 63575
 2009-02-03 00:04:43 +00:00
Torok Edwin
2bc41a36ba Only force SSE level if it is not correct. 
Add an assert to check HasX86_64 status.

llvm-svn: 63552
 2009-02-02 21:57:34 +00:00
Torok Edwin
c1017185a5 remove #if 0 code on Bill's request. 
llvm-svn: 63542
 2009-02-02 20:23:02 +00:00
Sanjiv Gupta
c47a19b23e Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces. 
llvm-svn: 63521
 2009-02-02 16:53:06 +00:00
Evan Cheng
16c8f917fb ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. 
llvm-svn: 63509
 2009-02-02 09:15:04 +00:00
Evan Cheng
e8dfbb5884 Add comment. 
llvm-svn: 63506
 2009-02-02 08:19:07 +00:00
Evan Cheng
483bbd1643 Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. 
llvm-svn: 63505
 2009-02-02 08:07:36 +00:00
Torok Edwin
b4c9a6097f Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for 
var-args, and don't allow FP return values

llvm-svn: 63495
 2009-02-01 18:15:56 +00:00
Duncan Sands
cac6cf74f9 Fix PR3453 and probably a bunch of other potential 
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.

llvm-svn: 63494
 2009-02-01 18:06:53 +00:00
Dale Johannesen
39738b1ff8 Make LowerCallTo and LowerArguments take a DebugLoc 
argument.  Adjust all callers and overloaded versions.

llvm-svn: 63444
 2009-01-30 23:10:59 +00:00
Bill Wendling
67737da99b Get rid of the non-DebugLoc-ified getNOT() method. 
llvm-svn: 63442
 2009-01-30 23:03:19 +00:00
Sanjiv Gupta
11d082d56e Fixed the comment. No functionality change. 
llvm-svn: 63387
 2009-01-30 09:01:44 +00:00
Sanjiv Gupta
b4cf873468 Use sublw for comparison with literals instead of subwf. 
llvm-svn: 63382
 2009-01-30 07:55:25 +00:00
Mon P Wang
5db99442e4 When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of 
an illegal type.

llvm-svn: 63380
 2009-01-30 07:07:40 +00:00
Sanjiv Gupta
e442452ade Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces. 
llvm-svn: 63377
 2009-01-30 04:25:10 +00:00
Dan Gohman
9d120d6d8f Make x86's BT instruction matching more thorough, and add some 
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266
 2009-01-29 01:59:02 +00:00
Mon P Wang
8abb07a527 Fixed lowering of v816 shuffles. 
llvm-svn: 63252
 2009-01-28 23:11:14 +00:00
Duncan Sands
aee16d4916 Rename getAnalysisToUpdate to getAnalysisIfAvailable. 
llvm-svn: 63198
 2009-01-28 13:14:17 +00:00
Evan Cheng
2a965124b7 The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. 
llvm-svn: 63195
 2009-01-28 08:35:02 +00:00
Mon P Wang
e1c886f775 Add shuffle splat pattern for x86 sse shifts. 
llvm-svn: 63193
 2009-01-28 08:12:05 +00:00
Evan Cheng
31f8d3639f Suppress a compile time warning. 
llvm-svn: 63161
 2009-01-28 00:53:34 +00:00
Anton Korobeynikov
7e63f1aae6 Treat [1 x i8] zeroinitializer as a C string, placing such stuff into 
mergeable string section. I don't see any bad impact of such decision
(rather then placing it into mergeable const section, as it was before),
but at least Darwin linker won't complain anymore.

The problem in LLVM is that we don't have special type for string constants
(like gcc does). Even more, we have two separate types: ConstatArray for non-null
strings and ConstantAggregateZero for null stuff.... It's a bit weird :)

llvm-svn: 63142
 2009-01-27 22:29:24 +00:00
Dan Gohman
c017343459 Reformat the allocation-order arrays to a more conventional style. 
llvm-svn: 63121
 2009-01-27 19:25:38 +00:00
Dan Gohman
f7e8bf0511 Respect the DisableRedZone flag on PowerPC. 
llvm-svn: 63119
 2009-01-27 19:19:28 +00:00
Dan Gohman
7d80f8688e Simplify findNonImmUse; return the result using the return value 
instead of via a by-reference argument. No functionality change.

llvm-svn: 63118
 2009-01-27 19:04:30 +00:00
Evan Cheng
a05436f739 Implement multiple with overflow by 2 with an add instruction. 
llvm-svn: 63090
 2009-01-27 03:30:42 +00:00
Dan Gohman
2e0343e321 Eliminate unnecessary operands-list traversals. 
llvm-svn: 63088
 2009-01-27 02:37:43 +00:00
Dan Gohman
f3c2ac3497 Enable the red zone on x86-64 by default. 
llvm-svn: 63078
 2009-01-27 00:58:47 +00:00
Dan Gohman
4ad174b236 Fix the Red Zone calculation for functions with frame pointers. 
Don't use the Red Zone when dynamic stack realignment is needed.
This could be implemented, but most x86-64 ABIs don't require
dynamic stack realignment so it isn't urgent.

llvm-svn: 63074
 2009-01-27 00:40:06 +00:00
Scott Michel
e00d746487 CellSPU: 
- Update DWARF debugging support.

llvm-svn: 63059
 2009-01-26 22:33:37 +00:00
Scott Michel
56fa9ba0b6 Make the Dwarf macro information section optional; CellSPU's assembler 
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.

llvm-svn: 63058
 2009-01-26 22:32:51 +00:00
Dan Gohman
3a51d8e847 Implement Red Zone utilization on x86-64. This is currently 
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.

llvm-svn: 63056
 2009-01-26 22:22:31 +00:00
Evan Cheng
ec03e0cd3b Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. 
llvm-svn: 63022
 2009-01-26 18:43:34 +00:00
Dan Gohman
4abaebae0c Take the next steps in making SDUse more consistent with LLVM Use, and 
tidy up SDUse and related code.
 - Replace the operator= member functions with a set method, like
   LLVM Use has, and variants setInitial and setNode, which take
   care up updating use lists, like LLVM Use's does. This simplifies
   code that calls these functions.
 - getSDValue() is renamed to get(), as in LLVM Use, though most
   places can either use the implicit conversion to SDValue or the
   convenience functions instead.
 - Fix some more node vs. value terminology issues.

Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.

llvm-svn: 62995
 2009-01-26 04:35:06 +00:00
Scott Michel
af51520775 Untabify code. 
llvm-svn: 62991
 2009-01-26 03:37:41 +00:00
Scott Michel
da9360e77e CellSPU: 
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>

llvm-svn: 62990
 2009-01-26 03:31:40 +00:00
Nate Begeman
48639fe6dc Fix a typo 
llvm-svn: 62989
 2009-01-26 03:15:54 +00:00
Nate Begeman
d2f708eca5 De-identifying per sabre review 
llvm-svn: 62988
 2009-01-26 03:15:31 +00:00
Nate Begeman
92efc4f0ce Map address space 256 to gs; similar mappings could be supported for the 
other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.

llvm-svn: 62980
 2009-01-26 01:24:32 +00:00
Nate Begeman
81d70f3f54 Support pattern matching various x86 sse shifts. 
llvm-svn: 62979
 2009-01-26 00:52:55 +00:00
Chris Lattner
e7bf6037e2 silence a warning when assertions are disabled. 
llvm-svn: 62976
 2009-01-25 23:08:00 +00:00
Torok Edwin
6f715ebe85 should have removed the + when manually applying a patch! 
llvm-svn: 62973
 2009-01-25 20:29:34 +00:00
Torok Edwin
3f54410405 revert this patch for now, because Codegen does still want to generate SSE code, 
for example in the case of va-args. XFAIL associated tests.

llvm-svn: 62972
 2009-01-25 20:21:24 +00:00
Torok Edwin
49b1d3e3cc If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402. 
llvm-svn: 62967
 2009-01-25 17:58:56 +00:00
Evan Cheng
71ca3e2bdb Private linkage support for PPC / Darwin. 
llvm-svn: 62955
 2009-01-25 06:32:01 +00:00
Nate Begeman
48f3fe9199 Fix an indent and a typo. 
llvm-svn: 62940
 2009-01-24 22:12:48 +00:00
Torok Edwin
6dd79be128 add note about possible GEP improvement with fields of size 0. 
llvm-svn: 62925
 2009-01-24 19:30:25 +00:00
Chris Lattner
97b6f6a674 hopefully address PR3379 by making the P modifier work in x86 inline asm. 
llvm-svn: 62887
 2009-01-23 22:33:40 +00:00
Bob Wilson
186046e657 Add SelectionDAG::getNOT method to construct bitwise NOT operations, 
corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.

llvm-svn: 62768
 2009-01-22 17:39:32 +00:00
Evan Cheng
c971801ae1 Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
llvm-svn: 62762
 2009-01-22 09:10:11 +00:00
Chris Lattner
fcf56e7fbe add a note 
llvm-svn: 62760
 2009-01-22 07:16:03 +00:00
Dan Gohman
29b575c6cd Recognize inline asm for bswap on x86-64 GLIBC. This allows it 
to be supported in the JIT.

llvm-svn: 62730
 2009-01-21 23:40:54 +00:00
Evan Cheng
43d680b0d8 Also favors NOT64r. 
llvm-svn: 62710
 2009-01-21 19:45:31 +00:00
Chris Lattner
2b6b947b4f fix warning in release-asserts mode and spelling of assert. 
llvm-svn: 62699
 2009-01-21 18:38:18 +00:00
Dan Gohman
704f0d5879 Fix a recent regression. ClrOpcode is not set for i8; for i8, if 
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.

llvm-svn: 62691
 2009-01-21 14:50:16 +00:00
Sanjiv Gupta
ebef67f13c Fixed build warnings. Restoring changes done in 62600, they were lost in 62655. 
llvm-svn: 62681
 2009-01-21 09:02:46 +00:00
Duncan Sands
392dc77fc6 Cleanup whitespace and comments, and tweak some 
prototypes, in operand type legalization.  No
functionality change.

llvm-svn: 62680
 2009-01-21 09:00:29 +00:00
Sanjiv Gupta
37fdb5ca11 Implement LowerOperationWrapper for legalizer. 
Also a few signed comparison fixes.

llvm-svn: 62665
 2009-01-21 05:44:05 +00:00
Scott Michel
c80e71ac35 CellSPU: 
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.

llvm-svn: 62664
 2009-01-21 04:58:48 +00:00
Evan Cheng
0ed6a9d7e0 Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661
 2009-01-21 02:09:05 +00:00
Evan Cheng
b3c82db63d Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 
llvm-svn: 62600
 2009-01-20 19:12:24 +00:00
Dan Gohman
7663e08915 Add a README entry noticed while investigating PR3216. 
llvm-svn: 62558
 2009-01-20 01:07:33 +00:00
Evan Cheng
06cfade044 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
llvm-svn: 62519
 2009-01-19 19:06:11 +00:00
Evan Cheng
3c00875658 Fix 80 col violations. 
llvm-svn: 62518
 2009-01-19 18:57:29 +00:00
Evan Cheng
2f50b49f22 Handle ISD::DECLARE with PIC relocation model. 
llvm-svn: 62516
 2009-01-19 18:31:51 +00:00
Evan Cheng
a14fd26a8b Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting. 
%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>

The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.

llvm-svn: 62505
 2009-01-19 08:19:57 +00:00
Evan Cheng
53e83a2eb9 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.

llvm-svn: 62504
 2009-01-19 08:08:22 +00:00
Bill Wendling
ce30a8cab9 Extend thi 
llvm-svn: 62415
 2009-01-17 07:40:19 +00:00
Evan Cheng
182d9c4c9f Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
llvm-svn: 62413
 2009-01-17 07:09:27 +00:00
Bill Wendling
ddd55bdfec Temporarily revert my last change. It is causing a bootstrap failure. 
llvm-svn: 62405
 2009-01-17 04:23:51 +00:00
Bill Wendling
d18c38c0f2 Implement a special algorithm for converting uint_to_fp for i32 values on 
X86. This code:

void f() {
  uint32_t x;
  float y = (float)x;
}

used to be:

     movl     %eax, -8(%ebp)
     movl     [2^52 double], -4(%ebp)
     movsd    -8(%ebp), %xmm0
     subsd    [2^52 double], %xmm0
     cvtsd2ss %xmm0, %xmm0

Is now:

   movsd        [2^52 double], %xmm0
   movsd        %xmm0, %xmm1
   movd         %ecx, %xmm2
   orps         %xmm2, %xmm1
   subsd        %xmm0, %xmm1
   cvtsd2ss     %xmm1, %xmm0

This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.

llvm-svn: 62404
 2009-01-17 03:56:04 +00:00
Oscar Fuentes
ee36d9ce83 CMake: Add lib/Target/IA64/IA64Subtarget.cpp 
llvm-svn: 62394
 2009-01-17 01:50:32 +00:00