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e4ab085322
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2603 Commits

Author SHA1 Message Date
Benjamin Kramer
e4ab085322 Emit the SubRegTable with the smallest possible integer type. 
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

llvm-svn: 151760
 2012-02-29 21:57:08 +00:00
Jim Grosbach
ccc97aa21e Tidy up. Spelling. 
llvm-svn: 151758
 2012-02-29 21:46:32 +00:00
Jim Grosbach
f0509324e0 Move the subregister indicies enum into the REGINFO_ENUM section. 
llvm-svn: 151756
 2012-02-29 21:43:16 +00:00
Jim Grosbach
1105208aec Switch TargetRegisterInfo::getSubReg() to use a lookup table. 
Instead of nested switch statements, use a lookup table. On ARM, this replaces
a 23k (x86_64 release build) function with a 16k table. Its not unlikely to
be faster, as well.

llvm-svn: 151751
 2012-02-29 20:31:17 +00:00
Craig Topper
f86322b091 Convert generated intrinsic attributes to use an array lookup as Chris suggested in PR11951. 
llvm-svn: 151622
 2012-02-28 06:32:00 +00:00
Craig Topper
ae4e236c50 Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files. 
llvm-svn: 151513
 2012-02-27 02:31:09 +00:00
Craig Topper
ab46706aa9 X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo. 
llvm-svn: 151510
 2012-02-27 01:54:29 +00:00
Craig Topper
b1b20ead88 Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that were added in r151038. 
llvm-svn: 151246
 2012-02-23 08:42:06 +00:00
Craig Topper
d8faffd93b Declare register classes as const. Fix a couple pointers to register classes that weren't already const. 
llvm-svn: 151138
 2012-02-22 07:28:11 +00:00
Craig Topper
3ed929de0a Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified. 
llvm-svn: 151134
 2012-02-22 05:59:10 +00:00
Craig Topper
f1056941f6 Reorder some members in MCRegisterClass to remove padding on 64-bit builds. 
llvm-svn: 151043
 2012-02-21 07:36:39 +00:00
Craig Topper
24cc28c7b8 In generated RegisterInfo files, replace a pointer to the end of an array with just the size of the array to avoid relocations. 
llvm-svn: 151041
 2012-02-21 06:54:41 +00:00
Craig Topper
91a96474a1 Merge some tables in generated RegisterInfo file. Store indices into larger table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038. 
llvm-svn: 151039
 2012-02-21 06:23:21 +00:00
Ahmed Charles
745c53c2a7 Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 
llvm-svn: 150918
 2012-02-19 11:37:01 +00:00
Craig Topper
cfbfa3dcd1 Add vmfunc instruction to X86 assembler and disassembler. 
llvm-svn: 150899
 2012-02-19 01:39:49 +00:00
Craig Topper
ecf21d8132 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. 
llvm-svn: 150873
 2012-02-18 08:19:49 +00:00
Benjamin Kramer
44e872829d Make the EDis tables const. 
llvm-svn: 150304
 2012-02-11 14:51:07 +00:00
Benjamin Kramer
675a84a6ea Reuse the enum names from X86Desc in the X86Disassembler. 
This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.

llvm-svn: 150303
 2012-02-11 14:50:54 +00:00
Benjamin Kramer
ba4dff0d18 Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc. 
Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

llvm-svn: 150245
 2012-02-10 13:18:44 +00:00
Benjamin Kramer
260bef228a Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors. 
llvm-svn: 150173
 2012-02-09 12:35:37 +00:00
Benjamin Kramer
005987fe7a Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per entry on x86_64. 
No change on i386.

llvm-svn: 150170
 2012-02-09 11:25:09 +00:00
James Molloy
85be8f7f88 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. 
llvm-svn: 150169
 2012-02-09 10:56:31 +00:00
Craig Topper
c20605c287 More tweaks to get the size of the X86 disassembler tables down. 
llvm-svn: 150167
 2012-02-09 08:58:07 +00:00
Craig Topper
82b0ee4558 Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. 
llvm-svn: 150161
 2012-02-09 07:45:30 +00:00
Benjamin Kramer
38ab261390 Don't map registers to the invalid dwarf register (-1). It's the default value. 
X86GenRegisterInfo.inc | 1032 -------------------------------------------------
  1 file changed, 1032 deletions(-)

llvm-svn: 150080
 2012-02-08 18:46:26 +00:00
Benjamin Kramer
b42d2a7238 Value initialize MCRegisterClasses. Not sure how could miss this during the MCTargetDesc refactor. 
llvm-svn: 150076
 2012-02-08 14:43:53 +00:00
Craig Topper
dfa8617ab9 Convert assert(0) to llvm_unreachable 
llvm-svn: 149814
 2012-02-05 07:21:30 +00:00
Brendon Cahoon
6db000fe17 Increment DFAStateEntryTable index for sentinel entry. 
When adding the {-1, -1} entry to the DFAStateInputTable, we
need to increment the index used to populate the DFAStateEntryTable.
Otherwise, the entry table will be off by one for each transition
after the {-1, -1} entry. PR11908.

llvm-svn: 149713
 2012-02-03 21:08:25 +00:00
Jakob Stoklund Olesen
230a0a4b40 Specify SubRegIndex components on the index itself. 
It is simpler to define a composite index directly:

  def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
  def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;

Than specifying the composite indices on each register:

  CompositeIndices = [(ssub_2 dsub_1, ssub_0),
                      (ssub_3 dsub_1, ssub_1)] in ...

This also makes it clear that SubRegIndex composition is supposed to be
unique.

llvm-svn: 149556
 2012-02-01 23:16:41 +00:00
Jakob Stoklund Olesen
b1190d3876 Fix a bug in the TopoOrderRC comparison function. 
The final tie breaker comparison also needs to return +/-1, or 0.
This is not a less() function.

This could cause otherwise identical super-classes to be ordered
unstably, depending on what the system qsort routine does with a bad
compare function.

llvm-svn: 149549
 2012-02-01 22:19:26 +00:00
Jakob Stoklund Olesen
758a27584a Avoid emitting empty arrays, they're not standard C++. 
It's only by luck that we haven't produced any yet, and clang refuses to
compile them.

llvm-svn: 149546
 2012-02-01 22:12:51 +00:00
Jakob Stoklund Olesen
22b91563a5 Don't assign a value to NUM_TARGET_NAMED_SUBREGS. 
It was wrong and completely unused.

llvm-svn: 149433
 2012-01-31 21:51:53 +00:00
Jakob Stoklund Olesen
6ce052d3b3 Move the composite map into CodeGenSubRegIndex. 
Each SubRegIndex keeps track of how it composes.

llvm-svn: 149423
 2012-01-31 21:44:11 +00:00
Jakob Stoklund Olesen
6ec7412170 Add a TableGen CodeGenSubRegIndex class. 
This class is used to represent SubRegIndex instances instead of the raw
Record pointers that were used before.

No functional change intended.

llvm-svn: 149418
 2012-01-31 20:57:55 +00:00
Jim Grosbach
8ed72f3cc0 Tidy up. Trailing whitespace. 
llvm-svn: 148856
 2012-01-24 21:06:59 +00:00
Owen Anderson
7492e4ff85 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand. 
llvm-svn: 148833
 2012-01-24 18:37:29 +00:00
Jakob Stoklund Olesen
3ff9738293 Add an (interleave A, B, ...) SetTheory operator. 
This will interleave the elements from two or more lists.

llvm-svn: 148824
 2012-01-24 18:06:05 +00:00
Jakob Stoklund Olesen
e9c53bc69b Add a CoveredBySubRegs property to Register descriptions. 
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363
 2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
c5fac0a05c Add TableGen support for callee saved registers. 
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().

llvm-svn: 148346
 2012-01-17 22:46:58 +00:00
Devang Patel
84d275a823 Intel syntax: Ignore mnemonic aliases. 
llvm-svn: 148316
 2012-01-17 18:30:45 +00:00
David Blaikie
81e875f888 Provide better messages in llvm_unreachable. 
llvm-svn: 148293
 2012-01-17 07:00:13 +00:00
David Blaikie
2526691971 Remove unreachable code. (replace with llvm_unreachable to help GCC where necessary) 
llvm-svn: 148284
 2012-01-17 04:43:56 +00:00
David Blaikie
067ad0b263 Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly. 
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

llvm-svn: 148262
 2012-01-16 23:24:27 +00:00
Jakob Stoklund Olesen
c477c8d35e Skip the NAME field when forming tuples. 
llvm-svn: 148147
 2012-01-13 22:23:50 +00:00
Jakob Stoklund Olesen
9ba097a208 Delete CodeInit and CodeRecTy from TableGen. 
The code type was always identical to a string anyway. Now it is simply
a synonym. The code literal syntax [{...}] is still valid.

llvm-svn: 148092
 2012-01-13 03:38:34 +00:00
Pete Cooper
f3141fef55 Added MVT::v2f16 
llvm-svn: 148067
 2012-01-12 23:14:13 +00:00
Devang Patel
c1e4ca5839 Record asm variant id in MatchEntry and check it while matching instruction. 
llvm-svn: 147858
 2012-01-10 17:50:43 +00:00
David Blaikie
8d47bb30e3 Remove unnecessary default cases in switches that cover all enum values. 
llvm-svn: 147855
 2012-01-10 16:47:17 +00:00
Devang Patel
77ab1ea721 Use descriptive variable name and remove incorrect operand number check. 
llvm-svn: 147802
 2012-01-09 21:30:46 +00:00
Devang Patel
921a16318d Split AsmParser into two components - AsmParser and AsmParserVariant 
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.

llvm-svn: 147787
 2012-01-09 19:13:28 +00:00