Krzysztof Parzyszek cfa276ba08 [Hexagon] Convert HVX vector constants of i1 to i8 ... Certain operations require vector of i1 values. However, for Hexagon architecture compatibility, they need to be represented as vector of i8. Patch by Suyog Sarda. llvm-svn: 309677		2017-08-01 13:12:53 +00:00
..
intrinsics	[Hexagon] Add intrinsics for data cache operations	2017-07-14 15:58:48 +00:00
loop-idiom	[Hexagon] Stop pmpy recognition when shift conversion fails	2017-06-13 13:51:49 +00:00
vect	[Hexagon] Remove custom lowering of loads of v4i16	2017-07-17 15:45:45 +00:00
absaddr-store.ll
absimm.ll
adde.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
addh-sext-trunc.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addh-shifted.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addh.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addr-calc-opt.ll
addrmode-globoff.mir	[Hexagon] Generate proper offset in opt-addr-mode	2017-04-19 15:15:51 +00:00
addrmode-indoff.ll
addrmode-keepdeadphis.mir	[Hexagon] Keep all phi nodes when building DFG in addr-mode-opt	2017-06-29 15:55:59 +00:00
adjust-latency-stackST.ll	[Hexagon] Adjust latency between allocframe and the first store on stack	2017-05-03 15:33:09 +00:00
alu64.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
always-ext.ll
anti-dep-partial.mir
args.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
ashift-left-right.ll
Atomics.ll
avoid-predspill-calleesaved.ll	[Hexagon] Start using regmasks on calls	2017-02-17 22:14:51 +00:00
avoid-predspill.ll
barrier-flag.ll
base-offset-addr.ll
base-offset-post.ll
bit-bitsplit-at.ll	[Hexagon] Fixes to the bitsplit generation	2017-03-09 22:02:14 +00:00
bit-bitsplit-src.ll	[Hexagon] Generate bitsplit instruction	2017-03-07 23:08:35 +00:00
bit-bitsplit.ll	[Hexagon] Generate bitsplit instruction	2017-03-07 23:08:35 +00:00
bit-eval.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bit-ext-sat.ll	[Hexagon] Handle saturations in Hexagon bit tracker	2017-02-23 22:11:52 +00:00
bit-extract-off.ll	[Hexagon] Use correct offset when extracting from the high word	2017-03-08 15:46:28 +00:00
bit-extract.ll	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
bit-extractu-half.ll
bit-gen-rseq.ll
bit-has.ll	[Hexagon] Check for presence before looking registers up in bit tracker	2017-03-07 23:12:04 +00:00
bit-loop-rc-mismatch.ll
bit-loop.ll
bit-phi.ll	[Hexagon] Do not insert instructions before PHI nodes	2017-03-07 14:20:19 +00:00
bit-rie.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
bit-skip-byval.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bit-validate-reg.ll	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
bit-visit-flowq.ll
bitconvert-vector.ll
bitmanip.ll	[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE	2017-02-23 15:02:09 +00:00
block-addr.ll	[Hexagon] Early-if-convert branches that may exit the loop	2017-03-06 17:24:04 +00:00
block-ranges-nodef.ll
branch-folder-hoist-kills.mir	Remove stale live-ins in the branch folder	2017-05-05 12:20:07 +00:00
branch-non-mbb.ll
branchfolder-keep-impdef.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
BranchPredict.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
brev_ld.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
brev_st.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bugAsmHWloop.ll
build-vector-shuffle.ll
builtin-expect.ll	[Hexagon] Pick the right branch opcode depending on branch probabilities	2017-03-02 21:49:49 +00:00
builtin-prefetch-offset.ll
builtin-prefetch.ll
calling-conv-2.ll
callr-dep-edge.ll
cext-check.ll
cext-valid-packet1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cext-valid-packet2.ll
cext.ll
cexti16.ll
cfgopt-fall-through.ll	[Hexagon] Do not move a block if it is on a fall-through path	2017-04-28 21:54:11 +00:00
cfi-late.ll
cfi-offset.ll
checktabs.ll
circ_ld.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ_ldd_bug.ll
circ_ldw.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ_st.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ-load-isel.ll
clr_set_toggle.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cmp_pred2.ll
cmp_pred_reg.ll
cmp_pred.ll
cmp-extend.ll
cmp-promote.ll
cmp-to-genreg.ll
cmp-to-predreg.ll
cmp.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cmpb_pred.ll
cmpb-eq.ll
combine_ir.ll
combine.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
common-gep-basic.ll
common-gep-icm.ll
common-gep-inbounds.ll	[Hexagon] Generate 'inbounds' GEPs in HexagonCommonGEP	2017-06-07 20:04:33 +00:00
compound.ll	[Hexagon] Start using regmasks on calls	2017-02-17 22:14:51 +00:00
const64.ll
const-pool-tf.ll
constp-clb.ll
constp-combine-neg.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
constp-ctb.ll
constp-extract.ll
constp-physreg.ll
constp-rewrite-branches.ll
constp-rseq.ll
constp-vsplat.ll
convert_const_i1_to_i8.ll	[Hexagon] Convert HVX vector constants of i1 to i8	2017-08-01 13:12:53 +00:00
convert-to-dot-old.ll	[Hexagon] Pick a dot-old instruction that matches the architecture	2017-03-06 17:03:16 +00:00
convertdptoint.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
convertdptoll.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
convertsptoint.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
convertsptoll.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
copy-to-combine-dbg.ll
csr-func-usedef.ll
ctor.ll
dadd.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
dead-store-stack.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
dmul.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
double.ll
doubleconvert-ieee-rnd-near.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
dsub.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
dualstore.ll
duplex-addi-global-imm.mir	[Hexagon] Fix typo in a testcase	2017-06-22 16:25:46 +00:00
duplex.ll
early-if-conversion-bug1.ll
early-if-merge-loop.ll	[Hexagon] Early-if-convert branches that may exit the loop	2017-03-06 17:24:04 +00:00
early-if-phi-i1.ll	[Hexagon] Add -march=hexagon to a testcase	2017-03-21 16:59:40 +00:00
early-if-spare.ll
early-if-vecpi.ll
early-if-vecpred.ll	[Hexagon] Skip blocks that define vector predicate registers in early-if	2017-03-02 18:10:59 +00:00
early-if.ll
eh_return.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
eliminate-pred-spill.ll	[Hexagon] Use -mattr to select HVX mode in a testcase, NFC	2017-04-05 19:46:37 +00:00
expand-condsets-basic.ll
expand-condsets-dead-bad.ll	[Hexagon] Mark dead defs as <dead> in expand-condsets	2017-03-06 17:09:06 +00:00
expand-condsets-dead-pred.ll	[Hexagon] Mark dead defs as <dead> in expand-condsets	2017-03-06 17:09:06 +00:00
expand-condsets-def-undef.mir
expand-condsets-extend.ll
expand-condsets-imm.mir	[Hexagon] Handle more types of immediate operands in expand-condsets	2017-06-21 19:21:30 +00:00
expand-condsets-impuse.mir
expand-condsets-pred-undef.ll
expand-condsets-rm-reg.mir	Bring back 2>&1 redirection for this test	2017-02-22 19:16:33 +00:00
expand-condsets-rm-segment.ll
expand-condsets-same-inputs.mir
expand-condsets-undef2.ll
expand-condsets-undef.ll
expand-condsets-undefvni.ll	Missed a check for UndefVI in r306466	2017-06-28 15:46:16 +00:00
expand-vselect-kill.ll	[Hexagon] Use proper predicate register state when expanding PS_vselect	2017-06-27 19:59:46 +00:00
expand-vstorerw-undef2.ll	[Hexagon] Remove dead defs from the live set when expanding wstores	2017-01-18 23:11:40 +00:00
expand-vstorerw-undef.ll
extload-combine.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
extract-basic.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
fadd.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
fcmp.ll
find-loop-instr.ll	[Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructions	2017-02-02 19:36:37 +00:00
fixed-spill-mutable.ll
float-amode.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
float.ll
floatconvert-ieee-rnd-near.ll
fminmax.ll
fmul.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
fpelim-basic.ll	[Hexagon] Implement frame pointer elimination with -fomit-frame-pointer	2017-06-30 21:21:40 +00:00
frame-offset-overflow.ll
fsel.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
fsub.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
fusedandshift.ll	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
hasfp-crash1.ll	[Hexagon] Do not rely on callee-saved info in hasFP	2017-07-11 17:11:54 +00:00
hasfp-crash2.ll	[Hexagon] Do not rely on callee-saved info in hasFP	2017-07-11 17:11:54 +00:00
hvx-nontemporal.ll	[Hexagon] Add support for nontemporal loads and stores on HVX	2017-07-11 16:39:33 +00:00
hwloop1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop3.ll
hwloop4.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop5.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop-cleanup.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop-const.ll
hwloop-crit-edge.ll
hwloop-dbg.ll
hwloop-le.ll
hwloop-loop1.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
hwloop-lt1.ll
hwloop-lt.ll
hwloop-missed.ll
hwloop-ne.ll
hwloop-noreturn-call.ll
hwloop-ph-deadcode.ll
hwloop-pos-ivbump1.ll
hwloop-preh.ll
hwloop-preheader.ll
hwloop-range.ll
hwloop-recursion.ll
hwloop-wrap2.ll
hwloop-wrap.ll
i1_VarArg.ll
i8_VarArg.ll
i16_VarArg.ll
idxload-with-zero-offset.ll
ifcvt-diamond-bad.ll
ifcvt-diamond-bug-2016-08-26.ll	[Hexagon] Fix typo in HexagonEarlyIfCConv.cpp	2017-03-31 20:36:00 +00:00
ifcvt-edge-weight.ll
ifcvt-impuse-livein.mir
ifcvt-live-subreg.mir
ifcvt-simple-bprob.ll	[IfConversion] Only renormalize probabilities if branches are analyzable	2017-03-06 19:12:42 +00:00
indirect-br.ll
inline-asm-a.ll	[Hexagon] Add inline-asm constraint 'a' for modifier register class	2017-07-21 17:51:27 +00:00
inline-asm-hexagon.ll
inline-asm-i1.ll
inline-asm-qv.ll
inline-asm-vecpred128.ll	[Hexagon] Properly handle 'q' constraint in 128-byte vector mode	2017-03-02 17:50:24 +00:00
insert4.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
insert-basic.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
invalid-dotnew-attempt.mir	[Hexagon] Fix dependence check in the packetizer	2017-06-01 18:02:40 +00:00
is-legal-void.ll
isel-exti1.ll	[Hexagon] Fix instruction selection for sign-extending i1 to i64	2017-02-28 22:37:01 +00:00
isel-i1arg-crash.ll	[Hexagon] Fix lowering of formal arguments of type i1	2017-03-01 17:30:10 +00:00
isel-op-zext-i1.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
jt-in-text.ll	[Hexagon] Emit jump tables in text section based on a flag	2017-06-30 20:21:48 +00:00
lit.local.cfg
livephysregs-lane-masks2.mir
livephysregs-lane-masks.mir
loadi1-G0.ll
loadi1-v4-G0.ll
loadi1-v4.ll
loadi1.ll
long-calls.ll
loop-prefetch.ll
lower-extract-subvector.ll
macint.ll
maxd.ll
maxh.ll
maxud.ll
maxuw.ll
maxw.ll
mem-fi-add.ll
memcpy-likely-aligned.ll
memops1.ll
memops2.ll
memops3.ll
memops-stack.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
memops.ll
mind.ll
minu-zext-8.ll
minu-zext-16.ll
minud.ll
minuw.ll
minw.ll
misaligned_double_vector_store_not_fast.ll
misaligned-access.ll
misched-top-rptracker-sync.ll
mpy.ll
mul64-sext.ll	[Hexagon] Improve code generation for 32x32-bit multiplication	2017-05-30 17:47:51 +00:00
mulh.ll	[Hexagon] Generate multiply-high instruction in isel	2017-06-13 16:21:57 +00:00
mulhs.ll
multi-cycle.ll	[Hexagon] Don't ignore mult-cycle latency information	2017-05-02 18:12:19 +00:00
mux-basic.ll
mux-kill1.mir	[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux	2017-06-22 20:43:02 +00:00
mux-kill2.mir	[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux	2017-06-22 20:43:02 +00:00
mux-kill3.mir	[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux	2017-06-22 20:43:02 +00:00
mux-undef.ll	[Hexagon] Skip mux generation when predicate register is undefined	2017-06-08 20:56:36 +00:00
newify-crash.ll	[Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist	2017-06-02 14:07:06 +00:00
newvaluejump2.ll	[Hexagon] Implement frame pointer elimination with -fomit-frame-pointer	2017-06-30 21:21:40 +00:00
newvaluejump3.ll	[Hexagon] Avoid IMPLICIT_DEFs as new-value producers	2017-02-23 17:47:34 +00:00
newvaluejump-c4.mir	[Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJump	2017-07-24 19:35:48 +00:00
newvaluejump-kill2.mir	[Hexagon] Update kills in hexagon-nvj even more properly than before	2017-06-27 18:37:16 +00:00
newvaluejump-kill.ll	[Hexagon] Properly update kill flags in HexagonNewValueJump	2017-06-22 21:11:44 +00:00
newvaluejump.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
newvalueSameReg.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
newvaluestore.ll
NVJumpCmp.ll
opt-addr-mode.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-fabs.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-fneg.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-spill-volatile.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
packetize_cond_inst.ll
packetize-cfi-location.ll
packetize-return-arg.ll
packetize-tailcall-arg.ll
peephole-kill-flags.ll
peephole-op-swap.ll
pic-jumptables.ll
pic-local.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
pic-regusage.ll
pic-simple.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
pic-static.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
plt-rel.ll	[Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCREL	2017-05-02 18:15:33 +00:00
post-inc-aa-metadata.ll
post-ra-kill-update.mir	ScheduleDAGInstrs: Fix fixupKills()	2017-05-27 02:50:50 +00:00
postinc-baseoffset.mir	[Hexagon] Fix a bug in r308502: post-inc offset is always 0	2017-07-19 19:17:32 +00:00
postinc-load.ll
postinc-offset.ll
postinc-store.ll
pred-absolute-store.ll	[RDF] Remove the map of reaching defs from copy propagation	2017-03-10 22:44:24 +00:00
pred-gp.ll
pred-instrs.ll
predicate-copy.ll
predicate-logical.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
predicate-rcmp.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
propagate-vcombine.ll
rdf-copy-undef2.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
rdf-copy.ll
rdf-cover-use.ll	[RDF] Remove covered parts of reached uses for phi and use in same block	2017-05-05 22:10:32 +00:00
rdf-dead-loop.ll
rdf-def-mask.ll	[RDF] Correctly calculate lane masks for defs	2017-04-28 21:57:53 +00:00
rdf-extra-livein.ll
rdf-filter-defs.ll
rdf-ignore-undef.ll
rdf-inline-asm-fixed.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
rdf-inline-asm.ll
rdf-multiple-phis-up.ll
rdf-phi-shadows.ll
rdf-phi-up.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
rdf-reset-kills.ll
readcyclecounter.ll	[Hexagon] Implement @llvm.readcyclecounter()	2017-02-22 22:28:47 +00:00
reg-scavengebug-3.ll
reg-scavenger-valid-slot.ll
regalloc-bad-undef.mir	Add extra operand to CALLSEQ_START to keep frame part set up previously	2017-05-09 13:35:13 +00:00
regalloc-block-overlap.ll	Treat segment [B, E) as not overlapping block with boundaries [A, B)	2017-01-18 23:12:19 +00:00
regalloc-liveout-undef.mir	Create a PHI value when merging with a known undef live-in	2017-06-27 21:30:46 +00:00
relax.ll
remove_lsr.ll
remove-endloop.ll
restore-single-reg.ll
ret-struct-by-val.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
runtime-stkchk.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
sdata-array.ll
sdata-basic.ll
sdr-basic.ll
sdr-shr32.ll
section_7275.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
select-instr-align.ll
sf-min-max.ll
sffms.ll
shrink-frame-basic.ll
signed_immediates.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
simple_addend.ll
simpletailcall.ll
split-const32-const64.ll
stack-align1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-align2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-align-reset.ll	[Hexagon] Handle cases when the aligned stack pointer is missing	2017-06-26 14:17:58 +00:00
stack-alloca1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-alloca2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
static.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
store-imm-large-stack.ll	[Hexagon] Recognize potential offset overflow for store-imm to stack	2017-06-22 14:11:23 +00:00
store-imm-stack-object.ll	[Hexagon] Generate store-immediate instructions for stack objects	2017-06-13 17:10:16 +00:00
store-shift.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
store-widen-aliased-load.ll
store-widen-negv2.ll
store-widen-negv.ll
store-widen.ll
storerd-io-over-rr.ll
storerinewabs.ll
struct_args_large.ll
struct_args.ll
sube.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
subi-asl.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
SUnit-boundary-prob.ll
switch-lut-explicit-section.ll	[Hexagon] Emit lookup tables in text section based on a flag	2017-07-18 15:31:37 +00:00
switch-lut-function-section.ll	[Hexagon] Emit lookup tables in text section based on a flag	2017-07-18 15:31:37 +00:00
switch-lut-multiple-functions.ll	[Hexagon] Emit lookup tables in text section based on a flag	2017-07-18 15:31:37 +00:00
switch-lut-text-section.ll	[Hexagon] Emit lookup tables in text section based on a flag	2017-07-18 15:31:37 +00:00
swp-const-tc.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-dag-phi.ll
swp-epilog-phi10.ll
swp-epilog-reuse-1.ll
swp-epilog-reuse.ll
swp-matmul-bitext.ll	[Hexagon] Use automatically-generated scheduling information for HVX	2017-05-03 20:10:36 +00:00
swp-max.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-multi-loops.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-prolog-phi4.ll
swp-stages4.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-stages5.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-vect-dotprod.ll
swp-vmult.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-vsum.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tail-call-mem-intrinsics.ll
tail-call-trunc.ll
tail-dup-subreg-abort.ll
tail-dup-subreg-map.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tailcall_fastcc_ccc.ll
target-flag-ext.mir	[Hexagon] Fix check for HMOTF_ConstExtend operand flag	2017-07-10 18:38:52 +00:00
tfr-to-combine.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tls_pic.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tls_static.ll
two-crash.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
undo-dag-shift.ll	[Hexagon] Undo shift folding where it could simplify addressing mode	2017-02-24 23:34:24 +00:00
union-1.ll
unreachable-mbb-phi-subreg.mir	Properly handle PHIs with subregisters in UnreachableBlockElim	2017-04-28 21:56:33 +00:00
usr-ovf-dep.ll
v6vec-vprint.ll	[llvm] Remove redundant check-prefix=CHECK from tests. NFC.	2017-07-17 17:32:45 +00:00
v60-cur.ll
v60-vsel1.ll
v60Intrins.ll
v60small.ll
v60Vasr.ll
vaddh.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
validate-offset.ll
vassign-to-combine.ll
vdmpy-halide-test.ll
vec-pred-spill1.ll
vec-vararg-align.ll	[Hexagon] Handle cases when the aligned stack pointer is missing	2017-06-26 14:17:58 +00:00
vector-align.ll
vector-ext-load.ll
vload-postinc-sel.ll
vmpa-halide-test.ll
vpack_eo.ll
vselect-pseudo.ll
vsplat-isel.ll
zextloadi1.ll