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AsmParser
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[AMDGPU] Simplify some generation checks. NFC.
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2020-12-01 10:15:32 +00:00 |
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Disassembler
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[AMDGPU] Introduce and use isGFX10Plus. NFC.
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2020-11-26 09:02:36 +00:00 |
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MCTargetDesc
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[AMDGPU] Introduce and use isGFX10Plus. NFC.
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2020-11-26 09:02:36 +00:00 |
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TargetInfo
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llvmbuildectomy - replace llvm-build by plain cmake
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2020-11-13 10:35:24 +01:00 |
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Utils
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[AMDGPU] Introduce and use isGFX10Plus. NFC.
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2020-11-26 09:02:36 +00:00 |
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AMDGPU.h
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[amdgpu] Add the late codegen preparation pass.
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2020-10-27 14:07:59 -04:00 |
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AMDGPU.td
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Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
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2020-11-11 14:40:14 +00:00 |
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AMDGPUAliasAnalysis.cpp
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[amdgpu] Enhance AMDGPU AA.
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2020-10-20 09:54:12 -04:00 |
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AMDGPUAliasAnalysis.h
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Remove orphan AMDGPUAAResult::Aliases and AMDGPUAAResult::PathAliases declarations. NFC.
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2020-06-25 16:00:44 +01:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPUAnnotateUniformValues.cpp
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[AA] Split up LocationSize::unknown()
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2020-11-26 18:39:55 +01:00 |
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AMDGPUArgumentUsageInfo.cpp
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AMDGPU/GlobalISel: Add types to special inputs
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2020-07-06 17:00:55 -04:00 |
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AMDGPUArgumentUsageInfo.h
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AMDGPU: Use MCRegister for preloaded arguments
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2020-07-20 13:34:28 -04:00 |
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AMDGPUAsmPrinter.cpp
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[AMDGPU] Introduce and use isGFX10Plus. NFC.
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2020-11-26 09:02:36 +00:00 |
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AMDGPUAsmPrinter.h
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[AMDGPU] Emit stack frame size in metadata
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2020-11-25 16:30:02 +01:00 |
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AMDGPUAtomicOptimizer.cpp
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[AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer
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2020-09-30 11:09:18 +02:00 |
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AMDGPUCallingConv.td
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[AMDGPU] Add amdgpu_gfx calling convention
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2020-11-09 16:51:44 +01:00 |
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AMDGPUCallLowering.cpp
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[AMDGPU] Omit buffer resource with flat scratch.
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2020-11-09 08:05:20 -08:00 |
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AMDGPUCallLowering.h
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AMDGPU/GlobalISel: Mark GlobalISel classes as final
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2020-07-28 11:42:17 -04:00 |
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AMDGPUCodeGenPrepare.cpp
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SelectionDAG.h - remove unnecessary FunctionLoweringInfo.h include. NFCI.
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2020-09-03 18:33:25 +01:00 |
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AMDGPUCombine.td
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AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner
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2020-11-03 09:24:50 +01:00 |
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AMDGPUExportClustering.cpp
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[AMDGPU] Fix scheduling of exp pos4
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2020-11-12 19:57:14 +00:00 |
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AMDGPUExportClustering.h
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AMDGPUFeatures.td
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AMDGPU: Change internal tracking of wave size
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2020-06-01 17:55:08 -04:00 |
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AMDGPUFixFunctionBitcasts.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUGenRegisterBankInfo.def
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AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping
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2020-08-17 09:53:26 -04:00 |
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AMDGPUGISel.td
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[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
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2020-08-21 12:26:31 +02:00 |
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AMDGPUGlobalISelUtils.cpp
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[AMDGPU] Remove an unused return value. NFC.
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2020-11-10 09:15:14 +00:00 |
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AMDGPUGlobalISelUtils.h
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[AMDGPU] Remove an unused return value. NFC.
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2020-11-10 09:15:14 +00:00 |
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AMDGPUHSAMetadataStreamer.cpp
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AMDGPU: Start interpreting byref on kernel arguments
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2020-07-21 18:11:22 -04:00 |
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AMDGPUHSAMetadataStreamer.h
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AMDGPU: Start interpreting byref on kernel arguments
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2020-07-21 18:11:22 -04:00 |
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AMDGPUInline.cpp
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[NFC] Remove unused GetUnderlyingObject paramenter
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2020-07-31 02:10:03 -07:00 |
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AMDGPUInstCombineIntrinsic.cpp
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[AMDGPU] Add simplification/combines for llvm.amdgcn.fma.legacy
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2020-10-23 16:16:13 +01:00 |
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AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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[AMDGPU] Use tablegen for argument indices
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2020-10-05 11:50:52 +02:00 |
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AMDGPUInstrInfo.td
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AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
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2020-06-16 21:06:25 -04:00 |
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AMDGPUInstructions.td
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[TableGen] Add the !filter bang operator.
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2020-11-09 10:56:55 -05:00 |
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AMDGPUInstructionSelector.cpp
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[AMDGPU] Introduce and use isGFX10Plus. NFC.
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2020-11-26 09:02:36 +00:00 |
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AMDGPUInstructionSelector.h
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AMDGPU: Split large offsets when selecting global saddr mode
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2020-11-16 11:36:01 -05:00 |
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AMDGPUISelDAGToDAG.cpp
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AMDGPU: Select global saddr mode from SGPR pointer
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2020-11-16 11:51:06 -05:00 |
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AMDGPUISelLowering.cpp
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[AMDGPU] Add amdgpu_gfx calling convention
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2020-11-09 16:51:44 +01:00 |
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AMDGPUISelLowering.h
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[AMDGPU] Some refactoring after D90404. NFC.
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2020-11-01 13:18:53 +05:30 |
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AMDGPULateCodeGenPrepare.cpp
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[amdgpu] Add the late codegen preparation pass.
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2020-10-27 14:07:59 -04:00 |
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AMDGPULegalizerInfo.cpp
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[AMDGPU] Fix v3f16 interaction with image store workaround
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2020-11-18 18:21:04 +01:00 |
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AMDGPULegalizerInfo.h
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[AMDGPU] Implement hardware bug workaround for image instructions
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2020-10-07 07:39:52 -04:00 |
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AMDGPULibCalls.cpp
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[AMDGPU] Mark sin/cos load folding as modifying the function.
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2020-11-13 14:49:33 -08:00 |
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AMDGPULibFunc.cpp
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[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
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2020-05-29 17:54:17 -07:00 |
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AMDGPULibFunc.h
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AMDGPULowerIntrinsics.cpp
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AMDGPU: Use caller subtarget, not intrinsic declaration
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2020-08-27 16:42:09 -04:00 |
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AMDGPULowerKernelArguments.cpp
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AMDGPU: Start interpreting byref on kernel arguments
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2020-07-21 18:11:22 -04:00 |
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AMDGPULowerKernelAttributes.cpp
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AMDGPUMachineCFGStructurizer.cpp
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[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
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2020-08-21 10:14:35 +01:00 |
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AMDGPUMachineFunction.cpp
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[amdgpu] Add codegen support for HIP dynamic shared memory.
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2020-08-20 21:29:18 -04:00 |
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AMDGPUMachineFunction.h
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[amdgpu] Add codegen support for HIP dynamic shared memory.
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2020-08-20 21:29:18 -04:00 |
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AMDGPUMachineModuleInfo.cpp
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AMDGPUMachineModuleInfo.h
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AMDGPUMacroFusion.cpp
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AMDGPUMacroFusion.h
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AMDGPUMCInstLower.cpp
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AMDGPU: Increase branch size estimate with offset bug
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2020-10-23 10:34:24 -04:00 |
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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AMDGPUPerfHintAnalysis.cpp
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AMDGPUPerfHintAnalysis.h
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AMDGPUPostLegalizerCombiner.cpp
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AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner
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2020-11-03 09:24:50 +01:00 |
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AMDGPUPreLegalizerCombiner.cpp
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AMDGPU/GlobalISel: Mark GlobalISel classes as final
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2020-07-28 11:42:17 -04:00 |
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AMDGPUPrintfRuntimeBinding.cpp
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AMDGPUPrintfRuntimeBinding.cpp - drop unnecessary casts/dyn_casts. NFCI.
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2020-09-15 14:49:04 +01:00 |
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AMDGPUPromoteAlloca.cpp
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[NFC] Remove unused GetUnderlyingObject paramenter
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2020-07-31 02:10:03 -07:00 |
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AMDGPUPropagateAttributes.cpp
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AMDGPU: Propagate amdgpu-flat-work-group-size attributes
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2020-10-21 12:06:24 -04:00 |
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AMDGPUPTNote.h
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AMDGPURegBankCombiner.cpp
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AMDGPU/GlobalISel: Mark GlobalISel classes as final
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2020-07-28 11:42:17 -04:00 |
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AMDGPURegisterBankInfo.cpp
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[AMDGPU] Remove an unused return value. NFC.
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2020-11-10 09:15:14 +00:00 |
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AMDGPURegisterBankInfo.h
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AMDGPU/GlobalISel: Start trying to handle AGPR bank
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2020-08-06 12:39:50 -04:00 |
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AMDGPURegisterBanks.td
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AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank
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2020-07-28 16:49:55 -04:00 |
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AMDGPURewriteOutArguments.cpp
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[AA] Split up LocationSize::unknown()
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2020-11-26 18:39:55 +01:00 |
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AMDGPUSearchableTables.td
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AMDGPU: Define raw/struct variants of buffer atomic fadd
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2020-08-06 13:36:19 -04:00 |
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AMDGPUSubtarget.cpp
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Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
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2020-11-11 14:40:14 +00:00 |
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AMDGPUSubtarget.h
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[AMDGPU] Enable multi-dword flat scratch load/stores
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2020-11-12 13:38:56 -08:00 |
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AMDGPUTargetMachine.cpp
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[AMDGPU] Set the default globals address space to 1
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2020-11-20 15:46:53 +00:00 |
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AMDGPUTargetMachine.h
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[InferAddrSpace] Teach to handle assumed address space.
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2020-11-16 17:06:33 -05:00 |
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AMDGPUTargetObjectFile.cpp
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AMDGPUTargetObjectFile.h
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AMDGPUTargetTransformInfo.cpp
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[NFC][CostModel]Extend class IntrinsicCostAttributes to use ElementCount Type
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2020-12-01 11:12:51 +00:00 |
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AMDGPUTargetTransformInfo.h
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Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
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2020-11-11 14:40:14 +00:00 |
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AMDGPUUnifyDivergentExitNodes.cpp
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[AMDGPU] One more use of the new export target names. NFC.
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2020-11-13 09:44:09 +00:00 |
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AMDGPUUnifyMetadata.cpp
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Use llvm::is_contained where appropriate (NFC)
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2020-07-27 10:20:44 -07:00 |
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AMDILCFGStructurizer.cpp
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AMDKernelCodeT.h
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BUFInstructions.td
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[AMDGPU] Add default 1 glc operand to rtn atomics
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2020-11-05 10:41:59 -08:00 |
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CaymanInstructions.td
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[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
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2020-07-08 19:14:49 +01:00 |
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CMakeLists.txt
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llvmbuildectomy - replace llvm-build by plain cmake
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2020-11-13 10:35:24 +01:00 |
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DSInstructions.td
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[AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds
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2020-10-29 17:31:59 +00:00 |
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EvergreenInstructions.td
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[AMDGPU] Omit needless string concatenations. NFC.
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2020-10-28 12:56:52 +00:00 |
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EXPInstructions.td
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[AMDGPU] Separate out real exp instructions by subtarget. NFC.
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2020-11-11 17:13:40 +00:00 |
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FLATInstructions.td
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[AMDGPU] Add default 1 glc operand to rtn atomics
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2020-11-05 10:41:59 -08:00 |
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GCNDPPCombine.cpp
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AMDGPU: Rename add/sub with carry out instructions
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2020-07-16 13:16:30 -04:00 |
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GCNHazardRecognizer.cpp
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[AMDGPU] Rename pseudo S_WAITCNT_IDLE to S_WAIT_IDLE. NFC.
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2020-11-18 14:03:43 +00:00 |
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GCNHazardRecognizer.h
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[AMDGPU] Add Reset function to GCNHazardRecognizer
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2020-10-28 16:32:32 -07:00 |
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GCNILPSched.cpp
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GCNIterativeScheduler.cpp
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GCNIterativeScheduler.h
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GCNMinRegStrategy.cpp
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Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
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2020-09-21 13:33:05 +02:00 |
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GCNNSAReassign.cpp
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[NFC][MC] Use MCRegister in LiveRangeMatrix
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2020-10-12 08:54:36 -07:00 |
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GCNProcessors.td
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[AMDGPU] Add gfx1033 target
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2020-11-03 16:27:48 +00:00 |
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GCNRegBankReassign.cpp
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[AMDGPU] Resolve pseudo registers at encoding uses
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2020-11-04 12:52:32 -05:00 |
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GCNRegPressure.cpp
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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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GCNRegPressure.h
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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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GCNSchedStrategy.cpp
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[AMDGPU] Fix not rescheduling without clustering
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2020-08-07 11:15:58 -07:00 |
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GCNSchedStrategy.h
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InstCombineTables.td
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[InstCombine] Move target-specific inst combining
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2020-07-22 15:59:49 +02:00 |
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MIMGInstructions.td
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[TableGen] Add the !filter bang operator.
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2020-11-09 10:56:55 -05:00 |
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R600.td
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R600AsmPrinter.cpp
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R600AsmPrinter.h
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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R600FrameLowering.h
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[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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R600InstrFormats.td
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R600InstrInfo.cpp
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[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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R600InstrInfo.h
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Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate
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2020-10-21 11:52:47 +01:00 |
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R600Instructions.td
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[NFC] Remove unused GetUnderlyingObject paramenter
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2020-07-31 02:10:03 -07:00 |
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R600ISelLowering.cpp
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[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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R600MachineScheduler.h
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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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R600OpenCLImageTypeLoweringPass.cpp
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R600OptimizeVectorRegisters.cpp
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AMDGPU: Use Register
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2020-06-30 12:13:08 -04:00 |
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R600Packetizer.cpp
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R600Processors.td
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R600RegisterInfo.cpp
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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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R600RegisterInfo.h
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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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R600RegisterInfo.td
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R600Schedule.td
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R700Instructions.td
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SIAddIMGInit.cpp
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[AMDGPU] gfx1030 RT support
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2020-09-16 11:40:58 -07:00 |
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SIAnnotateControlFlow.cpp
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SIDefines.h
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[AMDGPU] Add a TRANS bit to TSFlags. NFC.
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2020-11-24 17:49:56 +00:00 |
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SIFixSGPRCopies.cpp
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[AMDGPU] Fix iterating in SIFixSGPRCopies
|
2020-11-04 18:43:19 +01:00 |
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SIFixVGPRCopies.cpp
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SIFoldOperands.cpp
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[AMDGPU] Use flat scratch instructions where available
|
2020-10-26 14:40:42 -07:00 |
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SIFormMemoryClauses.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
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SIFrameLowering.cpp
|
[AMDGPU] Implement flat scratch init for pal
|
2020-11-20 11:14:30 +01:00 |
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SIFrameLowering.h
|
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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SIInsertHardClauses.cpp
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[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
|
2020-06-01 22:52:34 +05:30 |
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SIInsertSkips.cpp
|
[AMDGPU] Define and use names for export targets. NFC.
|
2020-11-12 19:57:14 +00:00 |
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SIInsertWaitcnts.cpp
|
[AMDGPU] Fix and extend vccz workarounds
|
2020-11-18 15:26:06 +00:00 |
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SIInstrFormats.td
|
[AMDGPU] Add a TRANS bit to TSFlags. NFC.
|
2020-11-24 17:49:56 +00:00 |
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SIInstrInfo.cpp
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AMDGPU: Factor out large flat offset splitting
|
2020-11-13 11:22:13 -05:00 |
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SIInstrInfo.h
|
[AMDGPU] Add a TRANS bit to TSFlags. NFC.
|
2020-11-24 17:49:56 +00:00 |
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SIInstrInfo.td
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[AMDGPU] Split exp instructions out into their own tablegen file. NFC.
|
2020-11-11 17:13:40 +00:00 |
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SIInstructions.td
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[AMDGPU] Remove scratch rsrc from spill pseudos
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2020-11-12 15:23:37 -08:00 |
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SIISelLowering.cpp
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
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SIISelLowering.h
|
[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
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SILoadStoreOptimizer.cpp
|
[AMDGPU] gfx1030 RT support
|
2020-09-16 11:40:58 -07:00 |
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SILowerControlFlow.cpp
|
[AMDGPU] SILowerControlFlow::removeMBBifRedundant. Refactoring plus fix for the null MBB pointer in MF->splice
|
2020-10-30 14:46:08 +03:00 |
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SILowerI1Copies.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
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SILowerSGPRSpills.cpp
|
[AMDGPU] Add amdgpu_gfx calling convention
|
2020-11-09 16:51:44 +01:00 |
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SIMachineFunctionInfo.cpp
|
[AMDGPU] Omit buffer resource with flat scratch.
|
2020-11-09 08:05:20 -08:00 |
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SIMachineFunctionInfo.h
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
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SIMachineScheduler.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
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SIMachineScheduler.h
|
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
|
2020-09-21 13:33:05 +02:00 |
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SIMemoryLegalizer.cpp
|
[NFC][AMDGPU] Reorder SIMemoryLegalizer functions to be consistent
|
2020-10-22 05:39:18 +00:00 |
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SIModeRegister.cpp
|
[AMDGPU] Enable scheduling around FP MODE-setting instructions
|
2020-09-16 16:10:47 +01:00 |
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SIOptimizeExecMasking.cpp
|
[AMDGPU] Fix lowering of S_MOV_{B32,B64}_term
|
2020-11-10 12:16:31 +09:00 |
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SIOptimizeExecMaskingPreRA.cpp
|
[NFC] Use Register/MCRegister
|
2020-11-04 12:20:17 -08:00 |
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SIPeepholeSDWA.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
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SIPostRABundler.cpp
|
AMDGPU: Do not bundle inline asm
|
2020-06-14 13:24:50 -04:00 |
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SIPreAllocateWWMRegs.cpp
|
AMDGPU: Reorder checks
|
2020-11-02 10:21:48 -05:00 |
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SIPreEmitPeephole.cpp
|
[AMDGPU] Fix missed SI_RETURN_TO_EPILOG in pre-emit peephole
|
2020-08-13 21:52:41 +09:00 |
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SIProgramInfo.cpp
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[AMDGPU] Set rsrc1 flags for graphics shaders
|
2020-11-04 12:25:41 +01:00 |
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SIProgramInfo.h
|
[AMDGPU] Set rsrc1 flags for graphics shaders
|
2020-11-04 12:25:41 +01:00 |
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SIRegisterInfo.cpp
|
[NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister.
|
2020-12-02 15:46:38 -08:00 |
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SIRegisterInfo.h
|
[AMDGPU] Implement flat scratch init for pal
|
2020-11-20 11:14:30 +01:00 |
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SIRegisterInfo.td
|
[TableGen] Add the !filter bang operator.
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2020-11-09 10:56:55 -05:00 |
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SIRemoveShortExecBranches.cpp
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SISchedule.td
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[AMDGPU] Add XDL resource to scheduling model
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2020-09-14 13:48:54 -07:00 |
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SIShrinkInstructions.cpp
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[AMDGPU] Fix VC warning about singed/unsigned comparison. NFC.
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2020-10-26 11:55:57 -07:00 |
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SIWholeQuadMode.cpp
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[NFC] Use [MC]Register
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2020-11-09 08:37:14 -08:00 |
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SMInstructions.td
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AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
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2020-06-18 14:12:19 -04:00 |
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SOPInstructions.td
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[AMDGPU] Rename pseudo S_WAITCNT_IDLE to S_WAIT_IDLE. NFC.
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2020-11-18 14:03:43 +00:00 |
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VIInstrFormats.td
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VOP1Instructions.td
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[AMDGPU] Add a TRANS bit to TSFlags. NFC.
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2020-11-24 17:49:56 +00:00 |
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VOP2Instructions.td
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[AMDGPU] Fix double space in disassembly of SDWA instructions with vcc
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2020-10-28 21:39:39 +00:00 |
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VOP3Instructions.td
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[AMDGPU] Allow some modifiers on VOP3B instructions
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2020-10-28 21:54:14 +00:00 |
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VOP3PInstructions.td
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[AMDGPU] Set default op_sel_hi on accvgpr read/write
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2020-11-10 13:07:29 -08:00 |
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VOPCInstructions.td
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[AMDGPU] Corrected declaration of VOPC instructions with SDWA addressing mode.
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2020-11-05 11:15:50 -05:00 |
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VOPInstructions.td
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[AMDGPU] Add a TRANS bit to TSFlags. NFC.
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2020-11-24 17:49:56 +00:00 |
