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86edc13433
llvm-mirror/lib/Target/AArch64
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Francis Visoiu Mistrih 86edc13433 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).

Basically:

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed

Differential Revision: https://reviews.llvm.org/D40420

llvm-svn: 319427
2017-11-30 12:12:19 +00:00
..
AsmParser Reverted r319315 because of unused functions (due to PPR not yet being 2017-11-29 15:14:39 +00:00
Disassembler Reverted r319315 because of unused functions (due to PPR not yet being 2017-11-29 15:14:39 +00:00
InstPrinter [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support 2017-11-07 16:45:48 +00:00
MCTargetDesc [AArch64] Use dwarf exception handling on MinGW 2017-11-03 07:33:20 +00:00
TargetInfo Add backend name to Target to enable runtime info to be fed back into TableGen 2017-11-15 23:55:44 +00:00
Utils [AArch64] Add support for dllimport of values and functions 2017-10-25 07:25:18 +00:00
AArch64.h [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 2) 2017-07-18 16:14:22 +00:00
AArch64.td AArch64: Enable AES instruction fusion on Cyclone. 2017-10-17 21:46:15 +00:00
AArch64A53Fix835769.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64A57FPLoadBalancing.cpp LiveRegUnits: Rename accumulateBackward()->accumulate() 2017-07-07 03:02:17 +00:00
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64CallingConvention.h Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64CallingConvention.td AArch64: support SwiftCC properly on AAPCS64 2017-09-22 04:31:44 +00:00
AArch64CallLowering.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64CallLowering.h GlobalISel (AArch64): fix ABI at border between GPRs and SP. 2017-08-21 21:56:11 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp fix trivial typos in comments; NFC 2017-07-03 06:32:59 +00:00
AArch64CollectLOH.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64CondBrTuning.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64ConditionalCompares.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64ConditionOptimizer.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64DeadRegisterDefinitionsPass.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64ExpandPseudoInsts.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64FalkorHWPFFix.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
AArch64FastISel.cpp [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64FrameLowering.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
AArch64FrameLowering.h Move TargetFrameLowering.h to CodeGen where it's implemented 2017-11-03 22:32:11 +00:00
AArch64GenRegisterBankInfo.def [AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies 2017-11-18 04:28:56 +00:00
AArch64InstrAtomics.td [AArch64] LSE Atomics reorg - part 1 2017-08-05 04:30:55 +00:00
AArch64InstrFormats.td [globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero. 2017-10-23 18:19:24 +00:00
AArch64InstrInfo.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
AArch64InstrInfo.h Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64InstrInfo.td [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects. 2017-11-21 18:08:34 +00:00
AArch64InstructionSelector.cpp [globalisel][tablegen] Generate rule coverage and use it to identify untested rules 2017-11-16 00:46:35 +00:00
AArch64ISelDAGToDAG.cpp [AArch64] Avoid selecting XZR inline ASM memory operand 2017-07-14 21:46:16 +00:00
AArch64ISelLowering.cpp [DAG] Do MergeConsecutiveStores again before Instruction Selection 2017-11-27 15:28:15 +00:00
AArch64ISelLowering.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64LegalizerInfo.cpp Fix VS2017 narrowing conversion warning. NFCI 2017-11-28 22:32:43 +00:00
AArch64LegalizerInfo.h [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal 2017-11-28 20:21:15 +00:00
AArch64LoadStoreOptimizer.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
AArch64MachineFunctionInfo.h [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64MacroFusion.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64MacroFusion.h Recommit rL305677: [CodeGen] Add generic MacroFusion pass 2017-06-19 12:53:31 +00:00
AArch64MCInstLower.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64MCInstLower.h [COFF, ARM64] Add support for Windows ARM64 COFF format 2017-06-27 23:58:19 +00:00
AArch64PBQPRegAlloc.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
AArch64PBQPRegAlloc.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-06-01 23:25:02 +00:00
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64RedundantCopyElimination.cpp AArch64: account for possible frame index operand in compares. 2017-10-17 21:43:52 +00:00
AArch64RegisterBankInfo.cpp [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR 2017-11-18 04:28:59 +00:00
AArch64RegisterBankInfo.h [AArch64][RegisterBankInfo] Add mapping for G_FPEXT. 2017-11-02 23:38:19 +00:00
AArch64RegisterBanks.td [aarch64][globalisel] Register banks and classes should have distinct names. 2017-10-18 00:12:43 +00:00
AArch64RegisterInfo.cpp Move TargetFrameLowering.h to CodeGen where it's implemented 2017-11-03 22:32:11 +00:00
AArch64RegisterInfo.h
AArch64RegisterInfo.td Reverted r319315 because of unused functions (due to PPR not yet being 2017-11-29 15:14:39 +00:00
AArch64SchedA53.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedA57.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedFalkor.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Remove some non-existent opcodes from sched detail regexes. NFC. 2017-06-23 21:59:09 +00:00
AArch64SchedKryo.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedKryoDetails.td [AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination. 2017-06-19 21:57:42 +00:00
AArch64SchedM1.td [AArch64] Adjust the cost model for Exynos M1 and M2 2017-11-22 22:48:50 +00:00
AArch64SchedThunderX2T99.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedThunderX.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64Subtarget.cpp [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal 2017-11-28 20:21:15 +00:00
AArch64Subtarget.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZ 2017-11-07 16:58:13 +00:00
AArch64SystemOperands.td [AArch64] IDSAR6 register assembler support 2017-08-31 08:36:45 +00:00
AArch64TargetMachine.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64TargetMachine.h Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" 2017-10-12 22:57:28 +00:00
AArch64TargetObjectFile.cpp Move Object format code to lib/BinaryFormat. 2017-06-07 03:48:56 +00:00
AArch64TargetObjectFile.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64TargetTransformInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64TargetTransformInfo.h [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64VectorByElementOpt.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
CMakeLists.txt [GlobalISel] Make GlobalISel a non-optional library. 2017-08-03 21:52:25 +00:00
LLVMBuild.txt
SVEInstrFormats.td Test commit 2017-11-13 09:57:20 +00:00