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intrinsics
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[Hexagon] Add intrinsics for masked vector stores
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2017-02-22 21:23:09 +00:00 |
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loop-idiom
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[Hexagon] Add Hexagon-specific loop idiom recognition pass
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2017-01-26 21:41:10 +00:00 |
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vect
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[Hexagon] Generate extract instructions more aggressively
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2017-02-28 23:27:33 +00:00 |
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absaddr-store.ll
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absimm.ll
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adde.ll
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[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
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2017-03-09 16:29:30 +00:00 |
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addh-sext-trunc.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addh-shifted.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addh.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addr-calc-opt.ll
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[Hexagon] Improve balancing of address calculation
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2016-07-29 15:15:35 +00:00 |
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addrmode-indoff.ll
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alu64.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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always-ext.ll
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anti-dep-partial.mir
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Move .mir tests to appropriate directories
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2016-12-09 19:08:15 +00:00 |
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args.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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ashift-left-right.ll
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Atomics.ll
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avoid-predspill-calleesaved.ll
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[Hexagon] Start using regmasks on calls
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2017-02-17 22:14:51 +00:00 |
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avoid-predspill.ll
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barrier-flag.ll
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base-offset-addr.ll
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base-offset-post.ll
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bit-bitsplit-at.ll
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[Hexagon] Fixes to the bitsplit generation
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2017-03-09 22:02:14 +00:00 |
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bit-bitsplit-src.ll
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[Hexagon] Generate bitsplit instruction
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2017-03-07 23:08:35 +00:00 |
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bit-bitsplit.ll
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[Hexagon] Generate bitsplit instruction
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2017-03-07 23:08:35 +00:00 |
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bit-eval.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bit-ext-sat.ll
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[Hexagon] Handle saturations in Hexagon bit tracker
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2017-02-23 22:11:52 +00:00 |
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bit-extract-off.ll
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[Hexagon] Use correct offset when extracting from the high word
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2017-03-08 15:46:28 +00:00 |
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bit-extract.ll
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[Hexagon] Generate extract instructions more aggressively
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2017-02-28 23:27:33 +00:00 |
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bit-extractu-half.ll
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bit-gen-rseq.ll
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MachinePipeliner pass that implements Swing Modulo Scheduling
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2016-07-29 16:44:44 +00:00 |
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bit-has.ll
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[Hexagon] Check for presence before looking registers up in bit tracker
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2017-03-07 23:12:04 +00:00 |
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bit-loop-rc-mismatch.ll
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[Hexagon] Gracefully handle reg class mismatch in HexagonLoopReschedule
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2016-07-26 19:17:13 +00:00 |
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bit-loop.ll
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bit-phi.ll
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[Hexagon] Do not insert instructions before PHI nodes
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2017-03-07 14:20:19 +00:00 |
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bit-rie.ll
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[Hexagon] Rerun bit tracker on new instructions in RIE
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2016-07-26 19:08:45 +00:00 |
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bit-skip-byval.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bit-validate-reg.ll
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[Hexagon] Generate extract instructions more aggressively
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2017-02-28 23:27:33 +00:00 |
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bit-visit-flowq.ll
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[Hexagon] Clear the flow queue after visiting a single instruction
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2016-09-13 14:36:55 +00:00 |
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bitconvert-vector.ll
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[Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)
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2016-06-27 15:08:22 +00:00 |
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bitmanip.ll
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[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE
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2017-02-23 15:02:09 +00:00 |
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block-addr.ll
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[Hexagon] Early-if-convert branches that may exit the loop
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2017-03-06 17:24:04 +00:00 |
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block-ranges-nodef.ll
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branch-non-mbb.ll
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branchfolder-keep-impdef.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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BranchPredict.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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brev_ld.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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brev_st.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bugAsmHWloop.ll
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build-vector-shuffle.ll
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[Hexagon] Better handling of HVX vector lowering
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2016-09-13 21:16:07 +00:00 |
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builtin-expect.ll
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[Hexagon] Pick the right branch opcode depending on branch probabilities
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2017-03-02 21:49:49 +00:00 |
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builtin-prefetch-offset.ll
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builtin-prefetch.ll
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calling-conv-2.ll
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callr-dep-edge.ll
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cext-check.ll
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cext-valid-packet1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cext-valid-packet2.ll
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cext.ll
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cexti16.ll
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cfi-late.ll
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cfi-offset.ll
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checktabs.ll
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circ_ld.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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circ_ldd_bug.ll
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circ_ldw.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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circ_st.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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circ-load-isel.ll
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clr_set_toggle.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cmp_pred2.ll
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cmp_pred_reg.ll
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cmp_pred.ll
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cmp-extend.ll
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cmp-promote.ll
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cmp-to-genreg.ll
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cmp-to-predreg.ll
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cmp.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cmpb_pred.ll
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cmpb-eq.ll
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combine_ir.ll
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combine.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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common-gep-basic.ll
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common-gep-icm.ll
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compound.ll
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[Hexagon] Start using regmasks on calls
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2017-02-17 22:14:51 +00:00 |
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const64.ll
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const-pool-tf.ll
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[Hexagon] Improve test to check for @PCREL, only run llc, not opt -> llc.
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2016-08-16 13:10:09 +00:00 |
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constp-clb.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-combine-neg.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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constp-ctb.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-extract.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-physreg.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-rewrite-branches.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-rseq.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-vsplat.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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convert-to-dot-old.ll
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[Hexagon] Pick a dot-old instruction that matches the architecture
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2017-03-06 17:03:16 +00:00 |
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convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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copy-to-combine-dbg.ll
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[Hexagon] Check for block end when skipping debug instructions
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2016-08-24 22:36:35 +00:00 |
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csr-func-usedef.ll
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ctor.ll
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dadd.ll
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dead-store-stack.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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dmul.ll
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double.ll
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doubleconvert-ieee-rnd-near.ll
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dsub.ll
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dualstore.ll
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duplex.ll
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early-if-conversion-bug1.ll
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early-if-merge-loop.ll
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[Hexagon] Early-if-convert branches that may exit the loop
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2017-03-06 17:24:04 +00:00 |
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early-if-phi-i1.ll
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early-if-spare.ll
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early-if-vecpi.ll
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[Hexagon] Post-increment loads/stores enhancements
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2016-07-26 20:30:30 +00:00 |
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early-if-vecpred.ll
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[Hexagon] Skip blocks that define vector predicate registers in early-if
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2017-03-02 18:10:59 +00:00 |
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early-if.ll
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eh_return.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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eliminate-pred-spill.ll
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[Hexagon] HexagonMachineScheduler should account for resources
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2016-07-18 14:52:13 +00:00 |
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expand-condsets-basic.ll
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expand-condsets-dead-bad.ll
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[Hexagon] Mark dead defs as <dead> in expand-condsets
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2017-03-06 17:09:06 +00:00 |
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expand-condsets-dead-pred.ll
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[Hexagon] Mark dead defs as <dead> in expand-condsets
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2017-03-06 17:09:06 +00:00 |
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expand-condsets-def-undef.mir
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[Hexagon] Separate Hexagon subreg indices for different register classes
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2016-11-09 16:19:08 +00:00 |
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expand-condsets-extend.ll
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[Hexagon] Deal with undefs when extending live intervals
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2016-09-01 13:59:35 +00:00 |
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expand-condsets-impuse.mir
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[Hexagon] Maintain kill flags through splitting in expand-condsets
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2016-10-28 15:50:22 +00:00 |
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expand-condsets-pred-undef.ll
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expand-condsets-rm-reg.mir
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Bring back 2>&1 redirection for this test
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2017-02-22 19:16:33 +00:00 |
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expand-condsets-rm-segment.ll
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expand-condsets-same-inputs.mir
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[Hexagon] Don't expand mux instructions with both sources identical
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2016-10-31 15:45:09 +00:00 |
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expand-condsets-undef2.ll
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[Hexagon] Check for empty live interval
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2016-08-19 14:29:43 +00:00 |
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expand-condsets-undef.ll
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expand-vstorerw-undef2.ll
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[Hexagon] Remove dead defs from the live set when expanding wstores
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2017-01-18 23:11:40 +00:00 |
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expand-vstorerw-undef.ll
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[Hexagon] Handle spills of partially defined double vector registers
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2016-10-21 16:38:29 +00:00 |
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extload-combine.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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extract-basic.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fadd.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fcmp.ll
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find-loop-instr.ll
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[Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructions
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2017-02-02 19:36:37 +00:00 |
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fixed-spill-mutable.ll
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Fixed spill stack objects are mutable
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2016-08-31 13:52:17 +00:00 |
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float-amode.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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float.ll
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floatconvert-ieee-rnd-near.ll
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fminmax.ll
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[Hexagon] Improvements to handling and generation of FP instructions
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2016-08-19 13:34:31 +00:00 |
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fmul.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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frame-offset-overflow.ll
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[Hexagon] Check for offset overflow when reserving scavenging slots
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2016-08-01 17:15:30 +00:00 |
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frame.ll
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fsel.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fsub.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fusedandshift.ll
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[Hexagon] Generate extract instructions more aggressively
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2017-02-28 23:27:33 +00:00 |
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gp-plus-offset-load.ll
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gp-plus-offset-store.ll
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gp-rel.ll
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[Hexagon] Adding gp+ to the syntax of gp-relative instructions
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2017-02-06 23:18:57 +00:00 |
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hwloop1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop3.ll
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hwloop4.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop5.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop-cleanup.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop-const.ll
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hwloop-crit-edge.ll
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[LSR] Don't try and create post-inc expressions on non-rotated loops
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2016-08-15 07:53:03 +00:00 |
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hwloop-dbg.ll
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hwloop-le.ll
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hwloop-loop1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop-lt1.ll
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hwloop-lt.ll
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hwloop-missed.ll
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hwloop-ne.ll
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hwloop-noreturn-call.ll
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[Hexagon] Allow non-returning calls in hardware loops
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2016-08-11 21:14:25 +00:00 |
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hwloop-ph-deadcode.ll
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hwloop-pos-ivbump1.ll
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hwloop-preh.ll
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[Hexagon] Find speculative loop preheader in hardware loop generation
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2016-07-27 21:20:54 +00:00 |
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hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
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hwloop-wrap2.ll
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hwloop-wrap.ll
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i1_VarArg.ll
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i8_VarArg.ll
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i16_VarArg.ll
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idxload-with-zero-offset.ll
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ifcvt-diamond-bad.ll
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ifcvt-diamond-bug-2016-08-26.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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ifcvt-edge-weight.ll
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ifcvt-impuse-livein.mir
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MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
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2016-08-25 01:27:13 +00:00 |
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ifcvt-live-subreg.mir
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IfConversion: Add implicit uses for redefined regs with live subregisters
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2016-09-28 20:07:41 +00:00 |
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ifcvt-simple-bprob.ll
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[IfConversion] Only renormalize probabilities if branches are analyzable
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2017-03-06 19:12:42 +00:00 |
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indirect-br.ll
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inline-asm-hexagon.ll
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[Hexagon] Add support for proper handling of H and L constraints
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2016-07-26 17:31:02 +00:00 |
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inline-asm-i1.ll
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[Hexagon] Add RUN line to test
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2016-08-19 19:36:35 +00:00 |
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inline-asm-qv.ll
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inline-asm-vecpred128.ll
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[Hexagon] Properly handle 'q' constraint in 128-byte vector mode
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2017-03-02 17:50:24 +00:00 |
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insert4.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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insert-basic.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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is-legal-void.ll
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[Hexagon] Do not check alignment for unsized types in isLegalAddressingMode
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2016-08-03 15:06:18 +00:00 |
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isel-exti1.ll
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[Hexagon] Fix instruction selection for sign-extending i1 to i64
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2017-02-28 22:37:01 +00:00 |
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isel-i1arg-crash.ll
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[Hexagon] Fix lowering of formal arguments of type i1
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2017-03-01 17:30:10 +00:00 |
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isel-op-zext-i1.ll
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[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
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2017-03-09 16:29:30 +00:00 |
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lit.local.cfg
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livephysregs-lane-masks2.mir
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Handle non-~0 lane masks on live-in registers in LivePhysRegs
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2016-10-28 20:06:37 +00:00 |
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livephysregs-lane-masks.mir
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Handle lane masks in LivePhysRegs when adding live-ins
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2016-10-12 22:53:41 +00:00 |
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loadi1-G0.ll
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loadi1-v4-G0.ll
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loadi1-v4.ll
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loadi1.ll
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long-calls.ll
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[Hexagon] Add target feature to generate long calls
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2016-07-25 14:42:11 +00:00 |
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loop-prefetch.ll
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[Hexagon] Use loop data prefetch on Hexagon
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2016-07-22 14:22:43 +00:00 |
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lower-extract-subvector.ll
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[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
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2016-07-29 16:44:27 +00:00 |
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macint.ll
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maxd.ll
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maxh.ll
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maxud.ll
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maxuw.ll
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maxw.ll
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mem-fi-add.ll
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memcpy-likely-aligned.ll
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memops1.ll
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memops2.ll
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memops3.ll
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memops-stack.ll
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[Hexagon] Improve patterns with stack-based addressing
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2016-07-15 15:35:52 +00:00 |
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memops.ll
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[Hexagon] Improve patterns with stack-based addressing
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2016-07-15 15:35:52 +00:00 |
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mind.ll
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minu-zext-8.ll
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minu-zext-16.ll
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minud.ll
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minuw.ll
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minw.ll
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misaligned_double_vector_store_not_fast.ll
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[Hexagon] Fix test that uses -debug-only to require asserts.
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2016-07-29 21:44:33 +00:00 |
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misaligned-access.ll
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misched-top-rptracker-sync.ll
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mpy.ll
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mulhs.ll
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[Hexagon] Add pattern for 64-bit mulhs
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2016-08-08 19:24:25 +00:00 |
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mux-basic.ll
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newvaluejump2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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newvaluejump3.ll
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[Hexagon] Avoid IMPLICIT_DEFs as new-value producers
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2017-02-23 17:47:34 +00:00 |
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newvaluejump.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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newvalueSameReg.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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newvaluestore.ll
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NVJumpCmp.ll
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opt-addr-mode.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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opt-fabs.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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opt-fneg.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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opt-spill-volatile.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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packetize_cond_inst.ll
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packetize-cfi-location.ll
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[Hexagon] Insert CFI instructions before throwing calls
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2016-07-28 19:13:46 +00:00 |
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packetize-return-arg.ll
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[Hexagon] Packetize return value setup with the return instruction
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2016-08-23 16:01:01 +00:00 |
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packetize-tailcall-arg.ll
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[Hexagon] Packetize function call arguments with tail call instructions
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2016-07-14 19:30:55 +00:00 |
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peephole-kill-flags.ll
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[Hexagon] Clear kill flags from modified registers in peephole optimizer
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2016-08-04 14:17:16 +00:00 |
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peephole-op-swap.ll
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pic-jumptables.ll
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pic-local.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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pic-regusage.ll
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pic-simple.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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pic-static.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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post-inc-aa-metadata.ll
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Propagate TBAA info in SelectionDAG::getIndexedLoad
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2016-08-29 19:50:15 +00:00 |
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post-ra-kill-update.mir
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Fix machine operand traversal in ScheduleDAGInstrs::fixupKills
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2016-10-05 13:15:06 +00:00 |
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postinc-load.ll
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postinc-offset.ll
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postinc-store.ll
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pred-absolute-store.ll
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[RDF] Remove the map of reaching defs from copy propagation
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2017-03-10 22:44:24 +00:00 |
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pred-gp.ll
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pred-instrs.ll
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predicate-copy.ll
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predicate-logical.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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predicate-rcmp.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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propagate-vcombine.ll
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[Hexagon] Recognize vcombine in copy propagation
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2016-08-02 21:49:20 +00:00 |
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rdf-copy-undef2.ll
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rdf-copy.ll
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Codegen: Tail Merge: Be less aggressive with special cases.
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2016-08-10 18:36:18 +00:00 |
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rdf-dead-loop.ll
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rdf-extra-livein.ll
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[RDF] Fix liveness propagation through shadows
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2016-10-03 20:17:20 +00:00 |
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rdf-filter-defs.ll
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[RDF] Fix live def propagation through basic block
|
2016-10-05 20:08:09 +00:00 |
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rdf-ignore-undef.ll
|
[RDF] Ignore undef use operands
|
2016-09-06 17:03:13 +00:00 |
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rdf-inline-asm-fixed.ll
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rdf-inline-asm.ll
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rdf-multiple-phis-up.ll
|
[RDF] Further improve handling of multiple phis reached from shadows
|
2016-09-08 20:48:42 +00:00 |
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rdf-phi-shadows.ll
|
[RDF] Fix liveness analysis for phi nodes with shadow uses
|
2016-09-07 20:37:05 +00:00 |
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rdf-phi-up.ll
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[RDF] Switch RefMap in liveness calculation to use lane masks
|
2016-10-19 16:30:56 +00:00 |
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rdf-reset-kills.ll
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readcyclecounter.ll
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[Hexagon] Implement @llvm.readcyclecounter()
|
2017-02-22 22:28:47 +00:00 |
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reg-scavengebug-3.ll
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reg-scavenger-valid-slot.ll
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regalloc-bad-undef.mir
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[Hexagon] Separate Hexagon subreg indices for different register classes
|
2016-11-09 16:19:08 +00:00 |
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regalloc-block-overlap.ll
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Treat segment [B, E) as not overlapping block with boundaries [A, B)
|
2017-01-18 23:12:19 +00:00 |
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relax.ll
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remove_lsr.ll
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remove-endloop.ll
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restore-single-reg.ll
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ret-struct-by-val.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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runtime-stkchk.ll
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sdata-array.ll
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sdata-basic.ll
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sdr-basic.ll
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sdr-shr32.ll
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section_7275.ll
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[Hexagon] Adding gp+ to the syntax of gp-relative instructions
|
2017-02-06 23:18:57 +00:00 |
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select-instr-align.ll
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sf-min-max.ll
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[Hexagon] Add extra patterns for single-precision min/max instructions
|
2016-08-10 17:56:24 +00:00 |
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sffms.ll
|
[Hexagon] Improvements to handling and generation of FP instructions
|
2016-08-19 13:34:31 +00:00 |
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shrink-frame-basic.ll
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signed_immediates.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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simple_addend.ll
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simpletailcall.ll
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split-const32-const64.ll
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[Hexagon] Simplify the SplitConst32/64 pass
|
2016-08-10 18:05:47 +00:00 |
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stack-align1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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stack-align2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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stack-alloca1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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stack-alloca2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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static.ll
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[Hexagon] Adding gp+ to the syntax of gp-relative instructions
|
2017-02-06 23:18:57 +00:00 |
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store-shift.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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store-widen-aliased-load.ll
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store-widen-negv2.ll
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store-widen-negv.ll
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store-widen.ll
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storerd-io-over-rr.ll
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[Hexagon] Prefer _io over _rr for 64-bit store with constant offset
|
2016-08-02 18:50:05 +00:00 |
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storerinewabs.ll
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struct_args_large.ll
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struct_args.ll
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[Hexagon] Bitwise operations for insert/extract word not simplified
|
2016-07-26 18:30:11 +00:00 |
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sube.ll
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[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
|
2017-03-09 16:29:30 +00:00 |
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subi-asl.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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SUnit-boundary-prob.ll
|
[Hexagon] segv while processing SUnit with nullNodePtr
|
2016-09-17 16:21:09 +00:00 |
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swp-const-tc.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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swp-dag-phi.ll
|
MachinePipeliner pass that implements Swing Modulo Scheduling
|
2016-07-29 16:44:44 +00:00 |
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swp-epilog-phi10.ll
|
Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
|
2016-12-22 18:49:55 +00:00 |
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swp-epilog-reuse-1.ll
|
[Pipeliner] Fix an asssert due to invalid Phi in the epilog
|
2016-08-16 14:29:24 +00:00 |
|
swp-epilog-reuse.ll
|
MachinePipeliner pass that implements Swing Modulo Scheduling
|
2016-07-29 16:44:44 +00:00 |
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swp-matmul-bitext.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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swp-max.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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swp-multi-loops.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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swp-prolog-phi4.ll
|
Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
|
2016-12-22 18:49:55 +00:00 |
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swp-stages4.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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swp-stages5.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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swp-vect-dotprod.ll
|
MachinePipeliner pass that implements Swing Modulo Scheduling
|
2016-07-29 16:44:44 +00:00 |
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swp-vmult.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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swp-vsum.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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tail-call-mem-intrinsics.ll
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tail-call-trunc.ll
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tail-dup-subreg-abort.ll
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tail-dup-subreg-map.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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tailcall_fastcc_ccc.ll
|
[Hexagon] Allow tail-call optimization when mixing C and fast calling conv
|
2016-08-19 15:02:18 +00:00 |
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tfr-to-combine.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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tls_pic.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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tls_static.ll
|
Set some tests to an unknown vendor and OS
|
2016-10-03 21:58:20 +00:00 |
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two-crash.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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undo-dag-shift.ll
|
[Hexagon] Undo shift folding where it could simplify addressing mode
|
2017-02-24 23:34:24 +00:00 |
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union-1.ll
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usr-ovf-dep.ll
|
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v6vec-vprint.ll
|
[Hexagon] vector store print tracing.
|
2016-08-25 13:35:48 +00:00 |
|
v60-cur.ll
|
MachinePipeliner pass that implements Swing Modulo Scheduling
|
2016-07-29 16:44:44 +00:00 |
|
v60-vsel1.ll
|
[Hexagon] Do not expand ISD::SELECT for HVX vectors
|
2016-10-27 14:30:16 +00:00 |
|
v60Intrins.ll
|
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v60small.ll
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v60Vasr.ll
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vaddh.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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validate-offset.ll
|
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|
vassign-to-combine.ll
|
[Hexagon] Create vcombine in HexagonCopyToCombine
|
2016-08-18 14:12:34 +00:00 |
|
vdmpy-halide-test.ll
|
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
|
2016-07-29 16:44:27 +00:00 |
|
vec-pred-spill1.ll
|
|
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|
vector-align.ll
|
|
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|
vector-ext-load.ll
|
[Hexagon] Expand sext- and zextloads of vector types, not just extloads
|
2016-09-08 17:42:14 +00:00 |
|
vload-postinc-sel.ll
|
[Hexagon] Simplify (+fix) instruction selection for indexed loads/stores
|
2016-06-24 21:27:17 +00:00 |
|
vmpa-halide-test.ll
|
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
|
2016-07-29 16:44:27 +00:00 |
|
vpack_eo.ll
|
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
|
2016-07-29 16:44:27 +00:00 |
|
vselect-pseudo.ll
|
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vsplat-isel.ll
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zextloadi1.ll
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|
