..
AsmParser
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
Disassembler
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
MCTargetDesc
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
TargetInfo
Utils
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
AMDGPU.h
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
AMDGPU.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
AMDGPUAliasAnalysis.cpp
AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory
2020-05-09 16:00:08 -04:00
AMDGPUAliasAnalysis.h
Remove orphan AMDGPUAAResult::Aliases and AMDGPUAAResult::PathAliases declarations. NFC.
2020-06-25 16:00:44 +01:00
AMDGPUAlwaysInlinePass.cpp
AMDGPU: Hack out noinline on functions using LDS globals
2020-04-02 14:12:07 -04:00
AMDGPUAnnotateKernelFeatures.cpp
AMDGPU: Annotate functions that have stack objects
2020-05-19 18:51:00 -04:00
AMDGPUAnnotateUniformValues.cpp
AMDGPU: Fix not using scalar loads for global reads in shaders
2020-06-02 09:49:23 -04:00
AMDGPUArgumentUsageInfo.cpp
AMDGPU/GlobalISel: Add types to special inputs
2020-07-06 17:00:55 -04:00
AMDGPUArgumentUsageInfo.h
AMDGPU/GlobalISel: Add types to special inputs
2020-07-06 17:00:55 -04:00
AMDGPUAsmPrinter.cpp
[AMDGPU][CODEGEN] Added support of new inline assembler constraints
2020-07-02 17:20:15 +03:00
AMDGPUAsmPrinter.h
AMDGPUAtomicOptimizer.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPUCallingConv.td
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
AMDGPUCallLowering.cpp
GlobalISel: Handle EVT argument lowering correctly
2020-07-07 16:36:14 -04:00
AMDGPUCallLowering.h
[Alignment][NFC] Transition to inferAlignFromPtrInfo
2020-03-31 08:06:49 +00:00
AMDGPUCodeGenPrepare.cpp
[AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32
2020-07-08 19:14:48 +01:00
AMDGPUCombine.td
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
AMDGPUExportClustering.cpp
[AMDGPU] Strengthen export cluster ordering
2020-05-13 23:07:37 +09:00
AMDGPUExportClustering.h
[AMDGPU] Cluster shader exports
2020-05-07 19:05:38 +09:00
AMDGPUFeatures.td
AMDGPU: Change internal tracking of wave size
2020-06-01 17:55:08 -04:00
AMDGPUFixFunctionBitcasts.cpp
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUGenRegisterBankInfo.def
[AMDGPU][GlobalISel] Revise handling of wide loads in RegBankSelect
2020-05-11 18:10:16 -07:00
AMDGPUGISel.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
AMDGPUGlobalISelUtils.cpp
AMDGPUGlobalISelUtils.h
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
AMDGPUHSAMetadataStreamer.h
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
AMDGPUInline.cpp
Revert "Revert "[llvm][NFC] Cleanup uses of std::function in Inlining-related APIs""
2020-05-15 12:29:16 -07:00
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPU/GlobalISel: Change intrinsic ID for _L to _LZ opt
2020-04-01 13:03:02 -04:00
AMDGPUInstrInfo.td
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
2020-06-16 21:06:25 -04:00
AMDGPUInstructions.td
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
AMDGPUInstructionSelector.cpp
[AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot.
2020-07-13 13:35:34 +02:00
AMDGPUInstructionSelector.h
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
AMDGPUISelDAGToDAG.cpp
[SDAG] Add new AssertAlign ISD node.
2020-06-23 00:51:11 -04:00
AMDGPUISelLowering.cpp
[AMDGPU] Fix typos in performCtlz_CttzCombine()
2020-07-14 10:18:18 +01:00
AMDGPUISelLowering.h
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
2020-06-16 21:06:25 -04:00
AMDGPULegalizerInfo.cpp
GlobalISel: Implement widenScalar for saturating add/sub
2020-07-13 14:46:40 -04:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Legalize 64-bit G_SDIV/G_SREM
2020-06-24 11:39:45 -04:00
AMDGPULibCalls.cpp
[Alignment][NFC] Use proper getter to retrieve alignment from ConstantInt and ConstantSDNode
2020-07-03 08:06:43 +00:00
AMDGPULibFunc.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPULibFunc.h
AMDGPULibFunc - fix include order. NFC.
2020-05-24 13:25:59 +01:00
AMDGPULowerIntrinsics.cpp
AMDGPULowerKernelArguments.cpp
[Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment
2020-07-01 14:31:56 +00:00
AMDGPULowerKernelAttributes.cpp
AMDGPUMachineCFGStructurizer.cpp
AMDGPUMachineFunction.cpp
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
AMDGPUMachineFunction.h
Remove GlobalValue::getAlignment().
2020-06-23 19:13:42 -07:00
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h
AMDGPUMacroFusion.cpp
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
2020-03-11 17:59:21 +00:00
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp
AMDGPUOpenCLEnqueuedBlockLowering.cpp
Avoid SmallString.h include in MD5.h, NFC
2020-02-26 09:10:24 -08:00
AMDGPUPerfHintAnalysis.cpp
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUPerfHintAnalysis.h
AMDGPUPostLegalizerCombiner.cpp
AMDGPU/GlobalISel: Fix asserts on non-s32 sitofp/uitofp sources
2020-06-23 10:00:35 -04:00
AMDGPUPreLegalizerCombiner.cpp
[gicombiner] Allow generated combiners to store additional members
2020-06-16 14:47:04 -07:00
AMDGPUPrintfRuntimeBinding.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPUPromoteAlloca.cpp
[AMDGPU] Limit promote alloca to vector with VGPR budget
2020-07-01 15:57:24 -07:00
AMDGPUPropagateAttributes.cpp
[AMDGPU] Propagate amdgpu-waves-per-eu to callees
2020-03-26 14:43:44 -07:00
AMDGPUPTNote.h
AMDGPURegBankCombiner.cpp
[gicombiner] Allow generated combiners to store additional members
2020-06-16 14:47:04 -07:00
AMDGPURegisterBankInfo.cpp
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
AMDGPURegisterBankInfo.h
AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
2020-06-15 11:33:16 -04:00
AMDGPURegisterBanks.td
[AMDGPU] Define AGPR subregs
2020-04-28 15:30:43 -07:00
AMDGPURewriteOutArguments.cpp
[SVE] Remove usages of VectorType::getNumElements() from AMDGPU
2020-05-13 15:57:55 -07:00
AMDGPUSearchableTables.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
AMDGPUSubtarget.cpp
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
AMDGPUSubtarget.h
AMDGPU: Don't pass MachineFunction if only the IR Function is used
2020-06-18 11:06:46 -04:00
AMDGPUTargetMachine.cpp
[AMDGPU] Move LowerSwitch pass to CodeGenPrepare.
2020-07-11 16:33:38 +05:30
AMDGPUTargetMachine.h
AMDGPU: Fix wrong null value for private address space
2020-05-26 16:35:13 -04:00
AMDGPUTargetObjectFile.cpp
AMDGPUTargetObjectFile.h
AMDGPUTargetObjectFile.h - remove unnecessary includes. NFC.
2020-05-24 13:57:02 +01:00
AMDGPUTargetTransformInfo.cpp
[NFC] Separate Peeling Properties into its own struct (re-land after minor fix)
2020-07-10 18:39:30 +00:00
AMDGPUTargetTransformInfo.h
[NFC] Separate Peeling Properties into its own struct (re-land after minor fix)
2020-07-10 18:39:30 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
DomTree: Remove getRoots() accessor
2020-07-06 21:58:11 +02:00
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
BUFInstructions.td
[AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping
2020-07-10 11:32:32 +02:00
CaymanInstructions.td
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
CMakeLists.txt
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
DSInstructions.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
EvergreenInstructions.td
[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #
2020-04-25 16:26:45 -07:00
FLATInstructions.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
GCNDPPCombine.cpp
[AMDGPU] Don't combine DPP if DPP register is used more than once per instruction
2020-07-03 15:08:26 +03:00
GCNHazardRecognizer.cpp
[AMDGPU] Don't implement GCNHazardRecognizer::PreEmitNoops(SUnit *)
2020-05-06 16:11:19 +01:00
GCNHazardRecognizer.h
[AMDGPU] Don't implement GCNHazardRecognizer::PreEmitNoops(SUnit *)
2020-05-06 16:11:19 +01:00
GCNILPSched.cpp
GCNIterativeScheduler.cpp
GCNIterativeScheduler.h
GCNMinRegStrategy.cpp
SmallPtrSet::find -> SmallPtrSet::count
2020-06-07 22:38:08 +02:00
GCNNSAReassign.cpp
GCNProcessors.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
GCNRegBankReassign.cpp
[AMDGPU] Use std::pair to return two values. NFC.
2020-06-26 11:47:12 +01:00
GCNRegPressure.cpp
GCNRegPressure.h
Upgrade some instances of std::sort to llvm::sort. NFC.
2020-03-28 19:23:29 +01:00
GCNSchedStrategy.cpp
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
GCNSchedStrategy.h
LLVMBuild.txt
MIMGInstructions.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
R600.td
R600AsmPrinter.cpp
[MC] Add MCStreamer::emitInt{8,16,32,64}
2020-02-29 09:40:21 -08:00
R600AsmPrinter.h
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
[AMDGPU] Make use of divideCeil. NFC.
2020-03-26 16:11:35 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600FrameLowering.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600FrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600InstrFormats.td
R600InstrInfo.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600InstrInfo.h
R600Instructions.td
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
R600ISelLowering.cpp
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OpenCLImageTypeLoweringPass.cpp
R600OptimizeVectorRegisters.cpp
AMDGPU: Use Register
2020-06-30 12:13:08 -04:00
R600Packetizer.cpp
R600Processors.td
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R700Instructions.td
SIAddIMGInit.cpp
SIAnnotateControlFlow.cpp
SIDefines.h
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
SIFixSGPRCopies.cpp
[AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate
2020-05-28 19:25:51 +03:00
SIFixupVectorISel.cpp
SIFixVGPRCopies.cpp
SIFoldOperands.cpp
AMDGPU: Clear subreg when folding immediate copies
2020-07-01 13:59:13 -04:00
SIFormMemoryClauses.cpp
SIFrameLowering.cpp
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
SIFrameLowering.h
For PAL, make sure Scratch Buffer Descriptor do not clobber GIT pointer
2020-05-06 10:31:15 -04:00
SIInsertHardClauses.cpp
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
2020-06-01 22:52:34 +05:30
SIInsertSkips.cpp
[AMDGPU] Insert PS early exit at end of control flow
2020-07-03 14:04:34 +09:00
SIInsertWaitcnts.cpp
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
2020-06-17 12:41:03 -04:00
SIInstrFormats.td
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
SIInstrInfo.cpp
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
SIInstrInfo.h
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
SIInstrInfo.td
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
SIInstructions.td
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
SIISelLowering.cpp
[NFC] Change isFPPredicate comparison to ignore lower bound
2020-07-10 11:57:20 +01:00
SIISelLowering.h
[AMDGPU] Tweak getTypeLegalizationCost()
2020-07-06 14:07:48 -07:00
SILoadStoreOptimizer.cpp
SILoadStoreOptimizer: add support for GFX10 image instructions
2020-07-08 19:15:46 +01:00
SILowerControlFlow.cpp
[AMDGPU] Insert PS early exit at end of control flow
2020-07-03 14:04:34 +09:00
SILowerI1Copies.cpp
SILowerSGPRSpills.cpp
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
SIMachineFunctionInfo.cpp
[AMDGPU] Spill more than wavesize CSR SGPRs
2020-07-01 07:40:47 +00:00
SIMachineFunctionInfo.h
AMDGPU/GlobalISel: Add types to special inputs
2020-07-06 17:00:55 -04:00
SIMachineScheduler.cpp
SIMachineScheduler.h
SIMemoryLegalizer.cpp
[AMDGPU] Skip generating cache invalidating instructions on AMDPAL
2020-04-24 13:53:44 +02:00
SIModeRegister.cpp
[AMDGPU] Avoid redundant mode register writes
2020-06-24 14:11:29 +01:00
SIOptimizeExecMasking.cpp
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
SIPeepholeSDWA.cpp
AMDGPU: Fix dropping MI flags when rewriting instructions
2020-05-27 13:27:06 -04:00
SIPostRABundler.cpp
AMDGPU: Do not bundle inline asm
2020-06-14 13:24:50 -04:00
SIPreAllocateWWMRegs.cpp
SIPreEmitPeephole.cpp
[AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips.
2020-06-29 20:41:53 +05:30
SIProgramInfo.h
SIRegisterInfo.cpp
AMDGPU: Use Register
2020-06-30 12:13:08 -04:00
SIRegisterInfo.h
[NFC] Move getAll{S,V}GPR{32,128} methods to SIFrameLowering
2020-06-17 12:08:09 -04:00
SIRegisterInfo.td
AMDGPU: Define mode register
2020-05-23 13:24:42 -04:00
SIRemoveShortExecBranches.cpp
SISchedule.td
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
SIShrinkInstructions.cpp
[AMDGPU] Avoid using s_cmpk when src0 is not register
2020-07-14 09:05:53 +01:00
SIWholeQuadMode.cpp
[AMDGPU] Update more live intervals in SIWholeQuadMode
2020-06-22 13:50:15 +01:00
SMInstructions.td
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
SOPInstructions.td
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
VIInstrFormats.td
VOP1Instructions.td
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
VOP2Instructions.td
AMDGPU: Don't use 16-bit FP inline constants in integer operands
2020-06-17 19:14:10 -04:00
VOP3Instructions.td
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
2020-06-16 21:06:25 -04:00
VOP3PInstructions.td
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
VOPCInstructions.td
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
VOPInstructions.td
AMDGPU: Set mayRaiseFPException
2020-06-04 17:35:27 -04:00
