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llvm-mirror/test/CodeGen/Hexagon
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Sanjay Patel a3c6b40b1a [DAGCombiner] add missing folds for scalar select of {-1,0,1} 
The motivation for filling out these select-of-constants cases goes back to D24480, 
where we discussed removing an IR fold from add(zext) --> select. And that goes back to:
https://reviews.llvm.org/rL75531
https://reviews.llvm.org/rL159230

The idea is that we should always canonicalize patterns like this to a select-of-constants 
in IR because that's the smallest IR and the best for value tracking. Note that we currently 
do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in 
this patch already exist in InstCombine today:
https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151

As this patch shows, most targets generate better machine code for simple ext/add/not ops 
rather than a select of constants. So the follow-up steps to make this less of a patchwork 
of special-case folds and missing IR canonicalization:

1. Have DAGCombiner convert any select of constants into ext/add/not ops.
2  Have InstCombine canonicalize in the other direction (create more selects).

Differential Revision: https://reviews.llvm.org/D30180

llvm-svn: 296137
2017-02-24 17:17:33 +00:00
..
intrinsics [Hexagon] Add intrinsics for masked vector stores 2017-02-22 21:23:09 +00:00
loop-idiom [Hexagon] Add Hexagon-specific loop idiom recognition pass 2017-01-26 21:41:10 +00:00
vect [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
absaddr-store.ll [Hexagon] Fix printing the address operand of S2_storerinewabs 2016-04-19 20:20:33 +00:00
absimm.ll
adde.ll [DAGCombiner] add missing folds for scalar select of {-1,0,1} 2017-02-24 17:17:33 +00:00
addh-sext-trunc.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
addh-shifted.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
addh.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
addr-calc-opt.ll [Hexagon] Improve balancing of address calculation 2016-07-29 15:15:35 +00:00
addrmode-indoff.ll
alu64.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
always-ext.ll
anti-dep-partial.mir Move .mir tests to appropriate directories 2016-12-09 19:08:15 +00:00
args.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
ashift-left-right.ll
Atomics.ll [Hexagon] Handle expansion of cmpxchg 2016-06-22 16:07:10 +00:00
avoid-predspill-calleesaved.ll [Hexagon] Start using regmasks on calls 2017-02-17 22:14:51 +00:00
avoid-predspill.ll
barrier-flag.ll
base-offset-addr.ll
base-offset-post.ll
bit-eval.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
bit-ext-sat.ll [Hexagon] Handle saturations in Hexagon bit tracker 2017-02-23 22:11:52 +00:00
bit-extractu-half.ll
bit-gen-rseq.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
bit-loop-rc-mismatch.ll [Hexagon] Gracefully handle reg class mismatch in HexagonLoopReschedule 2016-07-26 19:17:13 +00:00
bit-loop.ll
bit-phi.ll
bit-rie.ll [Hexagon] Rerun bit tracker on new instructions in RIE 2016-07-26 19:08:45 +00:00
bit-skip-byval.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
bit-validate-reg.ll [Hexagon] Validate register class when doing bit simplification 2016-08-04 17:56:19 +00:00
bit-visit-flowq.ll [Hexagon] Clear the flow queue after visiting a single instruction 2016-09-13 14:36:55 +00:00
bitconvert-vector.ll [Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1) 2016-06-27 15:08:22 +00:00
bitmanip.ll [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE 2017-02-23 15:02:09 +00:00
block-addr.ll [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumpr 2016-08-19 14:04:45 +00:00
block-ranges-nodef.ll [Hexagon] Properly close live range in HexagonBlockRanges ---add testcase 2016-04-22 17:30:13 +00:00
branch-non-mbb.ll
branchfolder-keep-impdef.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
BranchPredict.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
brev_ld.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
brev_st.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
bugAsmHWloop.ll
build-vector-shuffle.ll [Hexagon] Better handling of HVX vector lowering 2016-09-13 21:16:07 +00:00
builtin-prefetch-offset.ll
builtin-prefetch.ll
calling-conv-2.ll
callr-dep-edge.ll [ScheduleDAG] Make sure to process all def operands before any use operands 2016-05-10 16:50:30 +00:00
cext-check.ll [Hexagon] Simplify HexagonInstrInfo::isPredicable 2016-05-16 16:56:10 +00:00
cext-valid-packet1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
cext-valid-packet2.ll
cext.ll
cexti16.ll
cfi-late.ll [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
cfi-offset.ll [Hexagon] Use offsets relative to FP+8 in .cfi_offset instructions 2016-05-11 14:53:07 +00:00
checktabs.ll
circ_ld.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
circ_ldd_bug.ll
circ_ldw.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
circ_st.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
circ-load-isel.ll [Hexagon] Remove dead nodes from SelectionDAG to avoid cycles 2016-05-13 18:48:15 +00:00
clr_set_toggle.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
cmp_pred2.ll
cmp_pred_reg.ll
cmp_pred.ll
cmp-extend.ll
cmp-promote.ll
cmp-to-genreg.ll
cmp-to-predreg.ll
cmp.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
cmpb_pred.ll
cmpb-eq.ll
combine_ir.ll
combine.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
common-gep-basic.ll
common-gep-icm.ll
compound.ll [Hexagon] Start using regmasks on calls 2017-02-17 22:14:51 +00:00
const64.ll
const-pool-tf.ll [Hexagon] Improve test to check for @PCREL, only run llc, not opt -> llc. 2016-08-16 13:10:09 +00:00
constp-clb.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-combine-neg.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
constp-ctb.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-extract.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-physreg.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-rewrite-branches.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-rseq.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-vsplat.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
convertdptoint.ll
convertdptoll.ll
convertsptoint.ll
convertsptoll.ll
copy-to-combine-dbg.ll [Hexagon] Check for block end when skipping debug instructions 2016-08-24 22:36:35 +00:00
csr-func-usedef.ll [Hexagon] Register save/restore functions do not follow regular conventions 2016-04-25 17:49:44 +00:00
ctor.ll
dadd.ll
dead-store-stack.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
dmul.ll
double.ll
doubleconvert-ieee-rnd-near.ll
dsub.ll
dualstore.ll
duplex.ll
early-if-conversion-bug1.ll
early-if-phi-i1.ll
early-if-spare.ll
early-if-vecpi.ll [Hexagon] Post-increment loads/stores enhancements 2016-07-26 20:30:30 +00:00
early-if.ll
eh_return.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
eliminate-pred-spill.ll [Hexagon] HexagonMachineScheduler should account for resources 2016-07-18 14:52:13 +00:00
expand-condsets-basic.ll
expand-condsets-def-undef.mir [Hexagon] Separate Hexagon subreg indices for different register classes 2016-11-09 16:19:08 +00:00
expand-condsets-extend.ll [Hexagon] Deal with undefs when extending live intervals 2016-09-01 13:59:35 +00:00
expand-condsets-impuse.mir [Hexagon] Maintain kill flags through splitting in expand-condsets 2016-10-28 15:50:22 +00:00
expand-condsets-pred-undef.ll [Hexagon] Teach mux expansion how to deal with undef predicates 2016-04-22 16:47:01 +00:00
expand-condsets-rm-reg.mir Bring back 2>&1 redirection for this test 2017-02-22 19:16:33 +00:00
expand-condsets-rm-segment.ll
expand-condsets-same-inputs.mir [Hexagon] Don't expand mux instructions with both sources identical 2016-10-31 15:45:09 +00:00
expand-condsets-undef2.ll [Hexagon] Check for empty live interval 2016-08-19 14:29:43 +00:00
expand-condsets-undef.ll
expand-vstorerw-undef2.ll [Hexagon] Remove dead defs from the live set when expanding wstores 2017-01-18 23:11:40 +00:00
expand-vstorerw-undef.ll [Hexagon] Handle spills of partially defined double vector registers 2016-10-21 16:38:29 +00:00
extload-combine.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
extract-basic.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
fadd.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
fcmp.ll
find-loop-instr.ll [Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructions 2017-02-02 19:36:37 +00:00
fixed-spill-mutable.ll Fixed spill stack objects are mutable 2016-08-31 13:52:17 +00:00
float-amode.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
float.ll
floatconvert-ieee-rnd-near.ll
fminmax.ll [Hexagon] Improvements to handling and generation of FP instructions 2016-08-19 13:34:31 +00:00
fmul.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
frame-offset-overflow.ll [Hexagon] Check for offset overflow when reserving scavenging slots 2016-08-01 17:15:30 +00:00
frame.ll
fsel.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
fsub.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
fusedandshift.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll [Hexagon] Adding gp+ to the syntax of gp-relative instructions 2017-02-06 23:18:57 +00:00
hwloop1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop2.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop3.ll
hwloop4.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop5.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop-cleanup.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop-const.ll
hwloop-crit-edge.ll [LSR] Don't try and create post-inc expressions on non-rotated loops 2016-08-15 07:53:03 +00:00
hwloop-dbg.ll [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
hwloop-le.ll
hwloop-loop1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop-lt1.ll
hwloop-lt.ll
hwloop-missed.ll
hwloop-ne.ll
hwloop-noreturn-call.ll [Hexagon] Allow non-returning calls in hardware loops 2016-08-11 21:14:25 +00:00
hwloop-ph-deadcode.ll
hwloop-pos-ivbump1.ll
hwloop-preh.ll [Hexagon] Find speculative loop preheader in hardware loop generation 2016-07-27 21:20:54 +00:00
hwloop-preheader.ll
hwloop-range.ll
hwloop-recursion.ll
hwloop-wrap2.ll
hwloop-wrap.ll
i1_VarArg.ll
i8_VarArg.ll
i16_VarArg.ll
idxload-with-zero-offset.ll
ifcvt-diamond-bad.ll
ifcvt-diamond-bug-2016-08-26.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
ifcvt-edge-weight.ll
ifcvt-impuse-livein.mir MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
ifcvt-live-subreg.mir IfConversion: Add implicit uses for redefined regs with live subregisters 2016-09-28 20:07:41 +00:00
indirect-br.ll
inline-asm-hexagon.ll [Hexagon] Add support for proper handling of H and L constraints 2016-07-26 17:31:02 +00:00
inline-asm-i1.ll [Hexagon] Add RUN line to test 2016-08-19 19:36:35 +00:00
inline-asm-qv.ll [Hexagon] Recognize "q" and "v" in inline-asm as register constraints 2016-05-18 14:34:51 +00:00
insert4.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
insert-basic.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
is-legal-void.ll [Hexagon] Do not check alignment for unsized types in isLegalAddressingMode 2016-08-03 15:06:18 +00:00
lit.local.cfg
livephysregs-lane-masks2.mir Handle non-~0 lane masks on live-in registers in LivePhysRegs 2016-10-28 20:06:37 +00:00
livephysregs-lane-masks.mir Handle lane masks in LivePhysRegs when adding live-ins 2016-10-12 22:53:41 +00:00
loadi1-G0.ll
loadi1-v4-G0.ll
loadi1-v4.ll
loadi1.ll
long-calls.ll [Hexagon] Add target feature to generate long calls 2016-07-25 14:42:11 +00:00
loop-prefetch.ll [Hexagon] Use loop data prefetch on Hexagon 2016-07-22 14:22:43 +00:00
lower-extract-subvector.ll [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX 2016-07-29 16:44:27 +00:00
macint.ll
maxd.ll
maxh.ll
maxud.ll
maxuw.ll
maxw.ll
mem-fi-add.ll
memcpy-likely-aligned.ll
memops1.ll
memops2.ll
memops3.ll
memops-stack.ll [Hexagon] Improve patterns with stack-based addressing 2016-07-15 15:35:52 +00:00
memops.ll [Hexagon] Improve patterns with stack-based addressing 2016-07-15 15:35:52 +00:00
mind.ll
minu-zext-8.ll
minu-zext-16.ll
minud.ll
minuw.ll
minw.ll
misaligned_double_vector_store_not_fast.ll [Hexagon] Fix test that uses -debug-only to require asserts. 2016-07-29 21:44:33 +00:00
misaligned-access.ll
misched-top-rptracker-sync.ll Reset the TopRPTracker's position in ScheduleDAGMILive::initQueues 2016-04-28 19:17:44 +00:00
mpy.ll
mulhs.ll [Hexagon] Add pattern for 64-bit mulhs 2016-08-08 19:24:25 +00:00
mux-basic.ll
newvaluejump2.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
newvaluejump3.ll [Hexagon] Avoid IMPLICIT_DEFs as new-value producers 2017-02-23 17:47:34 +00:00
newvaluejump.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
newvalueSameReg.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
newvaluestore.ll [Hexagon] Enable the post-RA scheduler 2016-05-26 19:44:28 +00:00
NVJumpCmp.ll
opt-addr-mode.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
opt-fabs.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
opt-fneg.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
opt-spill-volatile.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
packetize_cond_inst.ll
packetize-cfi-location.ll [Hexagon] Insert CFI instructions before throwing calls 2016-07-28 19:13:46 +00:00
packetize-return-arg.ll [Hexagon] Packetize return value setup with the return instruction 2016-08-23 16:01:01 +00:00
packetize-tailcall-arg.ll [Hexagon] Packetize function call arguments with tail call instructions 2016-07-14 19:30:55 +00:00
peephole-kill-flags.ll [Hexagon] Clear kill flags from modified registers in peephole optimizer 2016-08-04 14:17:16 +00:00
peephole-op-swap.ll [Hexagon] Fix operand swapping in HexagonPeephole 2016-04-19 21:36:24 +00:00
pic-jumptables.ll
pic-local.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
pic-regusage.ll
pic-simple.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
pic-static.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
post-inc-aa-metadata.ll Propagate TBAA info in SelectionDAG::getIndexedLoad 2016-08-29 19:50:15 +00:00
post-ra-kill-update.mir Fix machine operand traversal in ScheduleDAGInstrs::fixupKills 2016-10-05 13:15:06 +00:00
postinc-load.ll
postinc-offset.ll
postinc-store.ll
pred-absolute-store.ll
pred-gp.ll
pred-instrs.ll
predicate-copy.ll
predicate-logical.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
predicate-rcmp.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
propagate-vcombine.ll [Hexagon] Recognize vcombine in copy propagation 2016-08-02 21:49:20 +00:00
rdf-copy-undef2.ll [RDF] Handle undefined registers in RDF copy propagation 2016-04-28 15:09:19 +00:00
rdf-copy.ll Codegen: Tail Merge: Be less aggressive with special cases. 2016-08-10 18:36:18 +00:00
rdf-dead-loop.ll
rdf-extra-livein.ll [RDF] Fix liveness propagation through shadows 2016-10-03 20:17:20 +00:00
rdf-filter-defs.ll [RDF] Fix live def propagation through basic block 2016-10-05 20:08:09 +00:00
rdf-ignore-undef.ll [RDF] Ignore undef use operands 2016-09-06 17:03:13 +00:00
rdf-inline-asm-fixed.ll [RDF] Improve handling of inline-asm 2016-04-28 20:33:33 +00:00
rdf-inline-asm.ll [RDF] Improve handling of inline-asm 2016-04-28 20:33:33 +00:00
rdf-multiple-phis-up.ll [RDF] Further improve handling of multiple phis reached from shadows 2016-09-08 20:48:42 +00:00
rdf-phi-shadows.ll [RDF] Fix liveness analysis for phi nodes with shadow uses 2016-09-07 20:37:05 +00:00
rdf-phi-up.ll [RDF] Switch RefMap in liveness calculation to use lane masks 2016-10-19 16:30:56 +00:00
rdf-reset-kills.ll [RDF] Consider register as live if any alias is live 2016-04-20 14:33:23 +00:00
readcyclecounter.ll [Hexagon] Implement @llvm.readcyclecounter() 2017-02-22 22:28:47 +00:00
reg-scavengebug-3.ll
reg-scavenger-valid-slot.ll When looking for a spill slot in reg scavenger, find one that matches RC 2016-05-18 18:16:00 +00:00
regalloc-bad-undef.mir [Hexagon] Separate Hexagon subreg indices for different register classes 2016-11-09 16:19:08 +00:00
regalloc-block-overlap.ll Treat segment [B, E) as not overlapping block with boundaries [A, B) 2017-01-18 23:12:19 +00:00
relax.ll Revert r265817 2016-04-08 18:15:37 +00:00
remove_lsr.ll
remove-endloop.ll
restore-single-reg.ll [Hexagon] Only use restore functions for single register at -Oz 2016-03-28 14:52:21 +00:00
ret-struct-by-val.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
runtime-stkchk.ll
sdata-array.ll [Hexagon] Expand handling of the small-data/bss section 2016-04-21 18:56:45 +00:00
sdata-basic.ll [Hexagon] Expand handling of the small-data/bss section 2016-04-21 18:56:45 +00:00
sdr-basic.ll
sdr-shr32.ll
section_7275.ll [Hexagon] Adding gp+ to the syntax of gp-relative instructions 2017-02-06 23:18:57 +00:00
select-instr-align.ll [Hexagon] Improve handling of unaligned vector loads and stores 2016-03-28 15:43:03 +00:00
sf-min-max.ll [Hexagon] Add extra patterns for single-precision min/max instructions 2016-08-10 17:56:24 +00:00
sffms.ll [Hexagon] Improvements to handling and generation of FP instructions 2016-08-19 13:34:31 +00:00
shrink-frame-basic.ll
signed_immediates.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
simple_addend.ll
simpletailcall.ll
split-const32-const64.ll [Hexagon] Simplify the SplitConst32/64 pass 2016-08-10 18:05:47 +00:00
stack-align1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
stack-align2.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
stack-alloca1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
stack-alloca2.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
static.ll [Hexagon] Adding gp+ to the syntax of gp-relative instructions 2017-02-06 23:18:57 +00:00
store-shift.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
store-widen-aliased-load.ll
store-widen-negv2.ll
store-widen-negv.ll
store-widen.ll
storerd-io-over-rr.ll [Hexagon] Prefer _io over _rr for 64-bit store with constant offset 2016-08-02 18:50:05 +00:00
storerinewabs.ll [Hexagon] Fix printing the address operand of S2_storerinewabs 2016-04-19 20:20:33 +00:00
struct_args_large.ll
struct_args.ll [Hexagon] Bitwise operations for insert/extract word not simplified 2016-07-26 18:30:11 +00:00
sube.ll [DAGCombiner] add missing folds for scalar select of {-1,0,1} 2017-02-24 17:17:33 +00:00
subi-asl.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
SUnit-boundary-prob.ll [Hexagon] segv while processing SUnit with nullNodePtr 2016-09-17 16:21:09 +00:00
swp-const-tc.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-dag-phi.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
swp-epilog-phi10.ll Fix two bugs in the pipeliner in renaming phis in the prolog and epilog 2016-12-22 18:49:55 +00:00
swp-epilog-reuse-1.ll [Pipeliner] Fix an asssert due to invalid Phi in the epilog 2016-08-16 14:29:24 +00:00
swp-epilog-reuse.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
swp-matmul-bitext.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-max.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-multi-loops.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-prolog-phi4.ll Fix two bugs in the pipeliner in renaming phis in the prolog and epilog 2016-12-22 18:49:55 +00:00
swp-stages4.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-stages5.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-vect-dotprod.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
swp-vmult.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-vsum.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
tail-call-mem-intrinsics.ll
tail-call-trunc.ll
tail-dup-subreg-abort.ll
tail-dup-subreg-map.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
tailcall_fastcc_ccc.ll [Hexagon] Allow tail-call optimization when mixing C and fast calling conv 2016-08-19 15:02:18 +00:00
tfr-to-combine.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
tls_pic.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
tls_static.ll Set some tests to an unknown vendor and OS 2016-10-03 21:58:20 +00:00
two-crash.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
union-1.ll
usr-ovf-dep.ll
v6vec-vprint.ll [Hexagon] vector store print tracing. 2016-08-25 13:35:48 +00:00
v60-cur.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
v60-vsel1.ll [Hexagon] Do not expand ISD::SELECT for HVX vectors 2016-10-27 14:30:16 +00:00
v60Intrins.ll [Hexagon] Enable the post-RA scheduler 2016-05-26 19:44:28 +00:00
v60small.ll
v60Vasr.ll
vaddh.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
validate-offset.ll
vassign-to-combine.ll [Hexagon] Create vcombine in HexagonCopyToCombine 2016-08-18 14:12:34 +00:00
vdmpy-halide-test.ll [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX 2016-07-29 16:44:27 +00:00
vec-pred-spill1.ll
vector-align.ll
vector-ext-load.ll [Hexagon] Expand sext- and zextloads of vector types, not just extloads 2016-09-08 17:42:14 +00:00
vload-postinc-sel.ll [Hexagon] Simplify (+fix) instruction selection for indexed loads/stores 2016-06-24 21:27:17 +00:00
vmpa-halide-test.ll [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX 2016-07-29 16:44:27 +00:00
vpack_eo.ll [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX 2016-07-29 16:44:27 +00:00
vselect-pseudo.ll [Hexagon] Expand VSelect pseudo instructions 2016-05-12 19:16:02 +00:00
vsplat-isel.ll [Hexagon] Properly handle instruction selection of vsplat intrinsics 2016-05-12 17:21:40 +00:00
zextloadi1.ll [Hexagon] Optimize addressing modes for load/store 2016-04-29 15:49:13 +00:00