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llvm-mirror/lib/Target/X86/X86InstrInfo.td

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refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 07:32:15 +02:00
//===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
Added LLVM copyright header. llvm-svn: 9321
2003-10-21 17:17:13 +02:00
//
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-29 21:36:04 +01:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Added LLVM copyright header. llvm-svn: 9321
2003-10-21 17:17:13 +02:00
//
//===----------------------------------------------------------------------===//
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
//
// This file describes the X86 instruction set, defining the instructions, and
// properties of the instructions which are needed for code generation, machine
// code emission, and analysis.
//
//===----------------------------------------------------------------------===//
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
//===----------------------------------------------------------------------===//
// X86 specific DAG Nodes.
//
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
def SDTIntShiftDOp: SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
SDTCisInt<0>, SDTCisInt<3>]>;
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def SDTX86Cmov : SDTypeProfile<1, 4,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. llvm-svn: 66058
2009-03-04 20:44:21 +01:00
// Unary and binary operator instructions that set EFLAGS as a side-effect.
Switch SDTUnaryArithWithFlags to being modeled as a two-result ISD node. The only change in the generated isel code are comments like: < // Src: (X86dec_flag:i16 GR16:i16:$src) --- > // Src: (X86dec_flag:i16:i32 GR16:i16:$src) because now it knows that X86dec_flag returns both an i16 (for the result) and an i32 (for EFLAGS) in this case. Wewt. llvm-svn: 99369
2010-03-24 01:47:47 +01:00
def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
[SDTCisInt<0>, SDTCisVT<1, i32>]>;
switch SDTBinaryArithWithFlags to be a multiple-result node as well. llvm-svn: 99370
2010-03-24 01:49:29 +01:00
def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
[SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisInt<0>, SDTCisVT<1, i32>]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def SDTX86BrCond : SDTypeProfile<0, 3,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
[SDTCisVT<0, OtherVT>,
SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def SDTX86SetCC : SDTypeProfile<1, 2,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
[SDTCisVT<0, i8>,
SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Re-enable 91381 with fixes. llvm-svn: 91489
2009-12-16 01:53:11 +01:00
def SDTX86SetCC_C : SDTypeProfile<1, 2,
[SDTCisInt<0>,
SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
* Added support for X86 RET with an additional operand to specify number of bytes to pop off stack. * Added support for X86 SETCC. llvm-svn: 24917
2005-12-21 21:21:51 +01:00
all but CAS working on x86 llvm-svn: 47798
2008-03-01 22:52:34 +01:00
def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
SDTCisVT<2, i8>]>;
64bit CAS on 32bit x86. llvm-svn: 47929
2008-03-05 02:15:49 +01:00
def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
all but CAS working on x86 llvm-svn: 47798
2008-03-01 22:52:34 +01:00
Handle some 64-bit atomics on x86-32, some of the time. llvm-svn: 56963
2008-10-02 20:53:47 +02:00
def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
Change the model for FP Stack return to use fp operands on the RET instruction instead of using FpSET_ST0_32. This also generalizes the code to handling returning of multiple FP results. llvm-svn: 48209
2008-03-11 04:23:40 +01:00
def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
X86 conditional branch support. llvm-svn: 24870
2005-12-20 00:12:38 +01:00
Test commit: fixed spacing. llvm-svn: 74022
2009-06-24 01:25:37 +02:00
def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
SDTCisVT<1, i32>]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
Fix a tblgen problem handling variable_ops in tblgen instruction definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). llvm-svn: 51699
2008-05-29 21:57:41 +02:00
def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
On x86-64, for a varargs function, don't store the xmm registers to the register save area if %al is 0. This avoids touching xmm regsiters when they aren't actually used. llvm-svn: 79061
2009-08-15 03:38:56 +02:00
def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
SDTCisVT<1, iPTR>,
SDTCisVT<2, iPTR>]>;
revert r99743, this is saying that the repmovs instructinos have an *input* of other type, which is the VT. llvm-svn: 99749
2010-03-28 09:38:39 +02:00
def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
Lower dynamic stack allocation on mingw32 to separate instruction. We cannot use a normal call here since it has extra unmodelled side effects (it changes stack pointer). This should fix PR5292. llvm-svn: 97884
2010-03-06 20:32:29 +01:00
def SDTX86Void : SDTypeProfile<0, 0, []>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 03:39:21 +01:00
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate). * Add patterns to handle GlobalAddress, ConstantPool, etc. MOV32ri to materialize these nodes in registers. ADD32ri to handle %reg + GA, etc. MOV32mi to handle store GA, etc. to memory. llvm-svn: 26374
2006-02-25 11:02:21 +01:00
def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
For general dynamic TLS access we must use leaq foo@TLSGD(%rip), %rdi as part of the instruction sequence. Using a register other than %rdi and then copying it to %rdi is not valid. llvm-svn: 69350
2009-04-17 16:35:58 +02:00
def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Implement "general dynamic", "initial exec" and "local exec" TLS models for X86 32 bits. llvm-svn: 36283
2007-04-20 23:38:10 +02:00
Add first pass at darwin tls compiler support. llvm-svn: 105381
2010-06-03 06:07:48 +02:00
def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
Long live the exception handling! This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
2007-07-14 16:06:15 +02:00
def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Added tail call optimization to the x86 back end. It can be enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden llvm-svn: 42870
2007-10-11 21:40:01 +02:00
def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
Custom lower the memory barrier instructions and add support for lowering without sse2. Add a couple of new testcases. Fixes a few libgomp tests and latent bugs. Remove a few todos. llvm-svn: 109078
2010-07-22 04:48:34 +02:00
def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
[SDNPHasChain]>;
def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
[SDNPHasChain]>;
def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
[SDNPHasChain]>;
def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
[SDNPHasChain]>;
def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
[SDNPHasChain]>;
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
2010-03-28 07:07:17 +02:00
def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 03:39:21 +01:00
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-23 23:45:23 +01:00
def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
[SDNPHasChain]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
Re-enable 91381 with fixes. llvm-svn: 91489
2009-12-16 01:53:11 +01:00
def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 03:39:21 +01:00
all but CAS working on x86 llvm-svn: 47798
2008-03-01 22:52:34 +01:00
def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
give VZEXT_LOAD a memory operand, it now works with segment registers. llvm-svn: 114515
2010-09-22 02:34:38 +02:00
SDNPMayLoad, SDNPMemOperand]>;
64bit CAS on 32bit x86. llvm-svn: 47929
2008-03-05 02:15:49 +01:00
def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
give VZEXT_LOAD a memory operand, it now works with segment registers. llvm-svn: 114515
2010-09-22 02:34:38 +02:00
SDNPMayLoad, SDNPMemOperand]>;
Handle some 64-bit atomics on x86-32, some of the time. llvm-svn: 56963
2008-10-02 20:53:47 +02:00
def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
[SDNPHasChain, SDNPMayStore,
SDNPMayLoad, SDNPMemOperand]>;
def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
[SDNPHasChain, SDNPMayStore,
SDNPMayLoad, SDNPMemOperand]>;
def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
[SDNPHasChain, SDNPMayStore,
SDNPMayLoad, SDNPMemOperand]>;
def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
[SDNPHasChain, SDNPMayStore,
SDNPMayLoad, SDNPMemOperand]>;
def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
[SDNPHasChain, SDNPMayStore,
SDNPMayLoad, SDNPMemOperand]>;
def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
[SDNPHasChain, SDNPMayStore,
SDNPMayLoad, SDNPMemOperand]>;
Make atomic Swap work, 64-bit on x86-32. Make it all work in non-pic mode. llvm-svn: 57034
2008-10-04 00:25:52 +02:00
def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
[SDNPHasChain, SDNPMayStore,
SDNPMayLoad, SDNPMemOperand]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
add a new SDNPVariadic SDNP node flag, and use it in dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
2010-03-19 06:07:09 +01:00
[SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 03:39:21 +01:00
On x86-64, for a varargs function, don't store the xmm registers to the register save area if %al is 0. This avoids touching xmm regsiters when they aren't actually used. llvm-svn: 79061
2009-08-15 03:38:56 +02:00
def X86vastart_save_xmm_regs :
SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
SDT_X86VASTART_SAVE_XMM_REGS,
add a new SDNPVariadic SDNP node flag, and use it in dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
2010-03-19 06:07:09 +01:00
[SDNPHasChain, SDNPVariadic]>;
On x86-64, for a varargs function, don't store the xmm registers to the register save area if %al is 0. This avoids touching xmm regsiters when they aren't actually used. llvm-svn: 79061
2009-08-15 03:38:56 +02:00
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
def X86callseq_start :
SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
CALLSEQ_* produces chain even if that's not needed. llvm-svn: 29603
2006-08-11 11:03:33 +02:00
[SDNPHasChain, SDNPOutFlag]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
def X86callseq_end :
SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
Added tail call optimization to the x86 back end. It can be enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden llvm-svn: 42870
2007-10-11 21:40:01 +02:00
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 03:39:21 +01:00
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-09 19:33:28 +01:00
def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
add a new SDNPVariadic SDNP node flag, and use it in dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
2010-03-19 06:07:09 +01:00
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
SDNPVariadic]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
revert r99743, this is saying that the repmovs instructinos have an *input* of other type, which is the VT. llvm-svn: 99749
2010-03-28 09:38:39 +02:00
def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
get def use info more correct. llvm-svn: 45821
2008-01-10 06:12:37 +01:00
[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
revert r99743, this is saying that the repmovs instructinos have an *input* of other type, which is the VT. llvm-svn: 99749
2010-03-28 09:38:39 +02:00
def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
get def use info more correct. llvm-svn: 45821
2008-01-10 06:12:37 +01:00
[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
SDNPMayLoad]>;
Support for MEMCPY and MEMSET. llvm-svn: 25226
2006-01-11 23:15:48 +01:00
Lower dynamic stack allocation on mingw32 to separate instruction. We cannot use a normal call here since it has extra unmodelled side effects (it changes stack pointer). This should fix PR5292. llvm-svn: 97884
2010-03-06 20:32:29 +01:00
def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
[SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
DAG based isel call support. llvm-svn: 25103
2006-01-05 01:27:02 +01:00
- Use a different wrapper node for RIP-relative GV, etc. - Proper support for both small static and PIC modes under X86-64 - Some (non-optimal) support for medium modes. llvm-svn: 32046
2006-11-30 22:55:46 +01:00
def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate). * Add patterns to handle GlobalAddress, ConstantPool, etc. MOV32ri to materialize these nodes in registers. ADD32ri to handle %reg + GA, etc. MOV32mi to handle store GA, etc. to memory. llvm-svn: 26374
2006-02-25 11:02:21 +01:00
Implement "general dynamic", "initial exec" and "local exec" TLS models for X86 32 bits. llvm-svn: 36283
2007-04-20 23:38:10 +02:00
def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern), but should work. Work is in progress, more models will follow llvm-svn: 50630
2008-05-04 23:36:32 +02:00
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Implement "general dynamic", "initial exec" and "local exec" TLS models for X86 32 bits. llvm-svn: 36283
2007-04-20 23:38:10 +02:00
Long live the exception handling! This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
2007-07-14 16:06:15 +02:00
def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
[SDNPHasChain]>;
Added tail call optimization to the x86 back end. It can be enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden llvm-svn: 42870
2007-10-11 21:40:01 +02:00
def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
add a new SDNPVariadic SDNP node flag, and use it in dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
2010-03-19 06:07:09 +01:00
[SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
Implement "general dynamic", "initial exec" and "local exec" TLS models for X86 32 bits. llvm-svn: 36283
2007-04-20 23:38:10 +02:00
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-04 21:51:05 +01:00
def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 01:44:20 +01:00
[SDNPCommutative]>;
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. llvm-svn: 66058
2009-03-04 20:44:21 +01:00
def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-04 21:51:05 +01:00
def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 01:44:20 +01:00
[SDNPCommutative]>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-04 21:51:05 +01:00
def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 01:44:20 +01:00
[SDNPCommutative]>;
Switch SDTUnaryArithWithFlags to being modeled as a two-result ISD node. The only change in the generated isel code are comments like: < // Src: (X86dec_flag:i16 GR16:i16:$src) --- > // Src: (X86dec_flag:i16:i32 GR16:i16:$src) because now it knows that X86dec_flag returns both an i16 (for the result) and an i32 (for EFLAGS) in this case. Wewt. llvm-svn: 99369
2010-03-24 01:47:47 +01:00
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. llvm-svn: 66058
2009-03-04 20:44:21 +01:00
def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-04 21:51:05 +01:00
def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 01:44:20 +01:00
[SDNPCommutative]>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-04 21:51:05 +01:00
def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 01:44:20 +01:00
[SDNPCommutative]>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-04 21:51:05 +01:00
def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 01:44:20 +01:00
[SDNPCommutative]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. llvm-svn: 68066
2009-03-30 23:36:47 +02:00
def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
Lower dynamic stack allocation on mingw32 to separate instruction. We cannot use a normal call here since it has extra unmodelled side effects (it changes stack pointer). This should fix PR5292. llvm-svn: 97884
2010-03-06 20:32:29 +01:00
def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
Add first pass at darwin tls compiler support. llvm-svn: 105381
2010-06-03 06:07:48 +02:00
def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
[]>;
Lower dynamic stack allocation on mingw32 to separate instruction. We cannot use a normal call here since it has extra unmodelled side effects (it changes stack pointer). This should fix PR5292. llvm-svn: 97884
2010-03-06 20:32:29 +01:00
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
//===----------------------------------------------------------------------===//
// X86 Operand Definitions.
//
Add a new register class to describe operands that can't be SP, due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
2009-07-30 03:56:29 +02:00
// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
// the index operand of an address, to conform to x86 encoding restrictions.
def ptr_rc_nosp : PointerLikeRegClass<1>;
eliminate the "call" operand modifier from the asm descriptions, modeling it as a pcrel immediate instead. This gets pc-rel weirdness out of the main printoperand codepath. llvm-svn: 73829
2009-06-20 21:34:09 +02:00
Convert asmprinter to new style of instruction printer Start asmprintergen'ifying machine instrs with memory operands. llvm-svn: 15646
2004-08-11 04:25:00 +02:00
// *mem - Operand definitions for the funky X86 addressing mode operands.
//
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record structure. llvm-svn: 78581
2009-08-10 20:41:10 +02:00
def X86MemAsmOperand : AsmOperandClass {
let Name = "Mem";
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. llvm-svn: 104452
2010-05-22 23:02:29 +02:00
let SuperClasses = [];
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record structure. llvm-svn: 78581
2009-08-10 20:41:10 +02:00
}
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. - This fixes "leal 0, %eax", for example. llvm-svn: 103205
2010-05-07 00:39:14 +02:00
def X86AbsMemAsmOperand : AsmOperandClass {
let Name = "AbsMem";
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
let SuperClasses = [X86MemAsmOperand];
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. - This fixes "leal 0, %eax", for example. llvm-svn: 103205
2010-05-07 00:39:14 +02:00
}
Use generic iPTR instead i32 to represent pointer type. llvm-svn: 28371
2006-05-17 23:21:41 +02:00
class X86MemOperand<string printMethod> : Operand<iPTR> {
No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
2005-11-30 19:54:35 +01:00
let PrintMethod = printMethod;
Add a new register class to describe operands that can't be SP, due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
2009-07-30 03:56:29 +02:00
let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record structure. llvm-svn: 78581
2009-08-10 20:41:10 +02:00
let ParserMatchClass = X86MemAsmOperand;
Convert asmprinter to new style of instruction printer Start asmprintergen'ifying machine instrs with memory operands. llvm-svn: 15646
2004-08-11 04:25:00 +02:00
}
No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
2005-11-30 19:54:35 +01:00
Added opaque 32-, 48-, and 80-bit memory operand types to the X86 instruction tables to support segmented addressing (and other objects of obscure type). Modified the X86 assembly printers to handle these new operand types. Added JMP and CALL instructions that use segmented addresses. llvm-svn: 80857
2009-09-03 02:04:47 +02:00
def opaque32mem : X86MemOperand<"printopaquemem">;
def opaque48mem : X86MemOperand<"printopaquemem">;
def opaque80mem : X86MemOperand<"printopaquemem">;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def opaque512mem : X86MemOperand<"printopaquemem">;
eliminate some redundancy llvm-svn: 24781
2005-12-17 20:47:05 +01:00
def i8mem : X86MemOperand<"printi8mem">;
def i16mem : X86MemOperand<"printi16mem">;
def i32mem : X86MemOperand<"printi32mem">;
def i64mem : X86MemOperand<"printi64mem">;
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. Fixed some existing bugs (wrong predicates, prefixes) at the same time. llvm-svn: 26310
2006-02-22 03:26:30 +01:00
def i128mem : X86MemOperand<"printi128mem">;
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! llvm-svn: 108769
2010-07-20 01:32:44 +02:00
def i256mem : X86MemOperand<"printi256mem">;
eliminate some redundancy llvm-svn: 24781
2005-12-17 20:47:05 +01:00
def f32mem : X86MemOperand<"printf32mem">;
def f64mem : X86MemOperand<"printf64mem">;
Long double patch 4 of N: initial x87 implementation. Lots of problems yet but some simple things work. llvm-svn: 40847
2007-08-05 20:49:15 +02:00
def f80mem : X86MemOperand<"printf80mem">;
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. - Use XORP* to implement fneg. llvm-svn: 25857
2006-01-31 23:28:30 +01:00
def f128mem : X86MemOperand<"printf128mem">;
Start the support for AVX instructions with 256-bit %ymm registers. A couple of notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. llvm-svn: 107996
2010-07-09 20:27:43 +02:00
def f256mem : X86MemOperand<"printf256mem">;
No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
2005-11-30 19:54:35 +01:00
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-13 18:09:41 +02:00
// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
// plain GR64, so that it doesn't potentially require a REX prefix.
def i8mem_NOREX : Operand<i64> {
let PrintMethod = "printi8mem";
Add a new register class to describe operands that can't be SP, due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
2009-07-30 03:56:29 +02:00
let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record structure. llvm-svn: 78581
2009-08-10 20:41:10 +02:00
let ParserMatchClass = X86MemAsmOperand;
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-13 18:09:41 +02:00
}
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. llvm-svn: 98465
2010-03-14 04:48:46 +01:00
// Special i32mem for addresses of load folding tail calls. These are not
// allowed to use callee-saved registers since they must be scheduled
// after callee-saved register are popped.
def i32mem_TC : Operand<i32> {
let PrintMethod = "printi32mem";
let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
let ParserMatchClass = X86MemAsmOperand;
}
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 08:37:31 +02:00
// Special i64mem for addresses of load folding tail calls. These are not
// allowed to use callee-saved registers since they must be scheduled
// after callee-saved register are popped.
def i64mem_TC : Operand<i64> {
let PrintMethod = "printi64mem";
let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
let ParserMatchClass = X86MemAsmOperand;
}
Committing X86-64 support. llvm-svn: 30177
2006-09-08 08:48:29 +02:00
MC/X86 AsmParser: Handle absolute memory operands correctly. We were doing something totally broken and parsing them as immediates, but the .td file also had the wrong match class so things sortof worked. Except, that is, that we would parse movl $0, %eax as movl 0, %eax Feel free to guess how well that worked. llvm-svn: 94869
2010-01-30 02:02:48 +01:00
let ParserMatchClass = X86AbsMemAsmOperand,
PrintMethod = "print_pcrel_imm" in {
X86.td: Refactor to bring operands that use print_pcrel_imm together. llvm-svn: 94861
2010-01-30 01:24:12 +01:00
def i32imm_pcrel : Operand<i32>;
Implement the major chunk of PR7195: support for 'callw' in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
2010-07-08 00:27:31 +02:00
def i16imm_pcrel : Operand<i16>;
X86.td: Refactor to bring operands that use print_pcrel_imm together. llvm-svn: 94861
2010-01-30 01:24:12 +01:00
def offset8 : Operand<i64>;
def offset16 : Operand<i64>;
def offset32 : Operand<i64>;
def offset64 : Operand<i64>;
// Branch targets have OtherVT type and print as pc-relative values.
def brtarget : Operand<OtherVT>;
def brtarget8 : Operand<OtherVT>;
}
Get closer to fully working scalar FP in SSE regs. This gets singlesource working, and Olden/power. llvm-svn: 22441
2005-07-15 02:38:55 +02:00
def SSECC : Operand<i8> {
let PrintMethod = "printSSECC";
}
Convert asmprinter to new style of instruction printer Start asmprintergen'ifying machine instrs with memory operands. llvm-svn: 15646
2004-08-11 04:25:00 +02:00
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
class ImmSExtAsmOperandClass : AsmOperandClass {
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. llvm-svn: 104452
2010-05-22 23:02:29 +02:00
let SuperClasses = [ImmAsmOperand];
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
let RenderMethod = "addImmOperands";
X86: Model i64i32imm properly, as a subclass of all immediates. llvm-svn: 104272
2010-05-20 22:20:39 +02:00
}
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
// Sign-extended immediate classes. We don't need to define the full lattice
// here because there is no instruction with an ambiguity between ImmSExti64i32
// and ImmSExti32i8.
//
// The strange ranges come from the fact that the assembler always works with
// 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
// (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
// [0, 0x7FFFFFFF] |
// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
let Name = "ImmSExti64i32";
}
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
let Name = "ImmSExti16i8";
let SuperClasses = [ImmSExti64i32AsmOperand];
}
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
let Name = "ImmSExti32i8";
}
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
// [0, 0x0000007F] |
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
let Name = "ImmSExti64i8";
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
ImmSExti64i32AsmOperand];
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record structure. llvm-svn: 78581
2009-08-10 20:41:10 +02:00
}
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 02:04:42 +01:00
// A couple of more descriptive operand definitions.
// 16-bits but only 8 bits are significant.
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 09:20:21 +02:00
def i16i8imm : Operand<i16> {
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
let ParserMatchClass = ImmSExti16i8AsmOperand;
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 09:20:21 +02:00
}
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 02:04:42 +01:00
// 32-bits but only 8 bits are significant.
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 09:20:21 +02:00
def i32i8imm : Operand<i32> {
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-22 23:02:33 +02:00
let ParserMatchClass = ImmSExti32i8AsmOperand;
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 09:20:21 +02:00
}
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 02:04:42 +01:00
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 08:37:31 +02:00
// 64-bits but only 32 bits are significant.
def i64i32imm : Operand<i64> {
let ParserMatchClass = ImmSExti64i32AsmOperand;
}
// 64-bits but only 32 bits are significant, and those bits are treated as being
// pc relative.
def i64i32imm_pcrel : Operand<i64> {
let PrintMethod = "print_pcrel_imm";
let ParserMatchClass = X86AbsMemAsmOperand;
}
// 64-bits but only 8 bits are significant.
def i64i8imm : Operand<i64> {
let ParserMatchClass = ImmSExti64i8AsmOperand;
}
def lea64_32mem : Operand<i32> {
let PrintMethod = "printi32mem";
let AsmOperandLowerMethod = "lower_lea64_32mem";
let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
let ParserMatchClass = X86MemAsmOperand;
}
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
//===----------------------------------------------------------------------===//
// X86 Complex Pattern Definitions.
//
* Added intelligence to X86 LEA addressing mode matching routine so it returns false if the match is not profitable. e.g. leal 1(%eax), %eax. * Added patterns for X86 integer loads and LEA32. llvm-svn: 24635
2005-12-08 03:01:35 +01:00
// Define X86 specific addressing mode.
reimplement support for GS and FS relative address space matching by having X86DAGToDAGISel::SelectAddr get passed in the parent node of the operand match (the load/store/atomic op) and having it get the address space from that, instead of having special FS/GS addr mode operations that require duplicating the entire instruction set to support. This makes FS and GS relative accesses *far* more predictable and work much better. It also simplifies the X86 backend a bit, more to come. There is still a pending issue with nodes like ISD::PREFETCH and X86ISD::FLD, which really should be MemSDNode's but aren't. llvm-svn: 114491
2010-09-22 00:07:31 +02:00
def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
Resync lea32addr and lea64addr. llvm-svn: 77893
2009-08-02 18:09:17 +02:00
[add, sub, mul, X86mul_imm, shl, or, frameindex],
[]>;
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
change TLS_ADDR lowering to lower to a real mem operand, instead of matching as a global with that gets printed with the :mem modifier. All operands to lea's should be handled with the lea32mem operand kind, and this allows the TLS stuff to do this. There are several better ways to do this, but I went for the minimal change since I can't really test this (beyond make check). This also makes the use of EBX explicit in the operand list in the 32-bit, instead of implicit in the instruction. llvm-svn: 73834
2009-06-20 22:38:48 +02:00
[tglobaltlsaddr], []>;
* Added intelligence to X86 LEA addressing mode matching routine so it returns false if the match is not profitable. e.g. leal 1(%eax), %eax. * Added patterns for X86 integer loads and LEA32. llvm-svn: 24635
2005-12-08 03:01:35 +01:00
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 08:37:31 +02:00
def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
[add, sub, mul, X86mul_imm, shl, or, frameindex,
X86WrapperRIP], []>;
def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
[tglobaltlsaddr], []>;
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. llvm-svn: 24886
2005-12-20 23:59:51 +01:00
//===----------------------------------------------------------------------===//
// X86 Instruction Predicate Definitions.
add support for pentium class CPUs which do not have cmov, PR4841. Patch by Craig Smith! llvm-svn: 98496
2010-03-14 19:31:44 +01:00
def HasCMov : Predicate<"Subtarget->hasCMov()">;
def NoCMov : Predicate<"!Subtarget->hasCMov()">;
Temporary hack to let codegen assert or generate poor code in case we are using AVX and no AVX version of the desired intruction is present, this is better for incremental dev (without fallbacks it's easier to spot what's missing). Not sure this is the best hack thought (we can also disable all HasSSE* predicates by dinamically marking them 'false' if AVX is present) llvm-svn: 109434
2010-07-26 23:01:18 +02:00
// FIXME: temporary hack to let codegen assert or generate poor code in case
// no AVX version of the desired intructions is present, this is better for
// incremental dev (without fallbacks it's easier to spot what's missing)
Fix typo! llvm-svn: 109877
2010-07-30 21:41:24 +02:00
def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
Implement support for the bizarre 3DNow! encoding (which is unlike anything else in X86), and add support for pavgusb. This is apparently the only instruction (other than movsx) that is preventing ffmpeg from building with clang. If someone else is interested in banging out the rest of the 3DNow! instructions, it should be quite easy now. llvm-svn: 115466
2010-10-03 20:08:05 +02:00
def Has3DNow : Predicate<"Subtarget->has3DNow()">;
def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
Fix typo! llvm-svn: 109877
2010-07-30 21:41:24 +02:00
def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
Temporary hack to let codegen assert or generate poor code in case we are using AVX and no AVX version of the desired intruction is present, this is better for incremental dev (without fallbacks it's easier to spot what's missing). Not sure this is the best hack thought (we can also disable all HasSSE* predicates by dinamically marking them 'false' if AVX is present) llvm-svn: 109434
2010-07-26 23:01:18 +02:00
Add feature flags for AVX and FMA and fix some SSE4A feature flag initialization problems. llvm-svn: 74350
2009-06-27 00:46:54 +02:00
def HasAVX : Predicate<"Subtarget->hasAVX()">;
Add x86 CLMUL (Carry-less multiplication) cpu feature llvm-svn: 109206
2010-07-23 03:17:51 +02:00
def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
Add feature flags for AVX and FMA and fix some SSE4A feature flag initialization problems. llvm-svn: 74350
2009-06-27 00:46:54 +02:00
def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
Fix PR 1681. When X86 target uses +sse -sse2, keep f32 in SSE registers and f64 in x87. This is effectively a new codegen mode. Change addLegalFPImmediate to permit float and double variants to do different things. Adjust callers. llvm-svn: 42246
2007-09-23 16:52:20 +02:00
def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
- Switch X86-64 JIT to large code size model. - Re-enable some codegen niceties for X86-64 static relocation model codegen. - Clean ups, etc. llvm-svn: 32238
2006-12-05 20:50:18 +01:00
def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
def In64BitMode : Predicate<"Subtarget->is64Bit()">;
Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers. llvm-svn: 77962
2009-08-03 10:12:53 +02:00
def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
We need to sext global addresses in kernel code model, not zext llvm-svn: 78299
2009-08-06 13:23:24 +02:00
def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
Missed part of recent kernel codemodel tweaks llvm-svn: 78293
2009-08-06 11:11:19 +02:00
"TM.getCodeModel() != CodeModel::Kernel">;
We need to sext global addresses in kernel code model, not zext llvm-svn: 78299
2009-08-06 13:23:24 +02:00
def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
"TM.getCodeModel() == CodeModel::Kernel">;
- Switch X86-64 JIT to large code size model. - Re-enable some codegen niceties for X86-64 static relocation model codegen. - Clean ups, etc. llvm-svn: 32238
2006-12-05 20:50:18 +01:00
def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this: addl $12, %esp popl %esi popl %edi popl %ebx popl %ebp jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class. The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit. llvm-svn: 99455
2010-03-25 01:10:31 +01:00
def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. llvm-svn: 91910
2009-12-22 18:47:23 +01:00
def OptForSize : Predicate<"OptForSize">;
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. llvm-svn: 56711
2008-09-27 01:41:32 +02:00
def OptForSpeed : Predicate<"!OptForSize">;
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. llvm-svn: 61557
2009-01-02 06:35:45 +01:00
def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
Try again. Allow call to immediate address for ELF or when in static relocation mode. llvm-svn: 72160
2009-05-20 06:53:57 +02:00
def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
Separate out the AES-NI instructions from the SSE4.2 instructions. Add a new subtarget option for AES and check for the support. Add "westmere" line of processors and add AES-NI support to the core i7. Add a couple of TODOs for information I couldn't verify. llvm-svn: 100231
2010-04-02 23:54:27 +02:00
def HasAES : Predicate<"Subtarget->hasAES()">;
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. llvm-svn: 24886
2005-12-20 23:59:51 +01:00
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
//===----------------------------------------------------------------------===//
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) llvm-svn: 40628
2007-07-31 10:04:03 +02:00
// X86 Instruction Format Definitions.
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 02:24:02 +01:00
//
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) llvm-svn: 40628
2007-07-31 10:04:03 +02:00
include "X86InstrFormats.td"
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 02:04:42 +01:00
//===----------------------------------------------------------------------===//
// Pattern fragments...
//
* Fast call support. * FP cmp, setcc, etc. llvm-svn: 25117
2006-01-06 01:43:03 +01:00
// X86 specific condition code. These correspond to CondCode in
Reference correct header llvm-svn: 36834
2007-05-06 06:00:55 +02:00
// X86InstrInfo.h. They must be kept in synch.
X86_COND_C and X86_COND_NC are alternate mnemonics for X86_COND_B and X86_COND_AE, respectively. llvm-svn: 61835
2009-01-07 01:15:08 +01:00
def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
* Fast call support. * FP cmp, setcc, etc. llvm-svn: 25117
2006-01-06 01:43:03 +01:00
def X86_COND_NO : PatLeaf<(i8 10)>;
X86_COND_C and X86_COND_NC are alternate mnemonics for X86_COND_B and X86_COND_AE, respectively. llvm-svn: 61835
2009-01-07 01:15:08 +01:00
def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
* Fast call support. * FP cmp, setcc, etc. llvm-svn: 25117
2006-01-06 01:43:03 +01:00
def X86_COND_NS : PatLeaf<(i8 12)>;
X86_COND_C and X86_COND_NC are alternate mnemonics for X86_COND_B and X86_COND_AE, respectively. llvm-svn: 61835
2009-01-07 01:15:08 +01:00
def X86_COND_O : PatLeaf<(i8 13)>;
def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
def X86_COND_S : PatLeaf<(i8 15)>;
* Fast call support. * FP cmp, setcc, etc. llvm-svn: 25117
2006-01-06 01:43:03 +01:00
Don't call Predicate_* from X86 target. llvm-svn: 112921
2010-09-03 02:35:18 +02:00
def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 02:04:42 +01:00
factor the 'sign extended from 8 bit' patterns better so that they are not destination type specific. This allows tblgen to factor them and the type check is redundant with what the isel does anyway. llvm-svn: 97629
2010-03-03 02:45:01 +01:00
def i16immSExt8 : PatLeaf<(i16 immSext8)>;
def i32immSExt8 : PatLeaf<(i32 immSext8)>;
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 08:37:31 +02:00
def i64immSExt8 : PatLeaf<(i64 immSext8)>;
def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>;
def i64immZExt32 : PatLeaf<(i64 imm), [{
// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
// unsignedsign extended field.
return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
}]>;
* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands. This enables the removal of some explicit type casts. * Rename immZExt8 to i16ZExt8 as well. llvm-svn: 24682
2005-12-13 01:01:09 +01:00
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. llvm-svn: 24688
2005-12-13 02:57:51 +01:00
// Helper fragments for loads.
- Fix the pasto in the fix for a previous pasto. - Incorporate Chris' comment suggestion. llvm-svn: 51061
2008-05-13 20:59:59 +02:00
// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
// known to be 32-bit aligned or better. Ditto for i8 to i16.
Now that predicates can be composed, simplify several of the predicates by extending simple predicates to create more complex predicates instead of duplicating the logic for the simple predicates. This doesn't reduce much redundancy in DAGISelEmitter.cpp's generated source yet; that will require improvements to DAGISelEmitter.cpp's instruction sorting, to make it more effectively group nodes with similar predicates together. llvm-svn: 57565
2008-10-15 08:50:19 +02:00
def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
Tablegen generated code already tests the opcode value, so it's not necessary to use dyn_cast in these predicates. llvm-svn: 55055
2008-08-20 17:24:22 +02:00
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD)
return true;
if (ExtType == ISD::EXTLOAD)
return LD->getAlignment() >= 2 && !LD->isVolatile();
On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. llvm-svn: 51019
2008-05-13 02:54:02 +02:00
return false;
}]>;
factor the 'in the default address space' check out to a single 'dsload' pattern. tblgen doesn't check patterns to see if they're textually identical. This allows better factoring. llvm-svn: 97630
2010-03-03 02:52:59 +01:00
def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. llvm-svn: 56594
2008-09-25 01:27:55 +02:00
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::EXTLOAD)
return LD->getAlignment() >= 2 && !LD->isVolatile();
return false;
}]>;
Now that predicates can be composed, simplify several of the predicates by extending simple predicates to create more complex predicates instead of duplicating the logic for the simple predicates. This doesn't reduce much redundancy in DAGISelEmitter.cpp's generated source yet; that will require improvements to DAGISelEmitter.cpp's instruction sorting, to make it more effectively group nodes with similar predicates together. llvm-svn: 57565
2008-10-15 08:50:19 +02:00
def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Tablegen generated code already tests the opcode value, so it's not necessary to use dyn_cast in these predicates. llvm-svn: 55055
2008-08-20 17:24:22 +02:00
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD)
return true;
if (ExtType == ISD::EXTLOAD)
return LD->getAlignment() >= 4 && !LD->isVolatile();
On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. llvm-svn: 51019
2008-05-13 02:54:02 +02:00
return false;
}]>;
reimplement support for GS and FS relative address space matching by having X86DAGToDAGISel::SelectAddr get passed in the parent node of the operand match (the load/store/atomic op) and having it get the address space from that, instead of having special FS/GS addr mode operations that require duplicating the entire instruction set to support. This makes FS and GS relative accesses *far* more predictable and work much better. It also simplifies the X86 backend a bit, more to come. There is still a pending issue with nodes like ISD::PREFETCH and X86ISD::FLD, which really should be MemSDNode's but aren't. llvm-svn: 114491
2010-09-22 00:07:31 +02:00
def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
Added sext and zext patterns. llvm-svn: 24705
2005-12-14 03:22:27 +01:00
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. llvm-svn: 30844
2006-10-09 22:57:25 +02:00
def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 08:37:31 +02:00
def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. llvm-svn: 30844
2006-10-09 22:57:25 +02:00
def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 08:37:31 +02:00
def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. llvm-svn: 30844
2006-10-09 22:57:25 +02:00
def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 08:37:31 +02:00
def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
Added separate alias instructions for SSE logical ops that operate on non-packed types. llvm-svn: 26297
2006-02-21 03:24:38 +01:00
Don't fold and's into test instructions if they have multiple uses. This compiles test-nofold.ll into: _test: movl $15, %ecx andl 4(%esp), %ecx testl %ecx, %ecx movl $42, %eax cmove %ecx, %eax ret instead of: _test: movl 4(%esp), %eax movl %eax, %ecx andl $15, %ecx testl $15, %eax movl $42, %eax cmove %ecx, %eax ret llvm-svn: 47330
2008-02-19 18:37:35 +01:00
// An 'and' node with a single use.
def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
Remove -always-fold-and-in-test. llvm-svn: 47871
2008-03-04 01:40:35 +01:00
return N->hasOneUse();
Don't fold and's into test instructions if they have multiple uses. This compiles test-nofold.ll into: _test: movl $15, %ecx andl 4(%esp), %ecx testl %ecx, %ecx movl $42, %eax cmove %ecx, %eax ret instead of: _test: movl 4(%esp), %eax movl %eax, %ecx andl $15, %ecx testl $15, %eax movl $42, %eax cmove %ecx, %eax ret llvm-svn: 47330
2008-02-19 18:37:35 +01:00
}]>;
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-13 18:09:41 +02:00
// An 'srl' node with a single use.
def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
return N->hasOneUse();
}]>;
// An 'trunc' node with a single use.
def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
return N->hasOneUse();
}]>;
Don't fold and's into test instructions if they have multiple uses. This compiles test-nofold.ll into: _test: movl $15, %ecx andl 4(%esp), %ecx testl %ecx, %ecx movl $42, %eax cmove %ecx, %eax ret instead of: _test: movl 4(%esp), %eax movl %eax, %ecx andl $15, %ecx testl $15, %eax movl $42, %eax cmove %ecx, %eax ret llvm-svn: 47330
2008-02-19 18:37:35 +01:00
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. llvm-svn: 93152
2010-01-11 18:03:47 +01:00
// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
reduce nesting. llvm-svn: 99358
2010-03-24 01:12:57 +01:00
unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
APInt Mask = APInt::getAllOnesValue(BitWidth);
APInt KnownZero0, KnownOne0;
CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
APInt KnownZero1, KnownOne1;
CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
return (~KnownZero0 & ~KnownZero1) == 0;
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. llvm-svn: 93152
2010-01-11 18:03:47 +01:00
}]>;
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
//===----------------------------------------------------------------------===//
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 07:32:15 +02:00
// Instruction list.
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
//
SSE cmov support. llvm-svn: 25190
2006-01-11 01:33:36 +01:00
// Nop
Added a 2+-byte NOP instruction to the Intel tables, for the assembler/disassembler to use. llvm-svn: 76914
2009-07-24 01:39:34 +02:00
let neverHasSideEffects = 1 in {
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
"nop{w}\t$zero", []>, TB, OpSize;
Added a 2+-byte NOP instruction to the Intel tables, for the assembler/disassembler to use. llvm-svn: 76914
2009-07-24 01:39:34 +02:00
def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
"nop{l}\t$zero", []>, TB;
Added a 2+-byte NOP instruction to the Intel tables, for the assembler/disassembler to use. llvm-svn: 76914
2009-07-24 01:39:34 +02:00
}
SSE cmov support. llvm-svn: 25190
2006-01-11 01:33:36 +01:00
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
Added the ENTER instruction, which sets up a stack frame, to the Intel instruction tables. llvm-svn: 81995
2009-09-16 04:57:13 +02:00
// Constructing a stack frame.
fix rdar://8444631 - encoder crash on 'enter' What a weird instruction. llvm-svn: 114190
2010-09-17 20:02:29 +02:00
def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
"enter\t$len, $lvl", []>;
Added the ENTER instruction, which sets up a stack frame, to the Intel instruction tables. llvm-svn: 81995
2009-09-16 04:57:13 +02:00
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
This purely mechanical patch gives the "I" tblgen class operand list and asm string operands, and adjusts all users to pass them in instead of using II. llvm-svn: 15624
2004-08-10 22:17:41 +02:00
def LEAVE : I<0xC9, RawFrm,
X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64]. llvm-svn: 108683
2010-07-19 09:21:01 +02:00
(outs), (ins), "leave", []>, Requires<[In32BitMode]>;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
move CMOV_FR32 and friends to InstrCompiler, since they are pseudo instructions. Move POPCNT to InstrSSE since they are SSE4 instructions. llvm-svn: 115603
2010-10-05 08:41:40 +02:00
let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
def LEAVE64 : I<0xC9, RawFrm,
(outs), (ins), "leave", []>, Requires<[In64BitMode]>;
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 08:04:14 +02:00
//===----------------------------------------------------------------------===//
move CMOV_FR32 and friends to InstrCompiler, since they are pseudo instructions. Move POPCNT to InstrSSE since they are SSE4 instructions. llvm-svn: 115603
2010-10-05 08:41:40 +02:00
// Miscellaneous Instructions.
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 08:04:14 +02:00
//
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
Added a variety of PUSH and POP instructions, including ones capable of accessing R/M operands instead of just registers. llvm-svn: 81456
2009-09-10 20:29:13 +02:00
let mayLoad = 1 in {
def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
OpSize;
def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
OpSize;
def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
OpSize;
def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 08:47:35 +02:00
def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
Requires<[In32BitMode]>;
Added a variety of PUSH and POP instructions, including ones capable of accessing R/M operands instead of just registers. llvm-svn: 81456
2009-09-10 20:29:13 +02:00
}
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
Added a variety of PUSH and POP instructions, including ones capable of accessing R/M operands instead of just registers. llvm-svn: 81456
2009-09-10 20:29:13 +02:00
let mayStore = 1 in {
def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
OpSize;
Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. llvm-svn: 42335
2007-09-26 03:29:06 +02:00
def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
Added a variety of PUSH and POP instructions, including ones capable of accessing R/M operands instead of just registers. llvm-svn: 81456
2009-09-10 20:29:13 +02:00
def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
OpSize;
def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
OpSize;
def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
Implemented correct stack probing on mingw/cygwin for dynamic alloca's. Also, fixed static case in presence of eax livin. This fixes PR331 PS: Why don't we still have push/pop instructions? :) llvm-svn: 36195
2007-04-17 11:20:00 +02:00
Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value caused the a pushl instruction to be incorrectly encoding using only two bytes of immediate, causing the following 2 instruction bytes to be part of the 32-bit immediate value. Also fixed the one byte form of push to be used when the immediate would fit in a signed extended byte. Lastly changed the names to not include the 32 of PUSH32 since they actually push the size of the stack pointer. llvm-svn: 102951
2010-05-03 22:45:05 +02:00
def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
The Ls and Qs were mixed up. Patch by Sean. llvm-svn: 73417
2009-06-15 22:59:31 +02:00
"push{l}\t$imm", []>;
Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value caused the a pushl instruction to be incorrectly encoding using only two bytes of immediate, causing the following 2 instruction bytes to be part of the 32-bit immediate value. Also fixed the one byte form of push to be used when the immediate would fit in a signed extended byte. Lastly changed the names to not include the 32 of PUSH32 since they actually push the size of the stack pointer. llvm-svn: 102951
2010-05-03 22:45:05 +02:00
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
"push{w}\t$imm", []>, OpSize;
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
The Ls and Qs were mixed up. Patch by Sean. llvm-svn: 73417
2009-06-15 22:59:31 +02:00
"push{l}\t$imm", []>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 08:47:35 +02:00
Fix assembly parsing and encoding of the pushf and popf family of instructions. llvm-svn: 104231
2010-05-20 18:16:00 +02:00
def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
Requires<[In32BitMode]>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 08:47:35 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
}
Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. llvm-svn: 42335
2007-09-26 03:29:06 +02:00
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 08:47:35 +02:00
let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
let mayLoad = 1 in {
def POP64r : I<0x58, AddRegFrm,
(outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
}
let mayStore = 1 in {
def PUSH64r : I<0x50, AddRegFrm,
(outs), (ins GR64:$reg), "push{q}\t$reg", []>;
def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
}
}
let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
"push{q}\t$imm", []>;
def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
"push{q}\t$imm", []>;
def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
"push{q}\t$imm", []>;
}
let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
Requires<[In64BitMode]>;
let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
Requires<[In64BitMode]>;
Add support for the x86 instructions "pusha" and "popa". llvm-svn: 106671
2010-06-23 22:00:58 +02:00
let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
mayLoad=1, neverHasSideEffects=1 in {
def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
Requires<[In32BitMode]>;
}
let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
mayStore=1, neverHasSideEffects=1 in {
def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
Requires<[In32BitMode]>;
}
move sign and zero extensions out to their own file. llvm-svn: 115605
2010-10-05 08:52:26 +02:00
let Constraints = "$src = $dst" in { // GR32 = bswap GR32
def BSWAP32r : I<0xC8, AddRegFrm,
(outs GR32:$dst), (ins GR32:$src),
"bswap{l}\t$dst",
[(set GR32:$dst, (bswap GR32:$src))]>, TB;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 08:47:35 +02:00
def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
"bswap{q}\t$dst",
[(set GR64:$dst, (bswap GR64:$src))]>, TB;
move sign and zero extensions out to their own file. llvm-svn: 115605
2010-10-05 08:52:26 +02:00
} // Constraints = "$src = $dst"
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 03:13:44 +01:00
// Bit scan instructions.
let Defs = [EFLAGS] in {
Fix bsf / bsr jit encoding. llvm-svn: 45037
2007-12-14 19:49:43 +01:00
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 16:10:00 +01:00
"bsf{w}\t{$src, $dst|$dst, $src}",
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the Operand size override prefix to be part of their records. llvm-svn: 102556
2010-04-29 01:20:40 +02:00
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 03:13:44 +01:00
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 16:10:00 +01:00
"bsf{w}\t{$src, $dst|$dst, $src}",
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the Operand size override prefix to be part of their records. llvm-svn: 102556
2010-04-29 01:20:40 +02:00
[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
OpSize;
Fix bsf / bsr jit encoding. llvm-svn: 45037
2007-12-14 19:49:43 +01:00
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 16:10:00 +01:00
"bsf{l}\t{$src, $dst|$dst, $src}",
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
2010-03-28 07:07:17 +02:00
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 03:13:44 +01:00
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 16:10:00 +01:00
"bsf{l}\t{$src, $dst|$dst, $src}",
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
2010-03-28 07:07:17 +02:00
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 08:47:35 +02:00
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"bsf{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"bsf{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 03:13:44 +01:00
Fix bsf / bsr jit encoding. llvm-svn: 45037
2007-12-14 19:49:43 +01:00
def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 16:10:00 +01:00
"bsr{w}\t{$src, $dst|$dst, $src}",
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the Operand size override prefix to be part of their records. llvm-svn: 102556
2010-04-29 01:20:40 +02:00
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 03:13:44 +01:00
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 16:10:00 +01:00
"bsr{w}\t{$src, $dst|$dst, $src}",
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the Operand size override prefix to be part of their records. llvm-svn: 102556
2010-04-29 01:20:40 +02:00
[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
OpSize;
Fix bsf / bsr jit encoding. llvm-svn: 45037
2007-12-14 19:49:43 +01:00
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 16:10:00 +01:00
"bsr{l}\t{$src, $dst|$dst, $src}",
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
2010-03-28 07:07:17 +02:00
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 03:13:44 +01:00
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 16:10:00 +01:00
"bsr{l}\t{$src, $dst|$dst, $src}",
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
2010-03-28 07:07:17 +02:00
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 08:47:35 +02:00
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"bsr{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"bsr{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 03:13:44 +01:00
} // Defs = [EFLAGS]
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let neverHasSideEffects = 1 in
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def LEA16r : I<0x8D, MRMSrcMem,
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
(outs GR16:$dst), (ins i32mem:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 02:41:09 +01:00
let isReMaterializable = 1 in
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def LEA32r : I<0x8D, MRMSrcMem,
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 01:46:44 +02:00
(outs GR32:$dst), (ins i32mem:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"lea{l}\t{$src|$dst}, {$dst|$src}",
Committing X86-64 support. llvm-svn: 30177
2006-09-08 08:48:29 +02:00
[(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 08:47:35 +02:00
def LEA64_32r : I<0x8D, MRMSrcMem,
(outs GR32:$dst), (ins lea64_32mem:$src),
"lea{l}\t{$src|$dst}, {$dst|$src}",
[(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
let isReMaterializable = 1 in
def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"lea{q}\t{$src|$dst}, {$dst|$src}",
[(set GR64:$dst, lea64addr:$src)]>;
This purely mechanical patch gives the "I" tblgen class operand list and asm string operands, and adjusts all users to pass them in instead of using II. llvm-svn: 15624
2004-08-10 22:17:41 +02:00
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-03 22:04:42 +01:00
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. llvm-svn: 115600
2010-10-05 08:27:48 +02:00
def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-03 22:04:42 +01:00
}
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. llvm-svn: 115600
2010-10-05 08:27:48 +02:00
let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-03 22:04:42 +01:00
Added SCAS instructions in their 8, 16, 32, and 64-bit variants for the disassembler. llvm-svn: 81591
2009-09-12 02:37:19 +02:00
def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. llvm-svn: 115600
2010-10-05 08:27:48 +02:00
def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
Added SCAS instructions in their 8, 16, 32, and 64-bit variants for the disassembler. llvm-svn: 81591
2009-09-12 02:37:19 +02:00
Added CMPS (string comparison) instructions for all operand widths to the Intel instruction tables, for the purposes of the disassembler. llvm-svn: 81601
2009-09-12 04:25:20 +02:00
def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. llvm-svn: 115600
2010-10-05 08:27:48 +02:00
def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
Added CMPS (string comparison) instructions for all operand widths to the Intel instruction tables, for the purposes of the disassembler. llvm-svn: 81601
2009-09-12 04:25:20 +02:00
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
//===----------------------------------------------------------------------===//
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 07:32:15 +02:00
// Move Instructions.
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
//
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let neverHasSideEffects = 1 in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{b}\t{$src, $dst|$dst, $src}", []>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{l}\t{$src, $dst|$dst, $src}", []>;
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
}
XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are. llvm-svn: 52454
2008-06-18 10:13:07 +02:00
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{b}\t{$src, $dst|$dst, $src}",
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
[(set GR8:$dst, imm:$src)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{w}\t{$src, $dst|$dst, $src}",
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
[(set GR16:$dst, imm:$src)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{l}\t{$src, $dst|$dst, $src}",
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
[(set GR32:$dst, imm:$src)]>;
Revert the earlier change that removed the M_REMATERIALIZABLE machine instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
2007-06-26 02:48:07 +02:00
}
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-03 22:04:42 +01:00
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{b}\t{$src, $dst|$dst, $src}",
* Added X86 store patterns. * Added X86 dec patterns. llvm-svn: 24654
2005-12-10 01:48:20 +01:00
[(store (i8 imm:$src), addr:$dst)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{w}\t{$src, $dst|$dst, $src}",
* Added X86 store patterns. * Added X86 dec patterns. llvm-svn: 24654
2005-12-10 01:48:20 +01:00
[(store (i16 imm:$src), addr:$dst)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{l}\t{$src, $dst|$dst, $src}",
* Added X86 store patterns. * Added X86 dec patterns. llvm-svn: 24654
2005-12-10 01:48:20 +01:00
[(store (i32 imm:$src), addr:$dst)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
reapply r103668 with a fix. Never make "minor syntax changes" after testing before committing. llvm-svn: 103681
2010-05-13 02:02:47 +02:00
/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
/// 32-bit offset from the PC. These are only valid in x86-32 mode.
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 llvm-svn: 103660
2010-05-13 00:48:24 +02:00
def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. llvm-svn: 108679
2010-07-19 08:14:44 +02:00
"mov{b}\t{$src, %al|%al, $src}", []>,
Requires<[In32BitMode]>;
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 llvm-svn: 103660
2010-05-13 00:48:24 +02:00
def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. llvm-svn: 108679
2010-07-19 08:14:44 +02:00
"mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
Requires<[In32BitMode]>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. llvm-svn: 108679
2010-07-19 08:14:44 +02:00
"mov{l}\t{$src, %eax|%eax, $src}", []>,
Requires<[In32BitMode]>;
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 llvm-svn: 103660
2010-05-13 00:48:24 +02:00
def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. llvm-svn: 108679
2010-07-19 08:14:44 +02:00
"mov{b}\t{%al, $dst|$dst, %al}", []>,
Requires<[In32BitMode]>;
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 llvm-svn: 103660
2010-05-13 00:48:24 +02:00
def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. llvm-svn: 108679
2010-07-19 08:14:44 +02:00
"mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
Requires<[In32BitMode]>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. llvm-svn: 108679
2010-07-19 08:14:44 +02:00
"mov{l}\t{%eax, $dst|$dst, %eax}", []>,
Requires<[In32BitMode]>;
reapply r103668 with a fix. Never make "minor syntax changes" after testing before committing. llvm-svn: 103681
2010-05-13 02:02:47 +02:00
Added a new register class for segment registers to the Intel register table. Added 16- and 64-bit MOVs to and from the segment registers to the Intel instruction tables. llvm-svn: 81895
2009-09-15 20:47:29 +02:00
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
let isCodeGenOnly = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
"mov{b}\t{$src, $dst|$dst, $src}", []>;
def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"mov{l}\t{$src, $dst|$dst, $src}", []>;
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
The mayHaveSideEffects flag is no longer used. llvm-svn: 97348
2010-02-28 00:47:46 +01:00
let canFoldAsLoad = 1, isReMaterializable = 1 in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{b}\t{$src, $dst|$dst, $src}",
a few fixes to "addrspace(256) is reference offset of GS segment register". It turns out that there are still several problems with this, will file a bugzilla. llvm-svn: 68749
2009-04-10 02:16:23 +02:00
[(set GR8:$dst, (loadi8 addr:$src))]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{w}\t{$src, $dst|$dst, $src}",
a few fixes to "addrspace(256) is reference offset of GS segment register". It turns out that there are still several problems with this, will file a bugzilla. llvm-svn: 68749
2009-04-10 02:16:23 +02:00
[(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{l}\t{$src, $dst|$dst, $src}",
a few fixes to "addrspace(256) is reference offset of GS segment register". It turns out that there are still several problems with this, will file a bugzilla. llvm-svn: 68749
2009-04-10 02:16:23 +02:00
[(set GR32:$dst, (loadi32 addr:$src))]>;
Mark load instructions with isLoad = 1. llvm-svn: 41595
2007-08-30 07:49:43 +02:00
}
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{b}\t{$src, $dst|$dst, $src}",
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
[(store GR8:$src, addr:$dst)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{w}\t{$src, $dst|$dst, $src}",
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
[(store GR16:$src, addr:$dst)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mov{l}\t{$src, $dst|$dst, $src}",
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
[(store GR32:$src, addr:$dst)]>;
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-13 18:09:41 +02:00
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. llvm-svn: 98465
2010-03-14 04:48:46 +01:00
/// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. llvm-svn: 108680
2010-07-19 08:14:49 +02:00
let isCodeGenOnly = 1 in {
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. llvm-svn: 98465
2010-03-14 04:48:46 +01:00
let neverHasSideEffects = 1 in
def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
"mov{l}\t{$src, $dst|$dst, $src}", []>;
let mayLoad = 1,
canFoldAsLoad = 1, isReMaterializable = 1 in
def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
"mov{l}\t{$src, $dst|$dst, $src}",
[]>;
let mayStore = 1 in
def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
"mov{l}\t{$src, $dst|$dst, $src}",
[]>;
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. llvm-svn: 108680
2010-07-19 08:14:49 +02:00
}
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. llvm-svn: 98465
2010-03-14 04:48:46 +01:00
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-27 18:41:36 +02:00
// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
// that they can be used for copying and storing h registers, which can't be
// encoded when a REX prefix is present.
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. llvm-svn: 108680
2010-07-19 08:14:49 +02:00
let isCodeGenOnly = 1 in {
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. llvm-svn: 69111
2009-04-15 02:04:23 +02:00
let neverHasSideEffects = 1 in
Fix 80-column violations. llvm-svn: 69204
2009-04-15 21:48:57 +02:00
def MOV8rr_NOREX : I<0x88, MRMDestReg,
(outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. llvm-svn: 69111
2009-04-15 02:04:23 +02:00
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively. llvm-svn: 70461
2009-04-30 02:58:57 +02:00
let mayStore = 1 in
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. llvm-svn: 69111
2009-04-15 02:04:23 +02:00
def MOV8mr_NOREX : I<0x88, MRMDestMem,
(outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively. llvm-svn: 70461
2009-04-30 02:58:57 +02:00
let mayLoad = 1,
The mayHaveSideEffects flag is no longer used. llvm-svn: 97348
2010-02-28 00:47:46 +01:00
canFoldAsLoad = 1, isReMaterializable = 1 in
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-27 18:41:36 +02:00
def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
(outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. llvm-svn: 108680
2010-07-19 08:14:49 +02:00
}
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-13 18:09:41 +02:00
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
//===----------------------------------------------------------------------===//
// Fixed-Register Multiplication and Division Instructions...
//
transition to using let instead of set llvm-svn: 7564
2003-08-04 06:59:56 +02:00
// Extra precision multiplication
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
Wording. llvm-svn: 110618
2010-08-10 00:52:47 +02:00
// AL is really implied by AX, but the registers in Defs must match the
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
// SDNode results (i8, i32).
let Defs = [AL,EFLAGS,AX], Uses = [AL] in
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
Added patterns for 8-bit multiply llvm-svn: 25338
2006-01-15 11:05:20 +01:00
// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted.
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(set AL, (mul AL, GR8:$src)),
(implicit EFLAGS)]>; // AL,AH = AL*GR8
more flags set right llvm-svn: 45860
2008-01-11 08:18:17 +01:00
let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
"mul{w}\t$src",
[]>, OpSize; // AX,DX = AX*GR16
more flags set right llvm-svn: 45860
2008-01-11 08:18:17 +01:00
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
"mul{l}\t$src",
[]>; // EAX,EDX = EAX*GR32
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
let Defs = [AL,EFLAGS,AX], Uses = [AL] in
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"mul{b}\t$src",
Added patterns for 8-bit multiply llvm-svn: 25338
2006-01-15 11:05:20 +01:00
// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted.
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(set AL, (mul AL, (loadi8 addr:$src))),
(implicit EFLAGS)]>; // AL,AH = AL*[mem8]
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let mayLoad = 1, neverHasSideEffects = 1 in {
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
"mul{w}\t$src",
[]>, OpSize; // AX,DX = AX*[mem16]
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
"mul{l}\t$src",
[]>; // EAX,EDX = EAX*[mem32]
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
}
transition to using let instead of set llvm-svn: 7564
2003-08-04 06:59:56 +02:00
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let neverHasSideEffects = 1 in {
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
let Defs = [AL,EFLAGS,AX], Uses = [AL] in
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
// AL,AH = AL*GR8
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
OpSize; // AX,DX = AX*GR16
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
// EAX,EDX = EAX*GR32
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let mayLoad = 1 in {
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
let Defs = [AL,EFLAGS,AX], Uses = [AL] in
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"imul{b}\t$src", []>; // AL,AH = AL*[mem8]
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
PR5886: Make sure IMUL32m is marked as setting EFLAGS, so scheduling doesn't do illegal stuff around it. No testcase because the issue is very fragile. llvm-svn: 92167
2009-12-26 21:08:30 +01:00
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
}
Don't set neverHasSideEffects on x86's divide instructions, since they trap on divide-by-zero, and this side effect is otherwise unmodeled. llvm-svn: 59551
2008-11-18 22:29:14 +01:00
} // neverHasSideEffects
add signed versions of the extra precision multiplies llvm-svn: 21106
2005-04-06 06:19:22 +02:00
transition to using let instead of set llvm-svn: 7564
2003-08-04 06:59:56 +02:00
// unsigned division/remainder
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
let Defs = [AL,EFLAGS,AX], Uses = [AX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"div{b}\t$src", []>;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"div{w}\t$src", []>, OpSize;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"div{l}\t$src", []>;
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let mayLoad = 1 in {
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
let Defs = [AL,EFLAGS,AX], Uses = [AX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"div{b}\t$src", []>;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"div{w}\t$src", []>, OpSize;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
// EDX:EAX/[mem32] = EAX,EDX
def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"div{l}\t$src", []>;
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
}
transition to using let instead of set llvm-svn: 7564
2003-08-04 06:59:56 +02:00
Convert all I<> instructions to asmformat. Delete the 'name' field of all instructions that have asmformats. llvm-svn: 15403
2004-08-01 11:52:59 +02:00
// Signed division/remainder.
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
let Defs = [AL,EFLAGS,AX], Uses = [AX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"idiv{b}\t$src", []>;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"idiv{w}\t$src", []>, OpSize;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"idiv{l}\t$src", []>;
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let mayLoad = 1, mayLoad = 1 in {
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
2010-03-04 21:42:07 +01:00
let Defs = [AL,EFLAGS,AX], Uses = [AX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"idiv{b}\t$src", []>;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"idiv{w}\t$src", []>, OpSize;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
// EDX:EAX/[mem32] = EAX,EDX
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
"idiv{l}\t$src", []>;
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
}
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
//===----------------------------------------------------------------------===//
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
// Two address Instructions.
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
//
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "$src1 = $dst" in {
Each instruction now has both an ImmType and a MemType. This describes the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). llvm-svn: 11967
2004-02-28 23:02:05 +01:00
Add some new instructions. Wheee llvm-svn: 9266
2003-10-19 21:25:35 +02:00
// unary instructions
INC / DEC instructions have shorter code size than ADD32ri8, etc. llvm-svn: 29194
2006-07-19 02:27:29 +02:00
let CodeSize = 2 in {
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EFLAGS] in {
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
"neg{b}\t$dst",
[(set GR8:$dst, (ineg GR8:$src1)),
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
(implicit EFLAGS)]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
"neg{w}\t$dst",
[(set GR16:$dst, (ineg GR16:$src1)),
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
(implicit EFLAGS)]>, OpSize;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
"neg{l}\t$dst",
[(set GR32:$dst, (ineg GR32:$src1)),
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
(implicit EFLAGS)]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
"neg{b}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (ineg (loadi8 addr:$dst)), addr:$dst),
(implicit EFLAGS)]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
"neg{w}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (ineg (loadi16 addr:$dst)), addr:$dst),
(implicit EFLAGS)]>, OpSize;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
"neg{l}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (ineg (loadi32 addr:$dst)), addr:$dst),
(implicit EFLAGS)]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
} // Defs = [EFLAGS]
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
Favors generating "not" over "xor -1". For example. unsigned test(unsigned a) { return ~a; } llvm used to generate: movl $4294967295, %eax xorl 4(%esp), %eax Now it generates: movl 4(%esp), %eax notl %eax It's 3 bytes shorter. llvm-svn: 62661
2009-01-21 03:09:05 +01:00
// Match xor -1 to not. Favors these over a move imm + xor to save code size.
let AddedComplexity = 15 in {
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
"not{b}\t$dst",
[(set GR8:$dst, (not GR8:$src1))]>;
def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
"not{w}\t$dst",
[(set GR16:$dst, (not GR16:$src1))]>, OpSize;
def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
"not{l}\t$dst",
[(set GR32:$dst, (not GR32:$src1))]>;
Favors generating "not" over "xor -1". For example. unsigned test(unsigned a) { return ~a; } llvm used to generate: movl $4294967295, %eax xorl 4(%esp), %eax Now it generates: movl 4(%esp), %eax notl %eax It's 3 bytes shorter. llvm-svn: 62661
2009-01-21 03:09:05 +01:00
}
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
"not{b}\t$dst",
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. llvm-svn: 24688
2005-12-13 02:57:51 +01:00
[(store (not (loadi8 addr:$dst)), addr:$dst)]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
"not{w}\t$dst",
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. llvm-svn: 24688
2005-12-13 02:57:51 +01:00
[(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
"not{l}\t$dst",
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. llvm-svn: 24688
2005-12-13 02:57:51 +01:00
[(store (not (loadi32 addr:$dst)), addr:$dst)]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
INC / DEC instructions have shorter code size than ADD32ri8, etc. llvm-svn: 29194
2006-07-19 02:27:29 +02:00
} // CodeSize
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
* Added X86 store patterns. * Added X86 dec patterns. llvm-svn: 24654
2005-12-10 01:48:20 +01:00
// TODO: inc/dec is slow for P4, but fast for Pentium-M.
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EFLAGS] in {
INC / DEC instructions have shorter code size than ADD32ri8, etc. llvm-svn: 29194
2006-07-19 02:27:29 +02:00
let CodeSize = 2 in
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
"inc{b}\t$dst",
[(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
Switch INC8r to defining its pattern in terms of X86inc_flag and defining the add pattern with Pat<>, eliminating a use of parallel. llvm-svn: 99375
2010-03-24 02:02:12 +01:00
INC / DEC instructions have shorter code size than ADD32ri8, etc. llvm-svn: 29194
2006-07-19 02:27:29 +02:00
let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
"inc{w}\t$dst",
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
Committing X86-64 support. llvm-svn: 30177
2006-09-08 08:48:29 +02:00
OpSize, Requires<[In32BitMode]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
"inc{l}\t$dst",
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
Requires<[In32BitMode]>;
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
}
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "", CodeSize = 2 in {
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (add (loadi8 addr:$dst), 1), addr:$dst),
(implicit EFLAGS)]>;
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (add (loadi16 addr:$dst), 1), addr:$dst),
(implicit EFLAGS)]>,
Local spiller optimization: Turn a store folding instruction into a load folding instruction. e.g. xorl %edi, %eax movl %eax, -32(%ebp) movl -36(%ebp), %eax orl %eax, -32(%ebp) => xorl %edi, %eax orl -36(%ebp), %eax mov %eax, -32(%ebp) This enables the unfolding optimization for a subsequent instruction which will also eliminate the newly introduced store instruction. llvm-svn: 43192
2007-10-19 23:23:22 +02:00
OpSize, Requires<[In32BitMode]>;
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (add (loadi32 addr:$dst), 1), addr:$dst),
(implicit EFLAGS)]>,
Local spiller optimization: Turn a store folding instruction into a load folding instruction. e.g. xorl %edi, %eax movl %eax, -32(%ebp) movl -36(%ebp), %eax orl %eax, -32(%ebp) => xorl %edi, %eax orl -36(%ebp), %eax mov %eax, -32(%ebp) This enables the unfolding optimization for a subsequent instruction which will also eliminate the newly introduced store instruction. llvm-svn: 43192
2007-10-19 23:23:22 +02:00
Requires<[In32BitMode]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = "", CodeSize = 2
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
INC / DEC instructions have shorter code size than ADD32ri8, etc. llvm-svn: 29194
2006-07-19 02:27:29 +02:00
let CodeSize = 2 in
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
"dec{b}\t$dst",
[(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
INC / DEC instructions have shorter code size than ADD32ri8, etc. llvm-svn: 29194
2006-07-19 02:27:29 +02:00
let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
"dec{w}\t$dst",
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
Committing X86-64 support. llvm-svn: 30177
2006-09-08 08:48:29 +02:00
OpSize, Requires<[In32BitMode]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
"dec{l}\t$dst",
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
Requires<[In32BitMode]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // CodeSize = 2
Get rid of the Im8, Im16, Im32 classes, converting more instructions over to asmprintergeneration llvm-svn: 15650
2004-08-11 06:31:00 +02:00
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "", CodeSize = 2 in {
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (add (loadi8 addr:$dst), -1), addr:$dst),
(implicit EFLAGS)]>;
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (add (loadi16 addr:$dst), -1), addr:$dst),
(implicit EFLAGS)]>,
Local spiller optimization: Turn a store folding instruction into a load folding instruction. e.g. xorl %edi, %eax movl %eax, -32(%ebp) movl -36(%ebp), %eax orl %eax, -32(%ebp) => xorl %edi, %eax orl -36(%ebp), %eax mov %eax, -32(%ebp) This enables the unfolding optimization for a subsequent instruction which will also eliminate the newly introduced store instruction. llvm-svn: 43192
2007-10-19 23:23:22 +02:00
OpSize, Requires<[In32BitMode]>;
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (add (loadi32 addr:$dst), -1), addr:$dst),
(implicit EFLAGS)]>,
Local spiller optimization: Turn a store folding instruction into a load folding instruction. e.g. xorl %edi, %eax movl %eax, -32(%ebp) movl -36(%ebp), %eax orl %eax, -32(%ebp) => xorl %edi, %eax orl -36(%ebp), %eax mov %eax, -32(%ebp) This enables the unfolding optimization for a subsequent instruction which will also eliminate the newly introduced store instruction. llvm-svn: 43192
2007-10-19 23:23:22 +02:00
Requires<[In32BitMode]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = "", CodeSize = 2
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
} // Defs = [EFLAGS]
Each instruction now has both an ImmType and a MemType. This describes the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). llvm-svn: 11967
2004-02-28 23:02:05 +01:00
// Logical operators...
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EFLAGS] in {
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
def AND8rr : I<0x20, MRMDestReg,
(outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
"and{b}\t{$src2, $dst|$dst, $src2}",
[(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
def AND16rr : I<0x21, MRMDestReg,
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"and{w}\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
GR16:$src2))]>, OpSize;
def AND32rr : I<0x21, MRMDestReg,
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"and{l}\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
GR32:$src2))]>;
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
}
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
// AND instructions with the destination register in REG and the source register
// in R/M. Included for the disassembler.
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
let isCodeGenOnly = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"and{b}\t{$src2, $dst|$dst, $src2}", []>;
def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
"and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"and{l}\t{$src2, $dst|$dst, $src2}", []>;
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND8rm : I<0x22, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{b}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
(loadi8 addr:$src2)))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND16rm : I<0x23, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
(loadi16 addr:$src2)))]>,
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND32rm : I<0x23, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
(loadi32 addr:$src2)))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND8ri : Ii8<0x80, MRM4r,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{b}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
imm:$src2))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND16ri : Ii16<0x81, MRM4r,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
imm:$src2))]>, OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND32ri : Ii32<0x81, MRM4r,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
imm:$src2))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND16ri8 : Ii8<0x83, MRM4r,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
i16immSExt8:$src2))]>,
Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc. llvm-svn: 24683
2005-12-13 01:14:11 +01:00
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND32ri8 : Ii8<0x83, MRM4r,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
i32immSExt8:$src2))]>;
X86 instructions that read-modify-write memory are not LLVM two-address instructions. llvm-svn: 15651
2004-08-11 07:07:25 +02:00
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND8mr : I<0x20, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i8mem :$dst, GR8 :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{b}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (and (load addr:$dst), GR8:$src), addr:$dst),
(implicit EFLAGS)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND16mr : I<0x21, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i16mem:$dst, GR16:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (and (load addr:$dst), GR16:$src), addr:$dst),
(implicit EFLAGS)]>,
Add and, or, and xor patterns which fold load + stores. llvm-svn: 24687
2005-12-13 02:41:36 +01:00
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND32mr : I<0x21, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i32mem:$dst, GR32:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (and (load addr:$dst), GR32:$src), addr:$dst),
(implicit EFLAGS)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND8mi : Ii8<0x80, MRM4m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i8mem :$dst, i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{b}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND16mi : Ii16<0x81, MRM4m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i16mem:$dst, i16imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>,
Add and, or, and xor patterns which fold load + stores. llvm-svn: 24687
2005-12-13 02:41:36 +01:00
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND32mi : Ii32<0x81, MRM4m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i32mem:$dst, i32imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND16mi8 : Ii8<0x83, MRM4m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i16mem:$dst, i16i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>,
Add and, or, and xor patterns which fold load + stores. llvm-svn: 24687
2005-12-13 02:41:36 +01:00
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def AND32mi8 : Ii8<0x83, MRM4m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i32mem:$dst, i32i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"and{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>;
Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. Added a 64-bit ADD %RAX, imm32 instruction. Added all 4 forms for AND %rAX, imm and CMP %rAX, imm. llvm-svn: 80746
2009-09-02 02:55:49 +02:00
def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
"and{b}\t{$src, %al|%al, $src}", []>;
def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
"and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
"and{l}\t{$src, %eax|%eax, $src}", []>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
X86 instructions that read-modify-write memory are not LLVM two-address instructions. llvm-svn: 15651
2004-08-11 07:07:25 +02:00
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
(ins GR8 :$src1, GR8 :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{b}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
OpSize;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
// OR instructions with the destination register in REG and the source register
// in R/M. Included for the disassembler.
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
let isCodeGenOnly = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"or{b}\t{$src2, $dst|$dst, $src2}", []>;
def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
"or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"or{l}\t{$src2, $dst|$dst, $src2}", []>;
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
(ins GR8 :$src1, i8mem :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{b}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
(load addr:$src2)))]>;
def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
(ins GR16:$src1, i16mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
(load addr:$src2)))]>,
OpSize;
def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
(ins GR32:$src1, i32mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
(load addr:$src2)))]>;
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
(ins GR8 :$src1, i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{b}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
(ins GR16:$src1, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
imm:$src2))]>, OpSize;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
(ins GR32:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
imm:$src2))]>;
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
(ins GR16:$src1, i16i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
i16immSExt8:$src2))]>, OpSize;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
(ins GR32:$src1, i32i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
i32immSExt8:$src2))]>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{b}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (or (load addr:$dst), GR8:$src), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (or (load addr:$dst), GR16:$src), addr:$dst),
(implicit EFLAGS)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (or (load addr:$dst), GR32:$src), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{b}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>,
Add and, or, and xor patterns which fold load + stores. llvm-svn: 24687
2005-12-13 02:41:36 +01:00
OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>,
Add and, or, and xor patterns which fold load + stores. llvm-svn: 24687
2005-12-13 02:41:36 +01:00
OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"or{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>;
Added ADC, SUB, SBB, and OR instructions that operate on rAX and an immediate. llvm-svn: 81551
2009-09-11 21:01:56 +02:00
def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
"or{b}\t{$src, %al|%al, $src}", []>;
def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
"or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
"or{l}\t{$src, %eax|%eax, $src}", []>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are. llvm-svn: 52454
2008-06-18 10:13:07 +02:00
let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the like. llvm-svn: 51662
2008-05-29 03:02:09 +02:00
def XOR8rr : I<0x30, MRMDestReg,
(outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
"xor{b}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
GR8:$src2))]>;
Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the like. llvm-svn: 51662
2008-05-29 03:02:09 +02:00
def XOR16rr : I<0x31, MRMDestReg,
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"xor{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
GR16:$src2))]>, OpSize;
Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the like. llvm-svn: 51662
2008-05-29 03:02:09 +02:00
def XOR32rr : I<0x31, MRMDestReg,
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"xor{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
GR32:$src2))]>;
XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are. llvm-svn: 52454
2008-06-18 10:13:07 +02:00
} // isCommutable = 1
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
// XOR instructions with the destination register in REG and the source register
// in R/M. Included for the disassembler.
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
let isCodeGenOnly = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"xor{b}\t{$src2, $dst|$dst, $src2}", []>;
def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
"xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"xor{l}\t{$src2, $dst|$dst, $src2}", []>;
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
def XOR8rm : I<0x32, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{b}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
(load addr:$src2)))]>;
def XOR16rm : I<0x33, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
(load addr:$src2)))]>,
Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the like. llvm-svn: 51662
2008-05-29 03:02:09 +02:00
OpSize;
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
def XOR32rm : I<0x33, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
(load addr:$src2)))]>;
def XOR8ri : Ii8<0x80, MRM6r,
(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
"xor{b}\t{$src2, $dst|$dst, $src2}",
[(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
def XOR16ri : Ii16<0x81, MRM6r,
(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
"xor{w}\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
imm:$src2))]>, OpSize;
XOR?RI instructions aren't as cheap as moves. llvm-svn: 51664
2008-05-29 05:46:36 +02:00
def XOR32ri : Ii32<0x81, MRM6r,
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
"xor{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
imm:$src2))]>;
XOR?RI instructions aren't as cheap as moves. llvm-svn: 51664
2008-05-29 05:46:36 +02:00
def XOR16ri8 : Ii8<0x83, MRM6r,
(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
"xor{w}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
i16immSExt8:$src2))]>,
XOR?RI instructions aren't as cheap as moves. llvm-svn: 51664
2008-05-29 05:46:36 +02:00
OpSize;
def XOR32ri8 : Ii8<0x83, MRM6r,
(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
"xor{l}\t{$src2, $dst|$dst, $src2}",
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
[(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
i32immSExt8:$src2))]>;
Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the like. llvm-svn: 51662
2008-05-29 03:02:09 +02:00
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def XOR8mr : I<0x30, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i8mem :$dst, GR8 :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{b}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (xor (load addr:$dst), GR8:$src), addr:$dst),
(implicit EFLAGS)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def XOR16mr : I<0x31, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i16mem:$dst, GR16:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (xor (load addr:$dst), GR16:$src), addr:$dst),
(implicit EFLAGS)]>,
Add and, or, and xor patterns which fold load + stores. llvm-svn: 24687
2005-12-13 02:41:36 +01:00
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def XOR32mr : I<0x31, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i32mem:$dst, GR32:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (xor (load addr:$dst), GR32:$src), addr:$dst),
(implicit EFLAGS)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def XOR8mi : Ii8<0x80, MRM6m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i8mem :$dst, i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{b}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def XOR16mi : Ii16<0x81, MRM6m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i16mem:$dst, i16imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>,
Add and, or, and xor patterns which fold load + stores. llvm-svn: 24687
2005-12-13 02:41:36 +01:00
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def XOR32mi : Ii32<0x81, MRM6m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i32mem:$dst, i32imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
(implicit EFLAGS)]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def XOR16mi8 : Ii8<0x83, MRM6m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i16mem:$dst, i16i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{w}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>,
Add and, or, and xor patterns which fold load + stores. llvm-svn: 24687
2005-12-13 02:41:36 +01:00
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def XOR32mi8 : Ii8<0x83, MRM6m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i32mem:$dst, i32i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"xor{l}\t{$src, $dst|$dst, $src}",
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. llvm-svn: 65965
2009-03-03 20:53:46 +01:00
[(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>;
Added XOR instructions for rAX and immediates of various widths. llvm-svn: 81458
2009-09-10 21:52:26 +02:00
eliminate a bunch more parallels now that scheduling handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
2010-03-25 06:44:01 +01:00
def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
"xor{b}\t{$src, %al|%al, $src}", []>;
def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
"xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
"xor{l}\t{$src, %eax|%eax, $src}", []>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
} // Defs = [EFLAGS]
Add some new instructions. Wheee llvm-svn: 9266
2003-10-19 21:25:35 +02:00
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
// Arithmetic.
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EFLAGS] in {
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Register-Register Addition
def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
(ins GR8 :$src1, GR8 :$src2),
"add{b}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Register-Register Addition
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
GR16:$src2))]>, OpSize;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
GR32:$src2))]>;
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
} // end isConvertibleToThreeAddress
} // end isCommutable
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher. llvm-svn: 98098
2010-03-09 23:50:46 +01:00
// These are alternate spellings for use by the disassembler, we mark them as
// code gen only to ensure they aren't matched by the assembler.
let isCodeGenOnly = 1 in {
def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"add{b}\t{$src2, $dst|$dst, $src2}", []>;
def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
"add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
Fix ADD32rr_alt instruction encoding bug. Patch by Marius Wachtler. llvm-svn: 100480
2010-04-06 00:21:09 +02:00
def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher. llvm-svn: 98098
2010-03-09 23:50:46 +01:00
"add{l}\t{$src2, $dst|$dst, $src2}", []>;
}
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Register-Memory Addition
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
(ins GR8 :$src1, i8mem :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{b}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
(load addr:$src2)))]>;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
(ins GR16:$src1, i16mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
(load addr:$src2)))]>, OpSize;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
(load addr:$src2)))]>;
Added register-to-register ADD instructions to the Intel tables, where the source operand is specified by the R/M field and the destination operand by the Reg field. llvm-svn: 81914
2009-09-15 22:53:57 +02:00
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Register-Integer Addition
def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
"add{b}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR8:$dst, EFLAGS,
(X86add_flag GR8:$src1, imm:$src2))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Register-Integer Addition
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
(ins GR16:$src1, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
(ins GR32:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86add_flag GR32:$src1, imm:$src2))]>;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
(ins GR16:$src1, i16i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
(ins GR32:$src1, i32i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
- Use exact-width integer types, e.g. int32_t, to avoid confusion. - Fix a couple of minor bugs in i16immSExt8 and i16immZExt8. - Added loadiPTR fragment used for indirect jumps and calls. llvm-svn: 28392
2006-05-19 20:40:54 +02:00
}
Get rid of the Im8, Im16, Im32 classes, converting more instructions over to asmprintergeneration llvm-svn: 15650
2004-08-11 06:31:00 +02:00
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Memory-Register Addition
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{b}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (add (load addr:$dst), GR8:$src2), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{w}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (add (load addr:$dst), GR16:$src2), addr:$dst),
(implicit EFLAGS)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{l}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (add (load addr:$dst), GR32:$src2), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{b}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{w}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
(implicit EFLAGS)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{l}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{w}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (add (load addr:$dst), i16immSExt8:$src2),
addr:$dst),
(implicit EFLAGS)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"add{l}\t{$src2, $dst|$dst, $src2}",
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
[(store (add (load addr:$dst), i32immSExt8:$src2),
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
addr:$dst),
(implicit EFLAGS)]>;
Added ADD instructions with rAX as one parameter to the Intel instruction tables. llvm-svn: 78721
2009-08-11 23:26:06 +02:00
// addition to rAX
def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. Added a 64-bit ADD %RAX, imm32 instruction. Added all 4 forms for AND %rAX, imm and CMP %rAX, imm. llvm-svn: 80746
2009-09-02 02:55:49 +02:00
"add{b}\t{$src, %al|%al, $src}", []>;
Added ADD instructions with rAX as one parameter to the Intel instruction tables. llvm-svn: 78721
2009-08-11 23:26:06 +02:00
def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. Added a 64-bit ADD %RAX, imm32 instruction. Added all 4 forms for AND %rAX, imm and CMP %rAX, imm. llvm-svn: 80746
2009-09-02 02:55:49 +02:00
"add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
Added ADD instructions with rAX as one parameter to the Intel instruction tables. llvm-svn: 78721
2009-08-11 23:26:06 +02:00
def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. Added a 64-bit ADD %RAX, imm32 instruction. Added all 4 forms for AND %rAX, imm and CMP %rAX, imm. llvm-svn: 80746
2009-09-02 02:55:49 +02:00
"add{l}\t{$src, %eax|%eax, $src}", []>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
ADC and SBB uses EFLAGS. llvm-svn: 42640
2007-10-05 19:59:57 +02:00
let Uses = [EFLAGS] in {
ADC and IMUL are also commutable. llvm-svn: 19264
2005-01-03 02:27:59 +01:00
let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
"adc{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
"adc{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"adc{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
ADC and IMUL are also commutable. llvm-svn: 19264
2005-01-03 02:27:59 +01:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
let isCodeGenOnly = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"adc{b}\t{$src2, $dst|$dst, $src2}", []>;
def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
"adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"adc{l}\t{$src2, $dst|$dst, $src2}", []>;
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
(ins GR8:$src1, i8mem:$src2),
"adc{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
(ins GR16:$src1, i16mem:$src2),
"adc{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
Add OpSize to 16-bit ADC and SBB. llvm-svn: 72045
2009-05-18 23:41:59 +02:00
OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"adc{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
"adc{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
(ins GR16:$src1, i16imm:$src2),
"adc{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
(ins GR16:$src1, i16i8imm:$src2),
"adc{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
(ins GR32:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"adc{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
(ins GR32:$src1, i32i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"adc{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
Get rid of the Im8, Im16, Im32 classes, converting more instructions over to asmprintergeneration llvm-svn: 15650
2004-08-11 06:31:00 +02:00
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
"adc{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
"adc{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
OpSize;
def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"adc{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
"adc{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
"adc{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
OpSize;
def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
"adc{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
OpSize;
def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"adc{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"adc{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
Added ADC, SUB, SBB, and OR instructions that operate on rAX and an immediate. llvm-svn: 81551
2009-09-11 21:01:56 +02:00
def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
"adc{b}\t{$src, %al|%al, $src}", []>;
def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
"adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
"adc{l}\t{$src, %eax|%eax, $src}", []>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
ADC and SBB uses EFLAGS. llvm-svn: 42640
2007-10-05 19:59:57 +02:00
} // Uses = [EFLAGS]
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Register-Register Subtraction
def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"sub{b}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR8:$dst, EFLAGS,
(X86sub_flag GR8:$src1, GR8:$src2))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
"sub{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
"sub{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86sub_flag GR32:$src1, GR32:$src2))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
let isCodeGenOnly = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"sub{b}\t{$src2, $dst|$dst, $src2}", []>;
def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
"sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"sub{l}\t{$src2, $dst|$dst, $src2}", []>;
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Register-Memory Subtraction
def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
(ins GR8 :$src1, i8mem :$src2),
"sub{b}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR8:$dst, EFLAGS,
(X86sub_flag GR8:$src1, (load addr:$src2)))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
(ins GR16:$src1, i16mem:$src2),
"sub{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
"sub{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86sub_flag GR32:$src1, (load addr:$src2)))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Register-Integer Subtraction
def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
(ins GR8:$src1, i8imm:$src2),
"sub{b}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR8:$dst, EFLAGS,
(X86sub_flag GR8:$src1, imm:$src2))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
(ins GR16:$src1, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
(ins GR32:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86sub_flag GR32:$src1, imm:$src2))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
(ins GR16:$src1, i16i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
(ins GR32:$src1, i32i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Memory-Register Subtraction
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{b}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{w}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
(implicit EFLAGS)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{l}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
(implicit EFLAGS)]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
// Memory-Integer Subtraction
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{b}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{w}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
(implicit EFLAGS)]>, OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{l}\t{$src2, $dst|$dst, $src2}",
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
[(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
(implicit EFLAGS)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{w}\t{$src2, $dst|$dst, $src2}",
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
[(store (sub (load addr:$dst), i16immSExt8:$src2),
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
addr:$dst),
(implicit EFLAGS)]>, OpSize;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sub{l}\t{$src2, $dst|$dst, $src2}",
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
[(store (sub (load addr:$dst), i32immSExt8:$src2),
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
addr:$dst),
(implicit EFLAGS)]>;
Added ADC, SUB, SBB, and OR instructions that operate on rAX and an immediate. llvm-svn: 81551
2009-09-11 21:01:56 +02:00
def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
"sub{b}\t{$src, %al|%al, $src}", []>;
def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
"sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
"sub{l}\t{$src, %eax|%eax, $src}", []>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
ADC and SBB uses EFLAGS. llvm-svn: 42640
2007-10-05 19:59:57 +02:00
let Uses = [EFLAGS] in {
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
(ins GR8:$src1, GR8:$src2),
"sbb{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
"sbb{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sbb{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
Add some new instructions. Fix the asm string for sbb32rr llvm-svn: 16759
2004-10-06 06:01:02 +02:00
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
let Constraints = "" in {
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
"sbb{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
"sbb{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
Add OpSize to 16-bit ADC and SBB. llvm-svn: 72045
2009-05-18 23:41:59 +02:00
OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sbb{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
fix incorrect encoding of SBB8mi that Kevin noticed. llvm-svn: 95448
2010-02-05 23:56:11 +01:00
def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
"sbb{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
"sbb{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
Add OpSize to 16-bit ADC and SBB. llvm-svn: 72045
2009-05-18 23:41:59 +02:00
OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
"sbb{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
Add OpSize to 16-bit ADC and SBB. llvm-svn: 72045
2009-05-18 23:41:59 +02:00
OpSize;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sbb{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sbb{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
Added ADC, SUB, SBB, and OR instructions that operate on rAX and an immediate. llvm-svn: 81551
2009-09-11 21:01:56 +02:00
def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
"sbb{b}\t{$src, %al|%al, $src}", []>;
def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
"sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
"sbb{l}\t{$src, %eax|%eax, $src}", []>;
Finish ripping isTwoAddress out of X86. Some mindless formatting and operand renaming to help. The giant turn the constraints on and selectively turn it off should probably be inverted at some point since it's just largely 50/50. llvm-svn: 106367
2010-06-19 02:37:40 +02:00
} // Constraints = ""
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
let isCodeGenOnly = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
"sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 00:21:28 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
"sbb{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
(ins GR16:$src1, i16mem:$src2),
"sbb{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
Add OpSize to 16-bit ADC and SBB. llvm-svn: 72045
2009-05-18 23:41:59 +02:00
OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sbb{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
"sbb{b}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
(ins GR16:$src1, i16imm:$src2),
"sbb{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
(ins GR16:$src1, i16i8imm:$src2),
"sbb{w}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
OpSize;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
(ins GR32:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sbb{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
Fill in the missing patterns for ADC and SBB. Some comment cleanup. llvm-svn: 72022
2009-05-18 19:44:15 +02:00
def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
(ins GR32:$src1, i32i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"sbb{l}\t{$src2, $dst|$dst, $src2}",
Revert 72707 and 72709, for the moment. llvm-svn: 72712
2009-06-02 05:12:52 +02:00
[(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
ADC and SBB uses EFLAGS. llvm-svn: 42640
2007-10-05 19:59:57 +02:00
} // Uses = [EFLAGS]
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
} // Defs = [EFLAGS]
A big X86 instruction rename. The instructions are renamed to make their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
2004-02-29 09:50:03 +01:00
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EFLAGS] in {
ADC and IMUL are also commutable. llvm-svn: 19264
2005-01-03 02:27:59 +01:00
let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
// Register-Register Signed Integer Multiply
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
ADC and IMUL are also commutable. llvm-svn: 19264
2005-01-03 02:27:59 +01:00
}
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
// Register-Memory Signed Integer Multiply
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 01:56:36 +01:00
def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
(ins GR16:$src1, i16mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{w}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86smul_flag GR16:$src1, (load addr:$src2)))]>,
TB, OpSize;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{l}\t{$src2, $dst|$dst, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
} // Defs = [EFLAGS]
Each instruction now has both an ImmType and a MemType. This describes the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). llvm-svn: 11967
2004-02-28 23:02:05 +01:00
} // end Two Address instructions
Rename the IMULri* instructions to IMULrri, as they are actually three address instructions. Add forms of these instructions that read from memory llvm-svn: 11518
2004-02-17 05:26:43 +01:00
Nuke the Im*i* patterns, by asmprintergenifying all users. llvm-svn: 15652
2004-08-11 07:31:07 +02:00
// Suprisingly enough, these are not two address instructions!
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EFLAGS] in {
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
// Register-Integer Signed Integer Multiply
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86smul_flag GR32:$src1, imm:$src2))]>;
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
OpSize;
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
- Use patterns instead of creating completely new instruction matching patterns, which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! llvm-svn: 60963
2008-12-12 22:15:41 +01:00
// Memory-Integer Signed Integer Multiply
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86smul_flag (load addr:$src1), imm:$src2))]>,
OpSize;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86smul_flag (load addr:$src1), imm:$src2))]>;
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR16:$dst, EFLAGS,
(X86smul_flag (load addr:$src1),
i16immSExt8:$src2))]>, OpSize;
X86 integer register classes naming changes. Make them consistent with FP, vector classes. llvm-svn: 28324
2006-05-16 09:21:53 +02:00
def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
eliminate almost all the rest of the x86-32 parallels. llvm-svn: 99686
2010-03-27 01:45:04 +01:00
[(set GR32:$dst, EFLAGS,
(X86smul_flag (load addr:$src1),
i32immSExt8:$src2))]>;
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
} // Defs = [EFLAGS]
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
Each instruction now has both an ImmType and a MemType. This describes the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). llvm-svn: 11967
2004-02-28 23:02:05 +01:00
//===----------------------------------------------------------------------===//
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
// Test instructions are just like AND, except they don't generate a result.
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
//
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
let Defs = [EFLAGS] in {
Two changes here: 1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP. 2. Set the isCommutable and isPromotableTo3Address bits on several instructions. llvm-svn: 19246
2005-01-02 03:35:46 +01:00
let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
X86: Fix encoding for TEST{8,16,32}rr. llvm-svn: 97982
2010-03-08 22:10:36 +01:00
def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
"test{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
X86: Fix encoding for TEST{8,16,32}rr. llvm-svn: 97982
2010-03-08 22:10:36 +01:00
def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
"test{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
0))]>,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
OpSize;
X86: Fix encoding for TEST{8,16,32}rr. llvm-svn: 97982
2010-03-08 22:10:36 +01:00
def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
"test{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
0))]>;
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
}
Added TEST %rAX, $imm instructions to the Intel tables. These are required for the X86 disassembler. llvm-svn: 80696
2009-09-01 20:14:18 +02:00
def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
"test{b}\t{$src, %al|%al, $src}", []>;
def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
"test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
"test{l}\t{$src, %eax|%eax, $src}", []>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
"test{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
0))]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
"test{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and GR16:$src1,
(loadi16 addr:$src2)), 0))]>, OpSize;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
"test{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and GR32:$src1,
(loadi32 addr:$src2)), 0))]>;
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins GR8:$src1, i8imm:$src2),
"test{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins GR16:$src1, i16imm:$src2),
"test{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
OpSize;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins GR32:$src1, i32imm:$src2),
"test{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins i8mem:$src1, i8imm:$src2),
"test{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
0))]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins i16mem:$src1, i16imm:$src2),
"test{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
0))]>, OpSize;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins i32mem:$src1, i32imm:$src2),
"test{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
0))]>;
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
} // Defs = [EFLAGS]
Each instruction now has both an ImmType and a MemType. This describes the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). llvm-svn: 11967
2004-02-28 23:02:05 +01:00
// Condition code ops, incl. set if equal/not equal/...
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 08:59:24 +01:00
let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
Each instruction now has both an ImmType and a MemType. This describes the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). llvm-svn: 11967
2004-02-28 23:02:05 +01:00
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-03 23:54:21 +02:00
// Integer comparisons
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-14 23:48:26 +02:00
let Defs = [EFLAGS] in {
Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. Added a 64-bit ADD %RAX, imm32 instruction. Added all 4 forms for AND %rAX, imm and CMP %rAX, imm. llvm-svn: 80746
2009-09-02 02:55:49 +02:00
def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
"cmp{b}\t{$src, %al|%al, $src}", []>;
def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
"cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
"cmp{l}\t{$src, %eax|%eax, $src}", []>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP8rr : I<0x38, MRMDestReg,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR8 :$src1, GR8 :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP16rr : I<0x39, MRMDestReg,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR16:$src1, GR16:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP32rr : I<0x39, MRMDestReg,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR32:$src1, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP8mr : I<0x38, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i8mem :$src1, GR8 :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP16mr : I<0x39, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i16mem:$src1, GR16:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP32mr : I<0x39, MRMDestMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i32mem:$src1, GR32:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP8rm : I<0x3A, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR8 :$src1, i8mem :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP16rm : I<0x3B, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR16:$src1, i16mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP32rm : I<0x3B, MRMSrcMem,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR32:$src1, i32mem:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher. llvm-svn: 98097
2010-03-09 23:50:40 +01:00
// These are alternate spellings for use by the disassembler, we mark them as
// code gen only to ensure they aren't matched by the assembler.
let isCodeGenOnly = 1 in {
def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
"cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
"cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
"cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
}
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP8ri : Ii8<0x80, MRM7r,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR8:$src1, i8imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP16ri : Ii16<0x81, MRM7r,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR16:$src1, i16imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP32ri : Ii32<0x81, MRM7r,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins GR32:$src1, i32imm:$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-03 22:35:00 +02:00
def CMP8mi : Ii8 <0x80, MRM7m,
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
(outs), (ins i8mem :$src1, i8imm :$src2),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-07-31 22:11:57 +02:00
"cmp{b}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def CMP16mi : Ii16<0x81, MRM7m,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins i16mem:$src1, i16imm:$src2),
"cmp{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
OpSize;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def CMP32mi : Ii32<0x81, MRM7m,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins i32mem:$src1, i32imm:$src2),
"cmp{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def CMP16ri8 : Ii8<0x83, MRM7r,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins GR16:$src1, i16i8imm:$src2),
"cmp{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
OpSize;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def CMP16mi8 : Ii8<0x83, MRM7m,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins i16mem:$src1, i16i8imm:$src2),
"cmp{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (loadi16 addr:$src1),
i16immSExt8:$src2))]>, OpSize;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def CMP32mi8 : Ii8<0x83, MRM7m,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins i32mem:$src1, i32i8imm:$src2),
"cmp{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp (loadi32 addr:$src1),
i32immSExt8:$src2))]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 02:00:36 +02:00
def CMP32ri8 : Ii8<0x83, MRM7r,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
(outs), (ins GR32:$src1, i32i8imm:$src2),
"cmp{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 03:57:46 +02:00
} // Defs = [EFLAGS]
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-23 23:45:23 +01:00
// Bit tests.
// TODO: BTC, BTR, and BTS
let Defs = [EFLAGS] in {
Fix a few more JIT encoding issues in the BT instructions. llvm-svn: 62179
2009-01-13 21:32:45 +01:00
def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-23 23:45:23 +01:00
"bt{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
Fix a few more JIT encoding issues in the BT instructions. llvm-svn: 62179
2009-01-13 21:32:45 +01:00
def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-23 23:45:23 +01:00
"bt{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
Disable the register+memory forms of the bt instructions for now. Thanks to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. llvm-svn: 62194
2009-01-14 00:23:30 +01:00
// Unlike with the register+register form, the memory+register form of the
// bt instruction does not ignore the high bits of the index. From ISel's
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
// perspective, this is pretty bizarre. Make these instructions disassembly
// only for now.
def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
Disable the register+memory forms of the bt instructions for now. Thanks to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. llvm-svn: 62194
2009-01-14 00:23:30 +01:00
// [(X86bt (loadi16 addr:$src1), GR16:$src2),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
// (implicit EFLAGS)]
[]
>, OpSize, TB, Requires<[FastBTMem]>;
def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
"bt{l}\t{$src2, $src1|$src1, $src2}",
Disable the register+memory forms of the bt instructions for now. Thanks to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. llvm-svn: 62194
2009-01-14 00:23:30 +01:00
// [(X86bt (loadi32 addr:$src1), GR32:$src2),
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
// (implicit EFLAGS)]
[]
>, TB, Requires<[FastBTMem]>;
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-13 21:33:23 +01:00
def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
OpSize, TB;
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-13 21:33:23 +01:00
def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
"bt{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-13 21:33:23 +01:00
// Note that these instructions don't need FastBTMem because that
// only applies when the other operand is in a register. When it's
// an immediate, bt is still fast.
def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
]>, OpSize, TB;
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-13 21:33:23 +01:00
def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
"bt{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 01:01:11 +01:00
[(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
]>, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
"btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
"btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
"btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
"btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
"btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
"btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
"btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
"btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
"btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
"btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
"bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
"bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
"bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
"bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-23 23:45:23 +01:00
} // Defs = [EFLAGS]
Long live the exception handling! This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
2007-07-14 16:06:15 +02:00
Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet llvm-svn: 47430
2008-02-21 07:45:13 +01:00
//===----------------------------------------------------------------------===//
// Atomic support
//
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. llvm-svn: 47795
2008-03-01 14:37:02 +01:00
Custom lower the memory barrier instructions and add support for lowering without sse2. Add a couple of new testcases. Fixes a few libgomp tests and latent bugs. Remove a few todos. llvm-svn: 109078
2010-07-22 04:48:34 +02:00
xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed. llvm-svn: 49946
2008-04-19 03:20:30 +02:00
// Atomic swap. These are just normal xchg instructions. But since a memory
// operand is referenced, the atomicity is ensured.
xchg does not modify FLAGS. llvm-svn: 54411
2008-08-06 17:52:50 +02:00
let Constraints = "$val = $dst" in {
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
"xchg{b}\t{$val, $ptr|$ptr, $val}",
[(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
(ins GR16:$val, i16mem:$ptr),
xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed. llvm-svn: 49946
2008-04-19 03:20:30 +02:00
"xchg{w}\t{$val, $ptr|$ptr, $val}",
[(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
OpSize;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$val, i32mem:$ptr),
"xchg{l}\t{$val, $ptr|$ptr, $val}",
[(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
(ins GR64:$val,i64mem:$ptr),
"xchg{q}\t{$val, $ptr|$ptr, $val}",
[(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
"xchg{b}\t{$val, $src|$src, $val}", []>;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
"xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
"xchg{l}\t{$val, $src|$src, $val}", []>;
def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
"xchg{q}\t{$val, $src|$src, $val}", []>;
xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed. llvm-svn: 49946
2008-04-19 03:20:30 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
"xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
"xchg{l}\t{$src, %eax|%eax, $src}", []>;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
"xchg{q}\t{$src, %rax|%rax, $src}", []>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. llvm-svn: 47795
2008-03-01 14:37:02 +01:00
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
"xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
"xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
"xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
"xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Add mayLoad and mayStore flags to instructions which missed them. llvm-svn: 103776
2010-05-14 18:34:55 +02:00
let mayLoad = 1, mayStore = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
"xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
"xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
"xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
"xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
Add mayLoad and mayStore flags to instructions which missed them. llvm-svn: 103776
2010-05-14 18:34:55 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
"cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
"cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
"cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
"cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Add mayLoad and mayStore flags to instructions which missed them. llvm-svn: 103776
2010-05-14 18:34:55 +02:00
let mayLoad = 1, mayStore = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
"cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
"cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
"cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
"cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
Add mayLoad and mayStore flags to instructions which missed them. llvm-svn: 103776
2010-05-14 18:34:55 +02:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
Fix what looks to me obvious instruction definition bugs. 1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses. 2. LCMPXCHG8B is loading 64 bit memory, not 32 bit. llvm-svn: 92985
2010-01-08 02:29:19 +01:00
let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
"cmpxchg8b\t$dst", []>, TB;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
"cmpxchg16b\t$dst", []>, TB;
Handle some 64-bit atomics on x86-32, some of the time. llvm-svn: 56963
2008-10-02 20:53:47 +02:00
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-03 22:04:42 +01:00
// Lock instruction prefix
def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
// Repeat string operation instruction prefixes
// These uses the DF flag in the EFLAGS register to inc or dec ECX
let Defs = [ECX], Uses = [ECX,EFLAGS] in {
// Repeat (used with INS, OUTS, MOVS, LODS and STOS)
def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
// Repeat while not equal (used with CMPS and SCAS)
def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
}
Added the LODS (load byte into register, usually as part string parsing) instructions to the Intel instruction tables. llvm-svn: 82089
2009-09-17 00:59:28 +02:00
// String manipulation instructions
def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 08:22:35 +02:00
def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 01:01:26 +01:00
def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
// Flag instructions
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
// Table lookup instructions
def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
Addd (shl x, 1) ==> (shl x, x) peepholes. llvm-svn: 25123
2006-01-06 03:31:59 +01:00
Add support for using the FLAGS result of or, xor, and and instructions on x86, to avoid explicit test instructions. A few existing tests changed due to arbitrary register allocation differences. llvm-svn: 82263
2009-09-18 21:59:53 +02:00
One more round of reorg so sabre doesn't freak out. :-) llvm-svn: 26303
2006-02-21 21:00:20 +01:00
//===----------------------------------------------------------------------===//
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 07:32:15 +02:00
// Subsystems.
One more round of reorg so sabre doesn't freak out. :-) llvm-svn: 26303
2006-02-21 21:00:20 +01:00
//===----------------------------------------------------------------------===//
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 07:32:15 +02:00
// Floating Point Stack Support
One more round of reorg so sabre doesn't freak out. :-) llvm-svn: 26303
2006-02-21 21:00:20 +01:00
include "X86InstrFPStack.td"
rename X86InstrX86-64.td -> X86Instr64bit.td llvm-svn: 45826
2008-01-10 06:50:42 +01:00
include "X86Instr64bit.td"
One more round of reorg so sabre doesn't freak out. :-) llvm-svn: 26303
2006-02-21 21:00:20 +01:00
split conditional moves and setcc's out to their own file. llvm-svn: 115601
2010-10-05 08:33:16 +02:00
include "X86InstrCMovSetCC.td"
move sign and zero extensions out to their own file. llvm-svn: 115605
2010-10-05 08:52:26 +02:00
include "X86InstrExtension.td"
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 08:04:14 +02:00
include "X86InstrControl.td"
move 32-bit shift and rotates out to their own file. llvm-svn: 115607
2010-10-05 09:00:12 +02:00
include "X86InstrShiftRotate.td"
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 08:04:14 +02:00
TableGen fragment refactoring. Move some utility TableGen defs, classes, etc. into a common file so they may be used my multiple pattern files. We will use this for the AVX specification to help with the transition from the current SSE specification. llvm-svn: 95727
2010-02-10 00:52:19 +01:00
// SIMD support (SSE, MMX and AVX)
include "X86InstrFragmentsSIMD.td"
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual llvm-svn: 109204
2010-07-23 02:54:35 +02:00
// FMA - Fused Multiply-Add support (requires FMA)
include "X86InstrFMA.td"
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 07:32:15 +02:00
// SSE, MMX and 3DNow! vector support.
Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one. llvm-svn: 50278
2008-04-25 20:19:54 +02:00
include "X86InstrSSE.td"
include "X86InstrMMX.td"
stub out a header to put 3dNow! instructions into. llvm-svn: 115429
2010-10-03 01:06:23 +02:00
include "X86Instr3DNow.td"
move VMX instructions out to their own file. llvm-svn: 115597
2010-10-05 08:06:53 +02:00
include "X86InstrVMX.td"
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 07:32:15 +02:00
// System instructions.
include "X86InstrSystem.td"
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 08:04:14 +02:00
// Compiler Pseudo Instructions and Pat Patterns
include "X86InstrCompiler.td"
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