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428 Commits

Author SHA1 Message Date
Akira Hatanaka
c9268767d6 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Akira Hatanaka
ffa28d49f1 Check values of immediate operands. 
llvm-svn: 140860
 2011-09-30 17:19:21 +00:00
Akira Hatanaka
dcd69c2e07 Mips64 shift instructions. 
llvm-svn: 140841
 2011-09-30 03:18:46 +00:00
Akira Hatanaka
4bdb4b1958 Mips64 arithmetic and logical instructions with one source register and 
immediate.

llvm-svn: 140839
 2011-09-30 02:08:54 +00:00
Akira Hatanaka
50a4f6d570 Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140825
 2011-09-29 23:52:13 +00:00
Akira Hatanaka
70be05d5d0 Mips64 arithmetic and logical instructions with two source registers. 
llvm-svn: 140806
 2011-09-29 20:37:56 +00:00
Eli Friedman
56e68f7271 Convert more tests over to the new atomic instructions. 
llvm-svn: 140559
 2011-09-26 20:27:49 +00:00
Akira Hatanaka
0c87291a10 Remove +. 
llvm-svn: 140266
 2011-09-21 17:43:48 +00:00
Akira Hatanaka
d987b12b57 Re-enable some of the disabled tests. Use FileCheck instead of grep to check 
output.

llvm-svn: 140263
 2011-09-21 17:36:30 +00:00
Akira Hatanaka
3d26b79a9a Delete test cases that generate code for allegrex/psp and cannot be repurposed. 
llvm-svn: 139652
 2011-09-13 22:29:13 +00:00
Akira Hatanaka
44c745931f Add pattern used to match MipsLo, which is needed when the instruction selector 
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead

llvm-svn: 139634
 2011-09-13 20:13:58 +00:00
Akira Hatanaka
1376e1eabf Disable tests which generate code for allegrex or psp. 
llvm-svn: 139632
 2011-09-13 20:00:35 +00:00
Akira Hatanaka
a8f0f7babb Fix test cases. 
Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433
 2011-09-09 23:14:58 +00:00
Akira Hatanaka
f65d050693 Drop support for Mips1 and Mips2. 
llvm-svn: 139405
 2011-09-09 20:45:50 +00:00
Akira Hatanaka
17df2dfe8c Drop support for Allegrex. Allegrex implements a variant of Mips2. 
llvm-svn: 139383
 2011-09-09 19:00:51 +00:00
Akira Hatanaka
e1eb015eb9 Change default target architecture from Mips1 to Mips32r1 in preparation for 
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344
 2011-09-09 01:13:27 +00:00
Nick Lewycky
4e3daabb26 Disable these tests harder. They're XFAIL'd, but that means they still run, and 
these tests all infinitely recurse, bringing my system down into swapping hell.

llvm-svn: 139192
 2011-09-06 22:08:18 +00:00
Bill Wendling
267bc5089a Better fix for this testcase. Update it to the new EH scheme entirely. 
llvm-svn: 139039
 2011-09-02 21:27:08 +00:00
Bill Wendling
a4f9142ad4 Update for new EH stuff. (I'm not sure if this is 100% correct.) 
llvm-svn: 139038
 2011-09-02 21:24:17 +00:00
Dan Gohman
6d0230847c Revert r131152, r129796, r129761. This code is currently considered 
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977
 2011-09-01 23:07:08 +00:00
Akira Hatanaka
163382894e Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Akira Hatanaka
0179c7fa68 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Akira Hatanaka
dcbf455b98 Add test case for r137711. 
llvm-svn: 137725
 2011-08-16 17:32:01 +00:00
Akira Hatanaka
12df91513e Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
 2011-08-16 03:51:51 +00:00
Akira Hatanaka
c9c0190cbe Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Akira Hatanaka
6caf61a6ac Test case for 137484 
llvm-svn: 137486
 2011-08-12 18:12:06 +00:00
Akira Hatanaka
b787f8a8a5 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 

llvm-svn: 137378
 2011-08-11 22:42:31 +00:00
Akira Hatanaka
a50bbdfe15 Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Akira Hatanaka
14e517df43 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
 2011-07-19 20:34:00 +00:00
Akira Hatanaka
f59cbeec14 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
52263f51f1 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
llvm-svn: 135418
 2011-07-18 19:58:59 +00:00
Akira Hatanaka
79f38f0ae7 Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
 2011-07-18 18:52:12 +00:00
Akira Hatanaka
539ba34c25 Change the chain input of nodes that load the address of a function. This change 
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811
 2011-06-24 19:01:25 +00:00
Akira Hatanaka
3a3e7dfd84 Prevent generation of redundant addiu instructions that compute address of 
static variables or functions. 

llvm-svn: 133803
 2011-06-24 17:55:19 +00:00
Akira Hatanaka
1e08980a21 Re-apply 132758 and 132768 which were speculatively reverted in 132777. 
llvm-svn: 133494
 2011-06-21 00:40:49 +00:00
Chris Lattner
0899957b99 make the asmparser reject function and type redefinitions. 'Merging' hasn't been 
needed since llvm-gcc 3.4 days.

llvm-svn: 133248
 2011-06-17 07:06:44 +00:00
Chris Lattner
9ec82f54d4 manually upgrade a bunch of tests to modern syntax, and remove some that 
are either unreduced or only test old syntax.

llvm-svn: 133228
 2011-06-17 03:14:27 +00:00
Eric Christopher
24dafa3dbc Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
llvm-svn: 132777
 2011-06-09 16:03:19 +00:00
Akira Hatanaka
33ec063f3b Initial support for inline asm memory operand constraints. 
llvm-svn: 132768
 2011-06-09 03:31:05 +00:00
Akira Hatanaka
38115eb019 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the 
dynamically allocated stack area was not set.

llvm-svn: 132758
 2011-06-08 21:28:09 +00:00
Akira Hatanaka
fbeb14925f Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: 
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703
 2011-06-07 02:17:21 +00:00
Akira Hatanaka
1f91013bcb Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic. 
llvm-svn: 132448
 2011-06-02 01:03:14 +00:00
Akira Hatanaka
77501e89a7 Test case for r132444. 
llvm-svn: 132445
 2011-06-02 00:25:53 +00:00
Bruno Cardoso Lopes
728ea362c3 This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, 
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
 2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
f6fa29e7a1 This patch implements the thread local storage. Implemented are General 
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
 2011-05-31 02:53:58 +00:00
Jakob Stoklund Olesen
49bf4dd965 Fix PR10046 by updating LiveVariables kill info when splitting live ranges. 
This only affects targets like Mips where branch instructions may kill virtual
registers. Most other targets branch on flag values, so virtual registers are
not involved.

The problem is that MachineBasicBlock::updateTerminator deletes branches and
inserts new ones while LiveVariables keeps a list of pointers to instructions
that kill virtual registers. That list wasn't properly updated in
MBB::SplitCriticalEdge.

llvm-svn: 132298
 2011-05-29 20:10:28 +00:00
Akira Hatanaka
1590e4eab1 Define a wrapper node for target constant nodes (tglobaladdr, etc.). 
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
 2011-05-28 01:07:07 +00:00
Akira Hatanaka
5bfbea9ef2 Add support for C++ exception handling. 
llvm-svn: 132131
 2011-05-26 18:59:03 +00:00
Akira Hatanaka
3f49cbeb37 Define WeakRefDirective. 
llvm-svn: 132098
 2011-05-25 23:30:30 +00:00
Akira Hatanaka
32b5043265 Custom-lower FCOPYSIGN nodes. 
llvm-svn: 132074
 2011-05-25 19:32:07 +00:00
Akira Hatanaka
a5b11ee449 Fix lowering of DYNAMIC_STACKALLOC nodes. 
llvm-svn: 132030
 2011-05-25 02:20:00 +00:00
Akira Hatanaka
4ef318f1e1 Test case for r132003. 
llvm-svn: 132005
 2011-05-24 21:28:18 +00:00
Akira Hatanaka
21f003a8d4 Fix test case. 
llvm-svn: 131988
 2011-05-24 19:37:15 +00:00
Akira Hatanaka
98951fd8b5 Revision 131986 test case. 
llvm-svn: 131987
 2011-05-24 19:29:37 +00:00
Akira Hatanaka
5b696387f7 Add pattern for double-to-integer conversion. Patch by Sasa Stankovic. 
llvm-svn: 131927
 2011-05-23 22:16:43 +00:00
Akira Hatanaka
6ddbe02441 Change StackDirection from StackGrowsUp to StackGrowsDown. 
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
  the stack pointer) are set before instruction selection is completed. There is
  no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
  no longer necessary to assign negative offsets to fixed objects for incoming
  arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
  selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in 
  MipsFrameLowering::adjustMipsStackFrame.

llvm-svn: 131915
 2011-05-23 20:16:59 +00:00
Akira Hatanaka
89801a318c Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle 
saving and restoring them.

llvm-svn: 131745
 2011-05-20 18:39:33 +00:00
Akira Hatanaka
9736ffe863 Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic 
llvm-svn: 131714
 2011-05-20 02:30:51 +00:00
Akira Hatanaka
669a518bab Align i64 arguments to 64 bit boundaries. 
llvm-svn: 131668
 2011-05-19 20:29:48 +00:00
Akira Hatanaka
8ab44cecb4 Remove LLVM IR metadata in test case committed in r130847. 
llvm-svn: 130849
 2011-05-04 18:28:36 +00:00
Akira Hatanaka
e9a2d2a78f Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp. 
llvm-svn: 130847
 2011-05-04 17:54:27 +00:00
Jakob Stoklund Olesen
307c86d1ee Don't run this test through -regalloc=basic. 
The basic allocator is really bad about hinting, so it doesn't eliminate all
copies when physreg joining is disabled.

llvm-svn: 130817
 2011-05-04 01:01:44 +00:00
Akira Hatanaka
59b356bcc3 Lower BlockAddress node when relocation-model is static. 
llvm-svn: 130131
 2011-04-25 17:10:45 +00:00
Jakob Stoklund Olesen
c9861cc9f6 Make tests register allocation independent again. 
llvm-svn: 129739
 2011-04-19 00:14:43 +00:00
Akira Hatanaka
ee5ee33cfc Re-enable test o32_cc_vararg.ll. 
llvm-svn: 129616
 2011-04-15 22:23:09 +00:00
Akira Hatanaka
025720d06f Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. 
llvm-svn: 129594
 2011-04-15 19:52:08 +00:00
Andrew Trick
916e01c917 Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. 
Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.

Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.

llvm-svn: 129421
 2011-04-13 00:38:32 +00:00
Akira Hatanaka
24e15bbe94 Fix handling of functions with internal linkage. 
llvm-svn: 129099
 2011-04-07 19:51:44 +00:00
Jakob Stoklund Olesen
a0e0f8d74b These tests no longer require linear scan because reserved register coalescing is now universal. 
llvm-svn: 128936
 2011-04-05 21:40:41 +00:00
Akira Hatanaka
c2d74b05ca Add code for analyzing FP branches. Clean up branch Analysis functions. 
llvm-svn: 128718
 2011-04-01 17:39:08 +00:00
Jakob Stoklund Olesen
36c7c9d42d Fix Mips, Sparc, and XCore tests that were dependent on register allocation. 
Add an extra run with -regalloc=basic to keep them honest.

llvm-svn: 128654
 2011-03-31 18:42:43 +00:00
Akira Hatanaka
b26c89ee68 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
llvm-svn: 128650
 2011-03-31 18:26:17 +00:00
Daniel Dunbar
11a8b6c4ff Revert "Re-enable test and hope to silence the buildbots", still broken. 
llvm-svn: 127369
 2011-03-09 22:48:46 +00:00
Bruno Cardoso Lopes
f34376b0e1 Add a testcase for the addc improvements introduced some commits ago. Patch by Akira Hatanaka 
llvm-svn: 127358
 2011-03-09 21:05:32 +00:00
Bruno Cardoso Lopes
51df3638f8 Re-enable test and hope to silence the buildbots 
llvm-svn: 127357
 2011-03-09 21:00:16 +00:00
Bruno Cardoso Lopes
64f0169989 try to make o32 cc tests less specific to silence some buildbots. The test isn't enabled yet, this is will be done in a subsequent commit. Patch by Akira Hatanaka. 
llvm-svn: 127356
 2011-03-09 20:59:05 +00:00
Bruno Cardoso Lopes
88bef593d8 Improve varags handling, with testcases. Patch by Sasa Stankovic 
llvm-svn: 127349
 2011-03-09 19:22:22 +00:00
Bruno Cardoso Lopes
52c64a2eb3 Improve div/rem node handling on mips. Patch by Akira Hatanaka 
llvm-svn: 127034
 2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
1deaf83a77 Add testcase for r127032 
llvm-svn: 127033
 2011-03-04 20:48:39 +00:00
Joerg Sonnenberger
5f2f5fa638 Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".

llvm-svn: 127028
 2011-03-04 20:03:14 +00:00
Bruno Cardoso Lopes
99619e5bef Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
llvm-svn: 127027
 2011-03-04 20:01:52 +00:00
Joerg Sonnenberger
bb93506f95 Bug#9033: For the ELF assembler output, always quote the section name. 
llvm-svn: 126963
 2011-03-03 22:31:08 +00:00
Daniel Dunbar
5620b11961 Disable this test for now... 
llvm-svn: 125361
 2011-02-11 02:59:08 +00:00
Bruno Cardoso Lopes
3792d82914 Add mips o32 tests again with the hope that the buildbot won't complaint again 
llvm-svn: 125316
 2011-02-10 23:37:20 +00:00
Bruno Cardoso Lopes
c9968d544b Remove the test to silence the buildbot, will check it in again with a proper fix soon 
llvm-svn: 125305
 2011-02-10 20:10:17 +00:00
Bruno Cardoso Lopes
7cc40009a8 Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka with some small modifications by me. 
llvm-svn: 125292
 2011-02-10 18:05:10 +00:00
Bruno Cardoso Lopes
6c5db0236a Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka 
llvm-svn: 123760
 2011-01-18 19:29:17 +00:00
Rafael Espindola
9afb7af08a Update tests. 
llvm-svn: 123591
 2011-01-16 18:02:57 +00:00
Bruno Cardoso Lopes
93e5c2fb64 Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka 
llvm-svn: 121377
 2010-12-09 17:32:30 +00:00
Bruno Cardoso Lopes
0e14644599 Match a pattern generated by a dag combiner opt where: 
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.

llvm-svn: 121163
 2010-12-07 19:00:20 +00:00
Devang Patel
6fe7fe8dd4 If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0. 
llvm-svn: 121059
 2010-12-06 22:39:26 +00:00
Bruno Cardoso Lopes
37f2439cbd Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com> 
llvm-svn: 118864
 2010-11-12 00:38:32 +00:00
Bruno Cardoso Lopes
c911863e01 Add a test to the previous added clo instruction. Patch by Akira again 
llvm-svn: 118668
 2010-11-10 02:22:44 +00:00
Evan Cheng
1ce02d180e Enable machine sinking critical edge splitting. e.g. 
define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886

llvm-svn: 114372
 2010-09-20 22:52:00 +00:00
Duncan Sands
254f8ff0a6 Correct bogus module triple specifications. 
llvm-svn: 112469
 2010-08-30 10:48:29 +00:00
Bruno Cardoso Lopes
0fa595f073 Fix PR7174, a couple o Mips fixes: 
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.

Patch by stetorvs@gmail.com

llvm-svn: 108820
 2010-07-20 08:37:04 +00:00
Bruno Cardoso Lopes
b127fa9a01 Fix Mips PR7473. Patch by stetorvs@gmail.com 
llvm-svn: 108816
 2010-07-20 07:58:51 +00:00
Dan Gohman
5736cd1e47 Start function numbering at 0. 
llvm-svn: 101638
 2010-04-17 16:29:15 +00:00
Dale Johannesen
4cdb545401 Split big test into multiple directories to cater to 
those who don't build all targets.

llvm-svn: 100688
 2010-04-07 20:43:35 +00:00
Dan Gohman
5fa04f2707 Delete useless trailing semicolons. 
llvm-svn: 92740
 2010-01-05 17:55:26 +00:00
Bruno Cardoso Lopes
038281c523 Support PIC loading of constant pool entries 
llvm-svn: 89863
 2009-11-25 12:17:58 +00:00
Daniel Dunbar
cfcc2952fb Unbreak test, Bruno please check. 
llvm-svn: 89329
 2009-11-19 07:18:49 +00:00
Bruno Cardoso Lopes
bf95b9699e - Add sugregister logic to handle f64=(f32,f32). 
- Support mips1 like load/store of doubles:

Instead of:
  sdc $f0, X($3)
Generate:
  swc $f0, X($3)
  swc $f1, X+4($3)

llvm-svn: 89322
 2009-11-19 06:06:13 +00:00
Evan Cheng
5c06a152a8 xfail for now. It has been failing. 
llvm-svn: 88892
 2009-11-16 05:44:04 +00:00
Bruno Cardoso Lopes
21ca44ba49 - Fix a small bug while handling target constant pools (one param was missing). 
- Add a smarter constant pool loading, instead of:

lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)

Generate:

lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)

llvm-svn: 88886
 2009-11-16 04:33:42 +00:00
Dan Gohman
142428ce64 Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Dan Gohman
bf08e82d8e Remove obsolete -f flags. 
llvm-svn: 79992
 2009-08-25 15:38:29 +00:00
Chris Lattner
4cebf6ca28 reintroduce support for Mips "small" section handling. This is 
implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.

llvm-svn: 78900
 2009-08-13 06:28:06 +00:00
Daniel Dunbar
775da1948b Pass target triple string in to TargetMachine constructor. 
This is not just a matter of passing in the target triple from the module;
currently backends are making decisions based on the build and host
architecture. The goal is to migrate to making these decisions based off of the
triple (in conjunction with the feature string). Thus most clients pass in the
target triple, or the host triple if that is empty.

This has one important change in the way behavior of the JIT and llc.

For the JIT, it was previously selecting the Target based on the host
(naturally), but it was setting the target machine features based on the triple
from the module. Now it is setting the target machine features based on the
triple of the host.

For LLC, -march was previously only used to select the target, the target
machine features were initialized from the module's triple (which may have been
empty). Now the target triple is taken from the module, or the host's triple is
used if that is empty. Then the triple is adjusted to match -march.

The take away is that -march for llc is now used in conjunction with the host
triple to initialize the subtarget. If users want more deterministic behavior
from llc, they should use -mtriple, or set the triple in the input module.

llvm-svn: 77946
 2009-08-03 04:03:51 +00:00
Chris Lattner
09511ed243 Remove SectionKind::Small*. This was only used on mips, and is apparently 
a sad mistake that is regretted. :)

llvm-svn: 76935
 2009-07-24 03:11:51 +00:00
Duncan Sands
2a4535353f Revert commit 76707, it was breaking the llvm-gcc build 
on linux platforms.  The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html 

llvm-svn: 76733
 2009-07-22 10:35:05 +00:00
Chris Lattner
ced616dd50 set the ELF "small" flag on objects that end up in .rodata.cst4 consistently, 
updating a mips testcase to expect it.

llvm-svn: 76707
 2009-07-22 00:41:56 +00:00
Dan Gohman
5f6f8101d5 Split the Add, Sub, and Mul instruction opcodes into separate 
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
 2009-06-04 22:49:04 +00:00
Bill Wendling
2944bcd25c This looks like it passes now. 
llvm-svn: 72485
 2009-05-27 17:43:21 +00:00
Rafael Espindola
0aba6c9435 Add the private linkage. 
llvm-svn: 62279
 2009-01-15 20:18:42 +00:00
Dan Gohman
9e9858781c The list-td and list-tdrr schedulers don't yet support physreg 
scheduling dependencies. Add assertion checks to help catch
this.

It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.

llvm-svn: 62177
 2009-01-13 20:24:13 +00:00
Duncan Sands
22e8a45a01 Fix PR2667: add soft float support for sint_to_fp/uint_to_fp 
where the argument is an apint, or smaller than the minimum
size for which there is a libcall (i32). 

llvm-svn: 58994
 2008-11-10 17:36:26 +00:00
Duncan Sands
a6bbc047d5 Turn on LegalizeTypes, the new type legalization 
codegen infrastructure, by default.  Please report
any breakage to the mailing lists.

llvm-svn: 58232
 2008-10-27 08:42:46 +00:00
Evan Cheng
de99d94c58 FIX PR2794. Make sure SIGN_EXTEND_INREG nodes introduced by LegalizeSetCCOperands are leglized. Patch by Richard Pennington. 
llvm-svn: 57460
 2008-10-13 18:46:18 +00:00
Bruno Cardoso Lopes
5463c59693 Added testcase for bswap allegrexel intrinsic 
llvm-svn: 56225
 2008-09-15 19:38:11 +00:00
Bruno Cardoso Lopes
f8906a40ab Support added for ctlz intrinsic, test case added. 
llvm-svn: 54516
 2008-08-08 06:16:31 +00:00
Bruno Cardoso Lopes
91abeb9458 [Last] Batch 7 of Mips CodeGen tests 
llvm-svn: 54512
 2008-08-08 04:12:42 +00:00
Bruno Cardoso Lopes
c4f524b9d1 Batch 6 of Mips CodeGen tests 
llvm-svn: 54511
 2008-08-08 04:11:30 +00:00
Bruno Cardoso Lopes
772cf1643c Batch 5 of Mips CodeGen tests 
llvm-svn: 54510
 2008-08-08 04:09:57 +00:00
Bruno Cardoso Lopes
7d4b844ee8 Batch 4 of Mips CodeGen tests 
llvm-svn: 54509
 2008-08-08 04:08:30 +00:00
Bruno Cardoso Lopes
06380b7221 Batch 3 of Mips CodeGen tests 
llvm-svn: 54508
 2008-08-08 04:05:51 +00:00
Bruno Cardoso Lopes
96efb82258 Batch 2 of Mips CodeGen tests 
llvm-svn: 54507
 2008-08-08 04:03:25 +00:00
Bruno Cardoso Lopes
42b4e15d50 Batch 1 of Mips CodeGen tests, more coming... 
I had a lot of simple local codegen tests and they are now ready to be placed
in test/CodeGen. 

llvm-svn: 54506
 2008-08-08 03:58:34 +00:00