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Author SHA1 Message Date
Jim Grosbach
37853d6216 ARM assembler should prefer non-aliases encoding of cmp. 
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.

llvm-svn: 153770
 2012-03-30 19:59:02 +00:00
Jim Grosbach
92ee2a8454 ARM encoding for VSWP got the second operand incorrect. 
Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

llvm-svn: 153766
 2012-03-30 18:53:01 +00:00
Jim Grosbach
2536615bab ARM integrated assembler should encoding choice for add/sub imm. 
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.

rdar://11156277

llvm-svn: 153759
 2012-03-30 17:20:40 +00:00
Jim Grosbach
9b185a753c ARM assembly parsing needs to be paranoid about negative immediates. 
Make sure to treat immediates as unsigned when doing relative comparisons.

rdar://11153621

llvm-svn: 153753
 2012-03-30 16:31:31 +00:00
James Molloy
70a6f5ebc7 Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch. 
Patch by Tim Northover!

llvm-svn: 153737
 2012-03-30 09:15:32 +00:00
Jim Grosbach
ab639b8c36 ARM assembly 'cmp lr, #0' should not encode using 'cmn'. 
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.

rdar://11129224

llvm-svn: 153689
 2012-03-29 21:19:52 +00:00
Richard Barton
201661d4bc Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version. 
llvm-svn: 153573
 2012-03-28 10:18:11 +00:00
Eli Bendersky
3ef88c1833 Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 
* Removed test/lib/llvm.exp - it is no longer needed 
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
  left in the test suite so this code is no longer required. test/lit.cfg is
  now much shorter and clearer 
* Removed a lot of duplicate code in lit.local.cfg files that need access to
  the root configuration, by adding a "root" attribute to the TestingConfig
  object. This attribute is dynamically computed to provide the same
  information as was previously provided by the custom getRoot functions. 
* Documented the config.root attribute in docs/CommandGuide/lit.pod

llvm-svn: 153408
 2012-03-25 09:02:19 +00:00
Kevin Enderby
b87e1e0bfd Fix assembling ARM vst2 instructions with double-spaced registers. 
llvm-svn: 153099
 2012-03-20 17:41:51 +00:00
Jim Grosbach
af19922301 ARM ldm/stm register lists can be out of order. 
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.

rdar://11064740

llvm-svn: 152943
 2012-03-16 20:48:38 +00:00
Jim Grosbach
a5d57ea09e ARM optional operand on MRC/MCR assembly instructions. 
rdar://11058464

llvm-svn: 152883
 2012-03-16 00:45:58 +00:00
Jim Grosbach
77151885af ARM vmrs system registers mvfr0 and mvfr1 handling. 
rdar://11058464

llvm-svn: 152881
 2012-03-16 00:27:18 +00:00
Jim Grosbach
3812c82b92 ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

llvm-svn: 152846
 2012-03-15 21:34:14 +00:00
Kristof Beyls
5f7d669c67 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. 
llvm-svn: 152814
 2012-03-15 17:50:29 +00:00
Jim Grosbach
91314c2db6 ARM vpush/vpop assembler mnemonics accept an optional size suffix. 
rdar://10988114

llvm-svn: 152068
 2012-03-05 23:16:31 +00:00
Jim Grosbach
02bf78f5ca ARM BL/BLX instruction fixups should use relocations. 
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.

To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.

rdar://10927209

llvm-svn: 151571
 2012-02-27 21:36:23 +00:00
Eli Bendersky
4afdeeb682 Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed. 
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.

llvm-svn: 150664
 2012-02-16 06:28:33 +00:00
James Molloy
b586b7c9c7 Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends. 
Fixes PR11877

llvm-svn: 149180
 2012-01-28 15:58:32 +00:00
James Molloy
402abeda73 Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. 
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
 2012-01-26 09:25:43 +00:00
Jim Grosbach
20a6580dff ARM assemly parsing and validation of IT instruction. 
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
 2012-01-25 19:52:01 +00:00
Jim Grosbach
e8095f3b49 NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach
f478b2a706 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Jim Grosbach
e151b15949 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Jim Grosbach
a78348fcda NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach
f3607eac5d NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach
47f7ce80b8 Remove redundant test file. 
llvm-svn: 148820
 2012-01-24 17:55:32 +00:00
Jim Grosbach
630dd380c7 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach
42c0f99aa0 NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach
703b0bb646 Tidy up. 
llvm-svn: 148817
 2012-01-24 17:46:54 +00:00
Jim Grosbach
3be662b372 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach
ca32a49eb5 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach
a4687dcf5a NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Jim Grosbach
048162ddf9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00
Jim Grosbach
8035fac461 NEON VLD3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148745
 2012-01-23 23:20:46 +00:00
Jim Grosbach
dd667a11d3 NEON VLD3 lane-indexed assembly parsing and encoding. 
llvm-svn: 148734
 2012-01-23 21:53:26 +00:00
Jim Grosbach
0eeacbfe2e Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Jim Grosbach
4579f05f36 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00
Jim Grosbach
b7ab9edb4e Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
 2012-01-18 22:46:46 +00:00
Jim Grosbach
a678ad9ecc ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

llvm-svn: 147189
 2011-12-22 22:19:05 +00:00
Rafael Espindola
eba1c0eb00 Fix incorrect relocation generation. Patch by Kristof Beyls. 
Fixes PR11214.

llvm-svn: 147180
 2011-12-22 21:36:43 +00:00
Jim Grosbach
100e3aaffa ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

llvm-svn: 147153
 2011-12-22 18:04:04 +00:00
Jim Grosbach
7d31680e2d ARM VFP optional data type on VMOV GPR<-->SPR. 
llvm-svn: 147104
 2011-12-21 23:24:15 +00:00
Jim Grosbach
2bbc41fa26 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096
 2011-12-21 21:04:19 +00:00
Jim Grosbach
91faf5d15f Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094
 2011-12-21 20:54:00 +00:00
Jim Grosbach
f7236d1084 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
llvm-svn: 147069
 2011-12-21 19:40:55 +00:00
Jim Grosbach
6bd1044b03 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Jim Grosbach
0768f2c420 Enable and fix a test. 
llvm-svn: 147011
 2011-12-20 23:20:00 +00:00
Jim Grosbach
8978194025 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Jim Grosbach
3f48367a1b ARM enable a few more tests. 
llvm-svn: 146985
 2011-12-20 20:03:00 +00:00
Jim Grosbach
8156a5dcee ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Jim Grosbach
3f5493c136 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

llvm-svn: 146937
 2011-12-20 00:59:38 +00:00
Jim Grosbach
343f270350 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

llvm-svn: 146921
 2011-12-19 23:06:24 +00:00
Jim Grosbach
797a88284c ARM NEON two-operand aliases for VPADD. 
rdar://10602276

llvm-svn: 146895
 2011-12-19 19:51:03 +00:00
Jim Grosbach
520db82971 ARM NEON implied destination aliases for VMAX/VMIN. 
llvm-svn: 146885
 2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
 2011-12-19 18:31:43 +00:00
Jim Grosbach
30f4b285a6 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Jim Grosbach
b79d2a8f50 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Jim Grosbach
75db252aee ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
llvm-svn: 146605
 2011-12-14 23:25:46 +00:00
Jim Grosbach
83520a5b70 ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594
 2011-12-14 21:49:24 +00:00
Jim Grosbach
44829ab9d2 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
 2011-12-14 19:35:22 +00:00
Jim Grosbach
54372eef76 ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

llvm-svn: 146567
 2011-12-14 17:30:24 +00:00
Jim Grosbach
628ae663ef ARM assembler support for the target-specific .req directive. 
rdar://10549683

llvm-svn: 146543
 2011-12-14 02:16:11 +00:00
Jim Grosbach
089ad574d8 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767

llvm-svn: 146520
 2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd ARM LDM/STM system instruction variants. 
rdar://10550269

llvm-svn: 146519
 2011-12-13 21:48:29 +00:00
Jim Grosbach
7db50010cc Test for 146516 
llvm-svn: 146517
 2011-12-13 21:06:59 +00:00
Jim Grosbach
13d3509445 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741

llvm-svn: 146515
 2011-12-13 20:50:38 +00:00
Jim Grosbach
dfec87fe2f ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00
Jim Grosbach
0ba5ba4535 ARM pre-UAL NEG mnemonic for convenience when porting old code. 
llvm-svn: 146511
 2011-12-13 20:23:22 +00:00
Jim Grosbach
356ad6d232 ARM assembly aliases for BIC<-->AND (immediate). 
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283
 2011-12-09 22:02:17 +00:00
Jim Grosbach
489e81da30 ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
 2011-12-09 21:28:25 +00:00
Jim Grosbach
62873cae5f ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
llvm-svn: 146194
 2011-12-08 22:19:04 +00:00
Jim Grosbach
a33fa8aa88 ARM VSHR implied destination operand form aliases. 
llvm-svn: 146192
 2011-12-08 22:06:06 +00:00
Jim Grosbach
af9cc198cf Tidy up a bit. 
llvm-svn: 146190
 2011-12-08 22:04:40 +00:00
Jim Grosbach
78020c4642 ARM VSUB implied destination operand form aliases. 
llvm-svn: 146182
 2011-12-08 20:56:26 +00:00
Jim Grosbach
957be45ccf Tidy up a bit. 
llvm-svn: 146181
 2011-12-08 20:53:19 +00:00
Jim Grosbach
a33af36947 ARM VQADD implied destination operand form aliases. 
llvm-svn: 146179
 2011-12-08 20:49:43 +00:00
Jim Grosbach
405e213008 ARM a few more VMUL implied destination operand form aliases. 
llvm-svn: 146177
 2011-12-08 20:42:35 +00:00
Jim Grosbach
e1fe053f6e ARM NEON two-operand aliases for VSHL(immediate). 
llvm-svn: 146125
 2011-12-08 01:30:04 +00:00
Jim Grosbach
3e9384b103 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Jim Grosbach
3b4d5c0510 ARM optional destination operand variants for VEXT instructions. 
llvm-svn: 146114
 2011-12-08 00:43:47 +00:00
Jim Grosbach
0c64182f7c Tidy up. 
llvm-svn: 146113
 2011-12-08 00:41:54 +00:00
Jim Grosbach
c1cf417595 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
llvm-svn: 146111
 2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

llvm-svn: 146106
 2011-12-07 23:40:58 +00:00
Jim Grosbach
dd3788b044 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
llvm-svn: 146095
 2011-12-07 23:08:12 +00:00
Jim Grosbach
da0a3e310a ARM two-operand aliases for VADDW instructions. 
llvm-svn: 146093
 2011-12-07 23:01:10 +00:00
Jim Grosbach
ecf9c2bb21 ARM two-operand aliases for VADD instructions. 
llvm-svn: 146091
 2011-12-07 22:52:54 +00:00
Jim Grosbach
1ccae84fa7 Thumb2 alias for long-form pop and friends. 
rdar://10542474

llvm-svn: 146046
 2011-12-07 18:32:28 +00:00
Jim Grosbach
81cb9952c9 ARM support the .arm and .thumb directives for assembly mode switching. 
llvm-svn: 146042
 2011-12-07 18:04:19 +00:00
Jim Grosbach
3352ab97ca ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
llvm-svn: 146039
 2011-12-07 17:51:15 +00:00
Jim Grosbach
61d2b8b2f9 Tidy up. Move MachO tests to MachO directory. 
llvm-svn: 146038
 2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
ed2be25205 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. 
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
 2011-12-06 06:48:26 +00:00
Jim Grosbach
5b4f7d74de ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

llvm-svn: 145923
 2011-12-06 05:28:00 +00:00
Jim Grosbach
dc7d42f559 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
 2011-12-06 05:03:45 +00:00
Jim Grosbach
8bdbe92631 Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
 2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
ea8cc0e506 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. 
MC/MachO assumes x86.

llvm-svn: 145916
 2011-12-06 03:56:05 +00:00
Jim Grosbach
74bbb6454e Tweak ADDrr fix. Bad check for explicit .w 
llvm-svn: 145863
 2011-12-05 22:27:04 +00:00
Jim Grosbach
6584358d09 Update tests for r145860. Add a few new ones. 
llvm-svn: 145861
 2011-12-05 22:21:28 +00:00
Jim Grosbach
655b017748 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348

llvm-svn: 145851
 2011-12-05 21:06:26 +00:00
Jim Grosbach
9c017fb254 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.

llvm-svn: 145846
 2011-12-05 20:29:59 +00:00
Jim Grosbach
6ae4df64e7 ARM tests for VLD1 single lane w/ writeback. 
llvm-svn: 145713
 2011-12-02 22:03:52 +00:00
Jim Grosbach
a568ef0db6 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Jim Grosbach
3129a92b38 Add some tests for all-lanes VLD1 parsing. 
llvm-svn: 145512
 2011-11-30 19:37:38 +00:00
Jim Grosbach
538759efa7 ARM assembly parsing and encoding for four-register VST1. 
llvm-svn: 145450
 2011-11-29 22:58:48 +00:00
Jim Grosbach
fc7e76b194 Enable some VST1 tests and add a few more. 
llvm-svn: 145443
 2011-11-29 22:40:32 +00:00
Chris Lattner
9d1e8420ff Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. 
llvm-svn: 145171
 2011-11-27 06:54:59 +00:00
Jim Grosbach
1b837af2bd Remove obsolete test. 
The PLD encoding is checked via the .s file now.

llvm-svn: 144853
 2011-11-16 22:50:38 +00:00
Jim Grosbach
fe5f0cfa29 Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

llvm-svn: 144852
 2011-11-16 22:48:37 +00:00
Jim Grosbach
8fae277866 Update test for r144842. 
llvm-svn: 144851
 2011-11-16 22:46:27 +00:00
Jim Grosbach
044acb8bee ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727
 2011-11-15 23:19:15 +00:00
Jim Grosbach
b8ebc386df ARM assembly parsing two operand forms for shift instructions. 
llvm-svn: 144713
 2011-11-15 22:27:54 +00:00
Jim Grosbach
4d0ad5a4e0 ARM alternate size suffices for VTRN instructions. 
rdar://10435076

llvm-svn: 144694
 2011-11-15 20:49:46 +00:00
Jim Grosbach
8987b277cb ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

llvm-svn: 144691
 2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

llvm-svn: 144689
 2011-11-15 20:14:51 +00:00
Jim Grosbach
8b1d4c989c ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

llvm-svn: 144688
 2011-11-15 20:02:06 +00:00
Jim Grosbach
e4933acaa7 Testcase for r144684. 
llvm-svn: 144685
 2011-11-15 19:56:17 +00:00
Jim Grosbach
df951fa128 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679
 2011-11-15 19:29:45 +00:00
Jim Grosbach
6846540505 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

llvm-svn: 144593
 2011-11-14 23:43:46 +00:00
Jim Grosbach
a1a28df278 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

llvm-svn: 144592
 2011-11-14 23:32:59 +00:00
Jim Grosbach
00283a5c8e ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

llvm-svn: 144587
 2011-11-14 23:11:19 +00:00
Jim Grosbach
4a2f107b04 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Jim Grosbach
13b7ab7527 ARM optional size suffix for VLDR/VSTR syntax. 
llvm-svn: 144427
 2011-11-11 23:34:43 +00:00
Jim Grosbach
1d581ecb00 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

llvm-svn: 144407
 2011-11-11 21:27:40 +00:00
Jim Grosbach
bd7df609b7 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

llvm-svn: 144331
 2011-11-10 23:17:11 +00:00
Jim Grosbach
c3651cb620 Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

llvm-svn: 144322
 2011-11-10 22:10:12 +00:00
Jim Grosbach
f5943e4c5e ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

llvm-svn: 144301
 2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

llvm-svn: 144293
 2011-11-10 16:44:55 +00:00
Jim Grosbach
8591bd2bab Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955

llvm-svn: 144242
 2011-11-09 23:44:23 +00:00
Benjamin Kramer
89ebc7ab4b Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
 2011-11-07 21:00:59 +00:00
Jim Grosbach
f3285dba99 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
 2011-10-28 22:36:30 +00:00
Jim Grosbach
72ab459378 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
 2011-10-28 16:57:07 +00:00
Jim Grosbach
dac7815a91 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

llvm-svn: 143167
 2011-10-28 00:06:50 +00:00
Jim Grosbach
4f7964293a Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

llvm-svn: 143110
 2011-10-27 17:33:59 +00:00
Jim Grosbach
e1ec953149 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584

llvm-svn: 143108
 2011-10-27 17:16:55 +00:00
Jim Grosbach
e3c6fa663f Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

llvm-svn: 143068
 2011-10-26 22:22:01 +00:00
Jim Grosbach
fabe0f2f0b ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.

llvm-svn: 142882
 2011-10-25 00:14:01 +00:00
Jim Grosbach
688186941f ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.

llvm-svn: 142876
 2011-10-24 23:26:05 +00:00
Jim Grosbach
cf4fba1dd0 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

llvm-svn: 142861
 2011-10-24 22:16:58 +00:00
Jim Grosbach
0bb9a86fc7 Update test for r142801. 
llvm-svn: 142806
 2011-10-24 17:26:26 +00:00
Jim Grosbach
d964cf8939 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Owen Anderson
2021ad2133 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
llvm-svn: 142626
 2011-10-20 22:23:58 +00:00
Owen Anderson
ffca195c01 Fix tests for corrected MSR encodings. 
llvm-svn: 142622
 2011-10-20 21:53:19 +00:00
Jim Grosbach
e9d1df8266 ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach
954465d59a Tidy up formatting. 
llvm-svn: 142582
 2011-10-20 14:57:47 +00:00
Jim Grosbach
972f26d936 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Jim Grosbach
6110df7008 Tidy up formatting. 
llvm-svn: 142422
 2011-10-18 21:09:01 +00:00
Jim Grosbach
de82cec744 Tidy up formatting. 
llvm-svn: 142421
 2011-10-18 21:08:16 +00:00
Jim Grosbach
f0d2d6bfc1 Enable more encoded immediate tests. 
llvm-svn: 142415
 2011-10-18 20:20:51 +00:00
Jim Grosbach
8c1298946c More vmov lane testcases. 
llvm-svn: 142414
 2011-10-18 20:19:48 +00:00
Jim Grosbach
ff8c26a53f ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2 ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Jim Grosbach
988b8dd4ce ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Owen Anderson
39a3d3305a Another failing encoding. 
llvm-svn: 142388
 2011-10-18 18:23:03 +00:00
Jim Grosbach
de8f8bec78 Fix NEON mul encoding tests. Wrong file contents previously. 
llvm-svn: 142387
 2011-10-18 18:14:55 +00:00
Jim Grosbach
2752e0b869 ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach
d2162f8c95 Remove duplicate test. 
llvm-svn: 142383
 2011-10-18 18:05:50 +00:00
Jim Grosbach
86d53ed3d4 Tidy up formatting. 
llvm-svn: 142382
 2011-10-18 18:05:16 +00:00
Jim Grosbach
b56577b650 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Jim Grosbach
93213f0ca9 Tidy up. 
llvm-svn: 142380
 2011-10-18 18:01:09 +00:00
Owen Anderson
593bfe68d2 Add a few more testcases. 
llvm-svn: 142379
 2011-10-18 17:57:31 +00:00
Owen Anderson
77f405511d Add several FIXME cases for ARM encodings. 
llvm-svn: 142377
 2011-10-18 17:50:22 +00:00
Jim Grosbach
8c454cac49 Tests for 142365. 
llvm-svn: 142368
 2011-10-18 17:23:34 +00:00
Jim Grosbach
df6fb84ea5 Tidy up formatting. 
llvm-svn: 142367
 2011-10-18 17:22:53 +00:00
Jim Grosbach
031bb99231 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Jim Grosbach
9266437a1f Enable a few more NEON immediate tests. 
llvm-svn: 142313
 2011-10-17 23:50:19 +00:00
Jim Grosbach
1e994e76a7 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
llvm-svn: 142303
 2011-10-17 23:09:09 +00:00
Jim Grosbach
f3d495fbbd ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Owen Anderson
96976108b1 Update test for disabling of code/data marker labels in ELF. 
llvm-svn: 142003
 2011-10-14 21:12:55 +00:00
Jim Grosbach
422576b6e8 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Jim Grosbach
2a501996ab ARM encoding tests for STC. 
llvm-svn: 141787
 2011-10-12 17:36:13 +00:00
Jim Grosbach
eb7acc978a ARM parsing and encoding for the <option> form of LDC/STC instructions. 
llvm-svn: 141786
 2011-10-12 17:34:41 +00:00
Jim Grosbach
d2cfc2b31f ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721
 2011-10-11 21:55:36 +00:00
Jim Grosbach
6322a90e2d Enable ARM mode VDUP(scalar) tests. 
llvm-svn: 141447
 2011-10-07 23:57:03 +00:00
Jim Grosbach
94980a23e6 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
Jim Grosbach
53b2b56db8 Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead. 
llvm-svn: 141321
 2011-10-06 22:04:05 +00:00
Jim Grosbach
ec12700fe4 Fix and clean up tests. Un-XFAIL. 
llvm-svn: 141318
 2011-10-06 21:32:50 +00:00
Jim Grosbach
17ae6aae38 Fix and clean up tests. Un-XFAIL. 
llvm-svn: 141316
 2011-10-06 21:28:30 +00:00
Owen Anderson
2d1e930b65 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
llvm-svn: 141190
 2011-10-05 17:16:40 +00:00
Owen Anderson
e255773f3d Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
llvm-svn: 141135
 2011-10-04 23:26:17 +00:00
Jim Grosbach
386f7cb041 Tidy up formatting. 
llvm-svn: 141123
 2011-10-04 21:43:51 +00:00
Jim Grosbach
f3373734b4 Un-XFAIL file. Comment out individual failing instructions. 
llvm-svn: 141117
 2011-10-04 21:16:42 +00:00
Jim Grosbach
6f00406f92 Tidy up formatting. 
llvm-svn: 141115
 2011-10-04 20:52:57 +00:00
Jim Grosbach
0db58d15e6 Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup. 
llvm-svn: 141114
 2011-10-04 20:50:05 +00:00
Jim Grosbach
3df5c47ec8 Un-XFAIL file. Fix incorrect CHECK line. General format cleanup. 
llvm-svn: 141113
 2011-10-04 20:46:49 +00:00
Jim Grosbach
4770714494 Tidy up formatting. 
llvm-svn: 141111
 2011-10-04 20:42:35 +00:00
Jim Grosbach
dee6bd4517 Un-XFAIL file. Fix incorrect CHECK line. 
llvm-svn: 141110
 2011-10-04 20:42:09 +00:00
Jim Grosbach
d7449dd23f Un-XFAIL the file. Disable only the individual tests that aren't working yet. 
llvm-svn: 141108
 2011-10-04 20:34:11 +00:00
Jim Grosbach
58f067b61b Un-XFAIL the file. Disable only the individual tests that aren't working yet. 
llvm-svn: 141099
 2011-10-04 18:43:15 +00:00
Jim Grosbach
93ad98accb Tidy up. Formatting. 
llvm-svn: 141096
 2011-10-04 17:49:45 +00:00
Jim Grosbach
8170db143e Tidy up. These tests are covered in the .s file tests now. 
llvm-svn: 141047
 2011-10-03 23:40:13 +00:00
Jim Grosbach
f38874e79e ARM assembly parsing and encoding for VMOV immediate. 
llvm-svn: 141046
 2011-10-03 23:38:36 +00:00
Jim Grosbach
c69258c747 ARM parsing/encoding for VCMP/VCMPE. 
llvm-svn: 141038
 2011-10-03 22:30:24 +00:00
Jim Grosbach
21a9f8f50f ARM assembly parsing and encoding for VMRS/FMSTAT. 
llvm-svn: 141025
 2011-10-03 21:12:43 +00:00
Jim Grosbach
0e385170ee Update test for 141010. 
llvm-svn: 141022
 2011-10-03 20:58:08 +00:00
Jim Grosbach
1651804363 Tidy up a bit. Formatting. 
llvm-svn: 141010
 2011-10-03 17:59:31 +00:00
James Molloy
c4fcff419c Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
 2011-09-28 14:21:38 +00:00