Chris Lattner
fc626aa37d
reimplement ppc asmprinter "toc" handling to use a VariantKind
...
on the operand, required for .o file writing and fixing
the PowerPC/mult-alt-generic-powerpc64.ll failure with the new
instprinter.
llvm-svn: 119087
2010-11-14 22:22:59 +00:00
Chris Lattner
3c8d9ea286
lower PPC::MFCRpseud when transforming to MC, avoiding calling
...
the aborting printSpecial() method. This gets us to 8 failures.
llvm-svn: 119084
2010-11-14 22:03:15 +00:00
Chris Lattner
36fad020cd
make the stubbed-out printer methods abort instead of
...
printing nothing. This gets us back up to 24 failures.
llvm-svn: 119083
2010-11-14 21:54:34 +00:00
Chris Lattner
331d966779
wire up a few more things, down to 4 test failures, all
...
about handling $stub, lo/hi etc.
llvm-svn: 119082
2010-11-14 21:51:37 +00:00
Chris Lattner
3959bd7fb4
properly wire up the instprinter to the ppc64 backend, down to 5 failures.
...
llvm-svn: 119081
2010-11-14 21:42:53 +00:00
Chris Lattner
27b65608d0
implement pretty printing support for the various pseudo
...
ops the asmprinter supported, fixing PowerPC/rlwimi2.ll
among others. Down to 20 failures.
llvm-svn: 119080
2010-11-14 21:39:51 +00:00
Chris Lattner
437623476f
Wire up symbol hi/lo printing. We don't print hi()/lo(), but this gets
...
us further along. Only 28 failures now.
llvm-svn: 119079
2010-11-14 21:33:07 +00:00
Chris Lattner
b12ecaae5a
implement basic support for symbol operand lowering,
...
and printing support for call operands. Down to 77 failures.
llvm-svn: 119078
2010-11-14 21:20:46 +00:00
Chris Lattner
3bf85b2f4b
trim #includes.
...
llvm-svn: 119075
2010-11-14 21:16:04 +00:00
Chris Lattner
32848508af
switch PPC to a simplified MCInstLowering model.
...
llvm-svn: 119074
2010-11-14 21:12:33 +00:00
Chris Lattner
163fbca360
fix PPC.h to not pull in TargetMachine.h
...
llvm-svn: 119072
2010-11-14 21:09:28 +00:00
Chris Lattner
3a01d37b66
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
...
llvm-svn: 119071
2010-11-14 21:00:02 +00:00
Chris Lattner
4dac1b2742
even more simplifications. ARM MCInstLowering is now just
...
a single function instead of a class. It doesn't need the
complexity that X86 does.
llvm-svn: 119070
2010-11-14 20:58:38 +00:00
Chris Lattner
3ebf1f315e
more shrinkification
...
llvm-svn: 119068
2010-11-14 20:41:53 +00:00
Chris Lattner
758bc06aff
more simplifications.
...
llvm-svn: 119067
2010-11-14 20:40:08 +00:00
Chris Lattner
2393da7c40
simplify and tidy up
...
llvm-svn: 119066
2010-11-14 20:31:06 +00:00
Chris Lattner
a6262cb13f
implement basic support for memory operands and crbit operands,
...
this fixes 3 more ppc tests.
llvm-svn: 119065
2010-11-14 20:22:56 +00:00
Chris Lattner
3249cd7521
implement several trivial operand printers, reducing
...
failures in CodeGen/PowerPC from 120 -> 117
llvm-svn: 119063
2010-11-14 20:11:21 +00:00
Chris Lattner
8d769a7610
Implement support for printing register and immediate operands,
...
add support for darwin vs aix syntax. We now can print instructions
like this:
add r3, r3, r4
blr
and (in aix mode):
add 3, 3, 4
blr
llvm-svn: 119062
2010-11-14 20:02:39 +00:00
Chris Lattner
e137166772
stub out PPCMCInstLowering, add a new option that uses it and the new
...
instprinter when -enable-ppc-inst-printer is passed to llc.
llvm-svn: 119061
2010-11-14 19:53:02 +00:00
Chris Lattner
d045c38bf6
stub out a powerpc MCInstPrinter implementation.
...
llvm-svn: 119059
2010-11-14 19:40:38 +00:00
Chris Lattner
cec3b226a4
move all the target's asmprinters into the main target. The piece
...
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.
llvm-svn: 119056
2010-11-14 18:43:56 +00:00
Chris Lattner
38ca2c6f0f
move PPCAsmPrinter into the main PPC library, like ARM and X86.
...
llvm-svn: 119054
2010-11-14 18:33:33 +00:00
Chris Lattner
7e03d38bd7
fix cmake
...
llvm-svn: 119053
2010-11-14 18:27:11 +00:00
Chris Lattner
4533444a49
remove JIT support from the Alpha backend. The JIT will be moving to MC,
...
and the Alpha backend isn't MCized yet. Approved by Andrew.
llvm-svn: 119051
2010-11-14 18:24:41 +00:00
Chris Lattner
3e3e29381e
random acts of tidiness.
...
llvm-svn: 119049
2010-11-14 18:09:50 +00:00
Owen Anderson
ad4f83df6a
Second attempt at providing correct encodings for Thumb2 binary operators.
...
llvm-svn: 119029
2010-11-14 05:37:38 +00:00
Peter Collingbourne
4ec6b2dbe7
Recognise 32-bit ror-based bswap implementation used by uclibc
...
llvm-svn: 119007
2010-11-13 19:54:30 +00:00
Peter Collingbourne
6c3094234e
Support ; as asm separator
...
llvm-svn: 119006
2010-11-13 19:54:23 +00:00
Bill Wendling
49dd03e223
Comment out the defms until they're activated.
...
llvm-svn: 119000
2010-11-13 11:20:05 +00:00
Bill Wendling
fadcb3cded
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
...
llvm-svn: 118999
2010-11-13 10:57:02 +00:00
Bill Wendling
184bc1368d
Convert the modes to lower case.
...
llvm-svn: 118998
2010-11-13 10:43:34 +00:00
Bill Wendling
0a55425158
Minor cleanups:
...
- Get the opcode once.
- Add a ParserMatchClass to reglist.
llvm-svn: 118997
2010-11-13 10:40:19 +00:00
Bill Wendling
aa9ca6fcca
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
Daniel Dunbar
2ba9f79194
MC: Simplify Mach-O and ELF object writer implementations.
...
- What was I thinking?????
llvm-svn: 118992
2010-11-13 07:33:40 +00:00
Wesley Peck
4a2644f203
Fixed error and re-enabled MBlaze MC disassembler tests.
...
llvm-svn: 118987
2010-11-13 05:48:21 +00:00
Evan Cheng
239d9b439d
Conditional moves are slightly more expensive than moves.
...
llvm-svn: 118985
2010-11-13 05:14:20 +00:00
Wesley Peck
c534d55751
1. Adding test cases for MBlaze MC disassembler.
...
2. Fixing several errors in disassembler uncovered by test cases.
3. Fixing invalid encoding of PCMPEQ and PCMPNE uncovered by test cases.
llvm-svn: 118969
2010-11-13 02:37:59 +00:00
Evan Cheng
a7d3c3d387
Add conditional move of large immediate.
...
llvm-svn: 118968
2010-11-13 02:25:14 +00:00
Jim Grosbach
cab8b12f7a
Swap multiclass operand order for consistency with other patterns.
...
llvm-svn: 118965
2010-11-13 01:28:30 +00:00
Jim Grosbach
c8b3147ca5
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
...
instructions.
llvm-svn: 118963
2010-11-13 01:07:20 +00:00
Jim Grosbach
03eb1993ea
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
...
flag for the LDRT/STRT family instructions as a side effect.
llvm-svn: 118955
2010-11-13 00:35:48 +00:00
Dan Gohman
a4aa69cf2a
Revert r118917, which is implicated in the llvm-gcc-i386-linux-selfhost failure.
...
llvm-svn: 118954
2010-11-13 00:31:40 +00:00
Evan Cheng
a08372d4b4
Fix an obvious typo which inverted an immediate.
...
llvm-svn: 118951
2010-11-13 00:27:47 +00:00
Wesley Peck
28f124b047
1. Adding missing immediate mode asm parser test cases.
...
2. Fixing improper immediate mode reverse subtract.
llvm-svn: 118948
2010-11-13 00:03:46 +00:00
Eric Christopher
f6c7694c29
Temporarily revert this.
...
llvm-svn: 118946
2010-11-12 23:50:48 +00:00
Evan Cheng
1f5296d832
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
...
llvm-svn: 118945
2010-11-12 23:46:13 +00:00
Wesley Peck
f11db049fe
Fixing improperly encoded reverse subtract instructions in MBlaze backend.
...
llvm-svn: 118943
2010-11-12 23:41:10 +00:00
Owen Anderson
053d9fb9b5
Revert r118939 while I work out why it broke some buildbots.
...
llvm-svn: 118942
2010-11-12 23:36:03 +00:00
Wesley Peck
be71f5db40
1. Finishing MBlaze MC asm parser test cases
...
2. Parsing .word directive in MBlaze asm parser
3. Fixing hack where memory instructions reversed order of last two parameters
4. Fixing many improperly encoded instructions
5. Support parsing special instructions (MFS,MTS,etc.)
6. Removing unused functions from inst printer
llvm-svn: 118941
2010-11-12 23:30:17 +00:00
Owen Anderson
f8192cf0cc
Attemt to provide correct encodings for Thumb2 binary operators.
...
llvm-svn: 118939
2010-11-12 23:18:11 +00:00
Evan Cheng
f3c75f91e9
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
...
llvm-svn: 118938
2010-11-12 23:03:38 +00:00
Eric Christopher
b8ee838424
Make this happen for ARM like x86. Don't entirely bail out when
...
an address is in a different block, get it into a register and go
from there.
llvm-svn: 118936
2010-11-12 22:52:32 +00:00
Evan Cheng
19f018a1be
Add conditional mvn instructions.
...
llvm-svn: 118935
2010-11-12 22:42:47 +00:00
Jim Grosbach
e0ba69b81d
Zap a copy/paste-o bit of dead code.
...
llvm-svn: 118926
2010-11-12 21:29:10 +00:00
Jim Grosbach
eaaf8294a5
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
...
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
Owen Anderson
f1ffc8fdc9
First stab at providing correct Thumb2 encodings, start with adc.
...
llvm-svn: 118924
2010-11-12 21:12:40 +00:00
Evan Cheng
b565d1acf9
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
...
llvm-svn: 118922
2010-11-12 20:32:20 +00:00
Jim Grosbach
160cc37f73
Kill more unused stuff.
...
llvm-svn: 118921
2010-11-12 19:27:45 +00:00
Jim Grosbach
8bb507dd6b
Remove unused class.
...
llvm-svn: 118919
2010-11-12 19:24:53 +00:00
Dan Gohman
8b86287a06
When the definition of an address value is in a different block
...
from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.
llvm-svn: 118917
2010-11-12 19:14:00 +00:00
Chris Lattner
2a70c4e38a
accept lret as an alias for lretl, fixing the reopened part of PR8592
...
llvm-svn: 118916
2010-11-12 18:54:56 +00:00
Jim Grosbach
f9d1b45754
Fill in the default predication bits for ARM unconditional branch.
...
llvm-svn: 118907
2010-11-12 18:13:26 +00:00
Jim Grosbach
cbab1ea04e
Encoding for ARM LDRSB instructions.
...
llvm-svn: 118905
2010-11-12 17:52:59 +00:00
Chris Lattner
612039e538
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
...
llvm-svn: 118903
2010-11-12 17:41:20 +00:00
Chris Lattner
bcdb696f6c
tidy up.
...
llvm-svn: 118896
2010-11-12 17:24:29 +00:00
Kalle Raiskila
f89d0d0389
Fix memory access lowering on SPU, adding
...
support for the case where alignment<value size.
These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.
llvm-svn: 118889
2010-11-12 10:14:03 +00:00
Eric Christopher
1ca7518097
Fix up a few more spots of addrmode2 (or not) changes that were
...
missed. Update some comments accordingly.
Fixes rdar://8652289
llvm-svn: 118888
2010-11-12 09:48:30 +00:00
Dale Johannesen
659061fcd3
Remove possibly useful info from comment, per Chris.
...
llvm-svn: 118865
2010-11-12 00:43:18 +00:00
Bruno Cardoso Lopes
37f2439cbd
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
...
llvm-svn: 118864
2010-11-12 00:38:32 +00:00
Jim Grosbach
f00a6faa17
Start of support for binary emit of 16-it Thumb instructions.
...
llvm-svn: 118859
2010-11-11 23:41:09 +00:00
Owen Anderson
85cf1b8ff5
Fill out support for Thumb2 encodings of NEON instructions.
...
llvm-svn: 118854
2010-11-11 23:12:55 +00:00
Wesley Peck
7974f4c201
The BRK instruction in the MicroBlaze is a branch-and-link.
...
llvm-svn: 118848
2010-11-11 22:21:08 +00:00
Wesley Peck
0e937ae80d
Fix tblgen instruction errors exposed by MC asm parser tests
...
Fix minimum 16-bit signed value error exposed by MC asm parser tests
Add initial MC asm parser tests for the MBlaze backend
llvm-svn: 118844
2010-11-11 21:40:53 +00:00
Owen Anderson
0913dac245
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
...
llvm-svn: 118843
2010-11-11 21:36:43 +00:00
Eric Christopher
474a93ff76
Revert the accidental commit I made reverting the previous commit.
...
llvm-svn: 118835
2010-11-11 20:50:14 +00:00
Jim Grosbach
cc8e5dc0c6
ARM fixup encoding for direct call instructions (BL).
...
llvm-svn: 118829
2010-11-11 20:05:40 +00:00
Eric Christopher
e7f27cf66a
Revert this temporarily.
...
llvm-svn: 118827
2010-11-11 19:47:02 +00:00
Eric Christopher
beb7a50acb
Change the prologue and epilogue to use push/pop for the low ARM registers.
...
llvm-svn: 118823
2010-11-11 19:26:03 +00:00
Owen Anderson
f43f09f6f6
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
...
More tests to come.
llvm-svn: 118819
2010-11-11 19:07:48 +00:00
Wesley Peck
9ad36509f8
Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code.
...
llvm-svn: 118807
2010-11-11 18:41:33 +00:00
Chris Lattner
b3eff154cd
add a note
...
llvm-svn: 118806
2010-11-11 18:23:57 +00:00
Jim Grosbach
abf0e10ea0
Encoding of destination fixup for ARM branch and conditional branch
...
instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
Chris Lattner
3514fa6b11
add pr#
...
llvm-svn: 118797
2010-11-11 17:17:56 +00:00
Jim Grosbach
cfc32e3b5a
Encoding for ARM LDRSH_POST.
...
llvm-svn: 118794
2010-11-11 16:55:29 +00:00
Rafael Espindola
5766346831
Remove some explicit arguments to getELFSection. This is
...
a leftover from the removal of isExplicit.
llvm-svn: 118774
2010-11-11 03:40:25 +00:00
Jim Grosbach
8cb10f8def
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
...
llvm-svn: 118767
2010-11-11 01:55:59 +00:00
Jim Grosbach
b86e183a33
Fix encoding of Ra register for ARM smla* instructions.
...
llvm-svn: 118761
2010-11-11 01:27:41 +00:00
Jim Grosbach
3b13f9013c
ARM STRH encoding information.
...
llvm-svn: 118757
2010-11-11 01:09:40 +00:00
Jim Grosbach
2c1d6373ab
Move LDM predicate operand encoding into base clase. Add STM missing STM
...
encoding bits.
llvm-svn: 118738
2010-11-10 23:44:32 +00:00
Jim Grosbach
ad037e5ded
ARM LDM encoding for the mode (ia, ib, da, db) operand.
...
llvm-svn: 118736
2010-11-10 23:38:36 +00:00
Jim Grosbach
ef95eee920
Fix ARM encoding of non-return LDM instructions.
...
llvm-svn: 118732
2010-11-10 23:18:49 +00:00
Jim Grosbach
d832c84199
Fix ARM encoding of LDM+Return instruction.
...
llvm-svn: 118730
2010-11-10 23:12:48 +00:00
Nate Begeman
c4fabeabb9
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
...
llvm-svn: 118720
2010-11-10 21:35:41 +00:00
Jim Grosbach
c5001c0f1d
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
...
double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
llvm-svn: 118688
2010-11-10 17:59:10 +00:00
Jim Grosbach
4e3653e4e1
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
...
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
llvm-svn: 118671
2010-11-10 03:26:07 +00:00
Bruno Cardoso Lopes
2266e58196
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
...
llvm-svn: 118667
2010-11-10 02:13:22 +00:00
Bill Wendling
87c781b411
Emit a '!' if this is a "writeback" register or memory address.
...
llvm-svn: 118662
2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay
993d07638e
Rename a parameter to avoid confusion with a local variable
...
llvm-svn: 118656
2010-11-10 00:08:58 +00:00
Bill Wendling
0c082b811f
Emit the warning about the register list not being in ascending order only once.
...
llvm-svn: 118653
2010-11-09 23:45:59 +00:00
Bill Wendling
8cfb0a507e
s/std::vector/SmallVector/
...
llvm-svn: 118648
2010-11-09 23:28:44 +00:00
Bill Wendling
01897eaa4e
Delete the allocated vector.
...
llvm-svn: 118644
2010-11-09 22:51:42 +00:00
Bob Wilson
03a878a419
Define the subtarget feature for the architecture version,
...
as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
llvm-svn: 118643
2010-11-09 22:50:47 +00:00
Bob Wilson
a933ce4caa
Do not use MEMBARRIER_MCR for any Thumb code.
...
It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
llvm-svn: 118642
2010-11-09 22:50:44 +00:00
Bill Wendling
63cfae801d
Two types of instructions have register lists:
...
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
llvm-svn: 118640
2010-11-09 22:44:22 +00:00
Jim Grosbach
be0d795478
Change the ARMConstantPoolValue modifier string to an enumeration. This will
...
help in MC'izing the references that use them.
llvm-svn: 118633
2010-11-09 21:36:17 +00:00
Jim Grosbach
d98cc456d2
Handle ARM constant pool values that need an explicit reference to the '.'
...
pseudo-label. (TLS stuff).
llvm-svn: 118609
2010-11-09 19:40:22 +00:00
Chris Lattner
d7d7d5717b
add a case we fail to devirt.
...
llvm-svn: 118608
2010-11-09 19:37:28 +00:00
Jim Grosbach
ce5c2dbeae
Trailing whitespace.
...
llvm-svn: 118606
2010-11-09 19:22:26 +00:00
Jim Grosbach
2c60dfb555
Further MCize ARM constant pool values. This allows basic PIC references for
...
object file emission.
llvm-svn: 118601
2010-11-09 18:45:04 +00:00
Jim Grosbach
abe68922ca
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
...
llvm-svn: 118600
2010-11-09 18:43:54 +00:00
Jim Grosbach
08310de036
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
...
a left shift by zero.
llvm-svn: 118587
2010-11-09 17:38:15 +00:00
Jim Grosbach
0a8517fd62
ARM .word data fixups don't need an adjustment.
...
llvm-svn: 118586
2010-11-09 17:36:59 +00:00
Bruno Cardoso Lopes
81f7b26109
Fix trailing whitespace and style, no functionality change
...
llvm-svn: 118515
2010-11-09 17:25:34 +00:00
Jim Grosbach
f64560f315
Add encoder method for ARM load/store shifted register offset operands.
...
llvm-svn: 118513
2010-11-09 17:20:53 +00:00
Jim Grosbach
0b06d57ccd
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
...
constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
llvm-svn: 118469
2010-11-09 01:37:15 +00:00
Bill Wendling
41fb74d268
Revert r118457 and r118458. These won't hold for GPRs.
...
llvm-svn: 118462
2010-11-09 00:30:18 +00:00
Bill Wendling
f080f8ddfe
Get the register and count from the register list operands.
...
llvm-svn: 118458
2010-11-08 23:51:20 +00:00
Bill Wendling
ab76e02a12
reglist has two operands.
...
llvm-svn: 118457
2010-11-08 23:50:20 +00:00
Bill Wendling
2ff2ee2765
The "addRegListOperands()" function returns the start register and the total
...
number of registers in the list.
llvm-svn: 118456
2010-11-08 23:49:57 +00:00
Owen Anderson
52e3873edc
Add support for ARM's specialized vector-compare-against-zero instructions.
...
llvm-svn: 118453
2010-11-08 23:21:22 +00:00
Bruno Cardoso Lopes
64dd957550
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
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llvm-svn: 118447
2010-11-08 21:42:32 +00:00
Bill Wendling
3e6eee5c35
Add "write back" bit encoding.
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llvm-svn: 118446
2010-11-08 21:28:03 +00:00
Bruno Cardoso Lopes
9f9f796756
Fix PR8211
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llvm-svn: 118445
2010-11-08 21:24:59 +00:00
Wesley Peck
f3909b741f
Adding working version of assembly parser for the MBlaze backend
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Major cleanup of whitespace and formatting issues in MBlaze backend
llvm-svn: 118434
2010-11-08 19:40:01 +00:00
Dale Johannesen
f16acd1325
Revert 118422 in search of bot verdancy.
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llvm-svn: 118429
2010-11-08 19:17:22 +00:00
Jason W Kim
a253ed4e26
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
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llvm-svn: 118422
2010-11-08 17:58:07 +00:00
Jason W Kim
c43f11132e
Complete listing of ARM/MC/ELF relocation enums
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llvm-svn: 118413
2010-11-08 16:47:27 +00:00
Che-Liang Chiou
6ba699c749
Add generating function declaration for PTX
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llvm-svn: 118398
2010-11-08 03:06:08 +00:00
Che-Liang Chiou
e207994d1b
Add physical register counting functions
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llvm-svn: 118397
2010-11-08 03:00:52 +00:00
Che-Liang Chiou
e2c8a54474
Add a dummy PTXMCAsmStreamer class
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llvm-svn: 118396
2010-11-08 02:58:44 +00:00
Bill Wendling
19873cf3ff
Make RegList an ASM operand so that TableGen will generate code for it. This is
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an initial implementation and may change once reglists are fully fleshed out.
llvm-svn: 118390
2010-11-08 00:39:58 +00:00
Bill Wendling
611dbaee50
Revert.
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llvm-svn: 118389
2010-11-08 00:32:40 +00:00
Duncan Sands
c9c7d54930
Fix a README item: when doing a comparison with the result
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of a select instruction, see if doing the compare with the
true and false values of the select gives the same result.
If so, that can be used as the value of the comparison.
llvm-svn: 118378
2010-11-07 16:12:23 +00:00
Bill Wendling
1338bc5cac
In this context, a reglist is a reg.
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llvm-svn: 118375
2010-11-07 13:08:28 +00:00
Chris Lattner
24ba201941
implement aliases for div/idiv that have an explicit A register operand,
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implementing rdar://8431864
llvm-svn: 118364
2010-11-06 22:41:18 +00:00
Bill Wendling
0493b6982a
Add support for parsing register lists. We can't use a bitfield to keep track of
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the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
llvm-svn: 118363
2010-11-06 22:36:58 +00:00
Chris Lattner
25f31dcc8f
add aliases for movs between seg registers and mem. There are multiple
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different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
llvm-svn: 118362
2010-11-06 22:35:34 +00:00
Chris Lattner
5cd42cb6f4
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.
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llvm-svn: 118361
2010-11-06 22:25:39 +00:00
Bill Wendling
7e32b2f98a
Return the base register of a register list for the "getReg()" method. This is
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to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
llvm-svn: 118360
2010-11-06 22:19:43 +00:00
Chris Lattner
95add4d79a
work-in-progress
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llvm-svn: 118358
2010-11-06 22:05:43 +00:00
Bill Wendling
dabc5e5b02
General cleanup:
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- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
llvm-svn: 118357
2010-11-06 21:42:12 +00:00
Chris Lattner
0d6d870628
go to great lengths to work around a GAS bug my previous patch
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exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
llvm-svn: 118356
2010-11-06 21:37:06 +00:00
Chris Lattner
bbd318b76a
rework the rotate-by-1 instructions to be defined like the
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shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
llvm-svn: 118355
2010-11-06 21:23:40 +00:00
Chris Lattner
af1f50772a
change the fp comparison instructions to not have %st0 explicitly
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listed in its asm string, for consistency with the other similar
instructions.
llvm-svn: 118354
2010-11-06 20:55:09 +00:00
Chris Lattner
b64f8e10ab
move the plethora of fp stack aliases to the .td file.
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llvm-svn: 118353
2010-11-06 20:47:38 +00:00
Chris Lattner
4834890f0a
add (and document) the ability for alias results to have
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fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
llvm-svn: 118352
2010-11-06 19:57:21 +00:00
Bill Wendling
ac0e90a877
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
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(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
llvm-svn: 118351
2010-11-06 19:56:04 +00:00
Chris Lattner
c0e756dc47
generalize alias support to allow the result of an alias to
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add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
llvm-svn: 118350
2010-11-06 19:25:43 +00:00
Chris Lattner
a7c7312e55
move fnstsw aliases to .td file, fix typo
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llvm-svn: 118349
2010-11-06 18:58:32 +00:00
Chris Lattner
b686fb93c7
move in/out aliases to the .td files.
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llvm-svn: 118348
2010-11-06 18:52:40 +00:00
Chris Lattner
6b905e3a10
move sldt, imul, and movabsq aliases from c++ to .td file.
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llvm-svn: 118347
2010-11-06 18:44:26 +00:00
Chris Lattner
1beb2b3fc5
correct suffix matching to search for s/l/t suffixes on
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floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
llvm-svn: 118346
2010-11-06 18:28:02 +00:00
Bill Wendling
e35565699c
Fix grammar.
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llvm-svn: 118341
2010-11-06 10:51:53 +00:00
Bill Wendling
84ce225095
Fix grammar.
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llvm-svn: 118340
2010-11-06 10:48:18 +00:00
Bill Wendling
f2e9379095
MatchRegisterName() returns 0 if it can't match the register.
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llvm-svn: 118339
2010-11-06 10:45:34 +00:00
Bill Wendling
f65f39e7a1
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
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while the latter doesn't.
llvm-svn: 118338
2010-11-06 10:40:24 +00:00
Benjamin Kramer
16b841c233
Add a note.
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llvm-svn: 118337
2010-11-06 10:37:16 +00:00
Chris Lattner
637f4910c3
fix a bug where we had an implicit assumption that the
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result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
llvm-svn: 118334
2010-11-06 08:20:59 +00:00
Eric Christopher
3a51a4ada2
Make sure we have movw on the target before using it.
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Fixes 8559.
llvm-svn: 118333
2010-11-06 07:53:11 +00:00
Chris Lattner
4fd3b4ad94
move the lcall/ljmp aliases to the .td file.
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llvm-svn: 118332
2010-11-06 07:48:45 +00:00
Chris Lattner
66c868f386
move the "movsd -> movsl" alias to the .td files,
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tidy up the movsx and movzx aliases.
llvm-svn: 118331
2010-11-06 07:34:58 +00:00
Chris Lattner
ec0ef3385d
fix some bugs in the alias support, unblocking changing of "clr" aliases
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from c++ hacks to proper .td InstAlias definitions. Change them!
llvm-svn: 118330
2010-11-06 07:31:43 +00:00
Chris Lattner
5d1361e9ed
Reimplement BuildResultOperands to be in terms of the result instruction's
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operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
llvm-svn: 118329
2010-11-06 07:14:44 +00:00
Jim Grosbach
009007e690
Hook up the '.code {16|32}' directive to the streamer.
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llvm-svn: 118310
2010-11-05 22:40:53 +00:00
Jim Grosbach
3d432a39dd
Hook up the '.thumb_func' directive to the streamer.
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llvm-svn: 118307
2010-11-05 22:33:53 +00:00
Jim Grosbach
dfa87da932
Fix past-o.
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llvm-svn: 118304
2010-11-05 22:11:33 +00:00
Jim Grosbach
bbef2c5fcc
MC'ize the '.code 16' and '.thumb_func' ARM directives.
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llvm-svn: 118301
2010-11-05 22:08:08 +00:00
Owen Anderson
f26ea37db7
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
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llvm-svn: 118300
2010-11-05 21:57:54 +00:00
Jim Grosbach
55b250bb64
MC'ize simple ARMConstantValue entry emission (with a FIXME).
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llvm-svn: 118295
2010-11-05 20:34:24 +00:00
Owen Anderson
add19dd6dd
Add codegen and encoding support for the immediate form of vbic.
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llvm-svn: 118291
2010-11-05 19:27:46 +00:00
Jim Grosbach
1ee24bfd45
Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work
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(relocations, e.g.), but this will allow simple things to flow through.
llvm-svn: 118289
2010-11-05 18:50:35 +00:00
Jim Grosbach
a85416eb77
Allow targets to specify the MachO CPUType/CPUSubtype information.
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llvm-svn: 118288
2010-11-05 18:48:58 +00:00
Jim Grosbach
49dd16ea6f
Add FIXME.
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llvm-svn: 118280
2010-11-05 17:37:13 +00:00
Duncan Sands
1af5c00d3c
When passing a huge parameter using the byval mechanism, a long
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sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead. PR7170.
llvm-svn: 118260
2010-11-04 21:16:46 +00:00
Duncan Sands
3bf2a701a5
In the calling convention logic, ValVT is always a legal type,
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and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
Evan Cheng
165e65f53a
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
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llvm-svn: 118237
2010-11-04 05:19:35 +00:00
Jim Grosbach
9766b186b6
Add ARM fixup info for load/store label references. Probably will need a bit of
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tweaking when we start using it for object file emission or JIT, but it's a
start.
llvm-svn: 118221
2010-11-04 01:12:30 +00:00
Bill Wendling
990c247994
Add encoding for VSTR.
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llvm-svn: 118220
2010-11-04 00:59:42 +00:00
Jim Grosbach
af6104d4bf
Teach ARM Target to use the tblgen support for generating an MC'ized
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CodeEmitter.
llvm-svn: 118209
2010-11-03 23:52:49 +00:00
Owen Anderson
d144bb1ddc
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
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This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
llvm-svn: 118204
2010-11-03 23:15:26 +00:00
Owen Anderson
1a89511e5d
Add support for code generation of the one register with immediate form of vorr.
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We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
llvm-svn: 118201
2010-11-03 22:44:51 +00:00
Jim Grosbach
6c197e41bf
trailing whitespace
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llvm-svn: 118199
2010-11-03 22:03:20 +00:00
Eric Christopher
6b586a109e
Optimize generated code for integer materialization a bit.
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llvm-svn: 118192
2010-11-03 20:21:17 +00:00
Owen Anderson
98f9965c89
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
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all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
llvm-svn: 118183
2010-11-03 18:16:27 +00:00
Bob Wilson
f44e708279
Add codegen patterns for VST1-lane instructions. Radar 8599955.
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llvm-svn: 118176
2010-11-03 16:24:53 +00:00
Bob Wilson
0ec96428ba
Check for extractelement with a variable operand for the element number.
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For NEON we had been assuming this was always an immediate constant.
llvm-svn: 118175
2010-11-03 16:24:50 +00:00
Duncan Sands
41edf30895
Simplify uses of MVT and EVT. An MVT can be compared directly
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with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
2010-11-03 12:17:33 +00:00
Duncan Sands
f6e5e02c9b
Inside the calling convention logic LocVT is always a simple
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
Evan Cheng
eab7251695
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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llvm-svn: 118160
2010-11-03 06:34:55 +00:00
Evan Cheng
b41703bc2f
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
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llvm-svn: 118152
2010-11-03 05:14:24 +00:00
Bill Wendling
3894287c96
Put the PC encoding in the correct bit position.
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llvm-svn: 118151
2010-11-03 04:57:44 +00:00
Eric Christopher
bc79fa1c9e
Invert these branches by default, it makes assembly comparisons a little
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easier to read.
llvm-svn: 118148
2010-11-03 04:29:11 +00:00
Bill Wendling
34599f4aa8
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
Jim Grosbach
90a084bac2
Remove unused function.
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llvm-svn: 118141
2010-11-03 01:35:15 +00:00
Jim Grosbach
d3213d4048
Remove the no longer used 'Modifier' optional operand to the ARM
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printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
2010-11-03 01:11:15 +00:00
Jim Grosbach
4d6b503b4c
Remove unused function.
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llvm-svn: 118139
2010-11-03 01:07:48 +00:00
Jim Grosbach
c10d3f3d4b
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
Evan Cheng
67db408634
Two sets of changes. Sorry they are intermingled.
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1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
llvm-svn: 118135
2010-11-03 00:45:17 +00:00
Evan Cheng
e156473432
Modify scheduling itineraries to correct instruction latencies (not operand
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latencies) of loads.
llvm-svn: 118134
2010-11-03 00:40:22 +00:00