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Commit Graph

203899 Commits

Author SHA1 Message Date
Roman Lebedev
33cace0561 [SCEV] Recognize @llvm.abs as smax(x, -x)
As per alive2 (ignoring undef):

----------------------------------------
define i32 @src(i32 %x, i1 %y) {
%0:
  %r = abs i32 %x, 0
  ret i32 %r
}
=>
define i32 @tgt(i32 %x, i1 %y) {
%0:
  %neg_x = mul i32 %x, 4294967295
  %r = smax i32 %x, %neg_x
  ret i32 %r
}
Transformation seems to be correct!

----------------------------------------
define i32 @src(i32 %x, i1 %y) {
%0:
  %r = abs i32 %x, 1
  ret i32 %r
}
=>
define i32 @tgt(i32 %x, i1 %y) {
%0:
  %neg_x = mul nsw i32 %x, 4294967295
  %r = smax i32 %x, %neg_x
  ret i32 %r
}
Transformation seems to be correct!
2020-09-21 20:25:53 +03:00
Roman Lebedev
a776b0a84c [NFC][SCEV] Add tests for @llvm.abs intrinsic 2020-09-21 20:25:53 +03:00
Simon Pilgrim
93c97aff7a [SLP] Use for-range loops across ValueLists. NFCI.
Also rename some existing loops that used a 'j' iterator to consistently use 'V'.
2020-09-21 18:24:23 +01:00
Dave Lee
891c239142 [cmake] Centralize LLVM_ENABLE_WARNINGS option
Configure default value of `LLVM_ENABLE_WARNINGS` in `HandleLLVMOptions.cmake`.

`LLVM_ENABLE_WARNINGS` is documented as ON by default, but `HandleLLVMOptions` assumes the default has been set somewhere else. If it has not been explicitly set, then `HandleLLVMOptions` implicitly uses OFF as a default.

This removes the various `option()` declarations in favor of a single declaration in `HandleLLVMOptions`. This will prevent the unwanted use of `-w` that is mentioned in a couple of the comments.

Reviewed By: DavidTruby, #libunwind, JDevlieghere, compnerd

Differential Revision: https://reviews.llvm.org/D87243
2020-09-21 10:23:17 -07:00
Sanjay Patel
5c7666e423 [SLP] simplify interface for gather(); NFC
The implementation of gather() should be reduced too,
but this change by itself makes things a little clearer:
we don't try to gather to a different type or
number-of-values than whatever is passed in as the value
list itself.
2020-09-21 12:57:28 -04:00
Simon Pilgrim
e0ca7afdf4 ImplicitNullChecks.cpp - use auto const& iterators in for-range loops to avoid copies. NFCI. 2020-09-21 17:42:57 +01:00
Florian Hahn
8648993934 [SCEV] Add additional max BTC tests with loop guards. 2020-09-21 17:41:24 +01:00
Arthur Eubanks
1a477f367f [ObjCARC][NewPM] Port objc-arc-contract to NPM
Similar to https://reviews.llvm.org/D86178.

This is a module pass instead of a function pass since
ARCRuntimeEntryPoints can lazily add function declarations.

Reviewed By: ahatanak

Differential Revision: https://reviews.llvm.org/D87806
2020-09-21 09:40:14 -07:00
Momchil Velikov
85f907b9af [ARM][CMSE] Issue an error if passing arguments through memory across
security boundary

It was never supported and that part was accidentally omitted when
upstreaming D76518.

Differential Revision: https://reviews.llvm.org/D86478

Change-Id: If6ba9506eb0431c87a1d42a38aa60e47ce263039
2020-09-21 17:26:10 +01:00
Simon Pilgrim
1f062b848e TargetPassConfig.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI. 2020-09-21 17:17:11 +01:00
Simon Pilgrim
40596098d9 SLPVectorizer.cpp - fix include ordering. NFCI. 2020-09-21 17:17:11 +01:00
Simon Pilgrim
bb00c44c2f MachineCSE.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI. 2020-09-21 16:54:26 +01:00
Simon Pilgrim
8597b6c759 Fix Wdocumentation unknown parameter warnings. NFCI. 2020-09-21 16:54:26 +01:00
Simon Pilgrim
31aa31919a ProfileSummary.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI. 2020-09-21 16:54:26 +01:00
David Sherwood
34f10ad200 [SVE][CodeGen] Mark ptrue/pfalse instructions as rematerializable 2020-09-21 16:44:32 +01:00
Cyndy Ishida
efc5b116e0 [TextAPI] clean up auto usages in tests, NFC 2020-09-21 08:39:40 -07:00
Baptiste Saleil
85360aaf7b [PowerPC] Add vector pair load/store instructions and vector pair register class
This patch adds support for the lxvp, lxvpx, plxvp, stxvp, stxvpx and pstxvp
instructions in the PowerPC backend. These instructions allow loading and
storing VSX register pairs. This patch also adds the VSRp register class
definition needed for these instructions.

Differential Revision: https://reviews.llvm.org/D84359
2020-09-21 10:27:47 -05:00
Arthur Eubanks
33cc850aa4 [LoopSimplifyCFG][NewPM] Rename simplify-cfg -> loop-simplifycfg
This matches the legacy PM name and makes all tests in
Transforms/LoopSimplifyCFG pass under NPM.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D87948
2020-09-21 08:27:19 -07:00
Simon Pilgrim
1e7924bec0 [CostModel][X86] Add some select shuffle costs tests for D87884 2020-09-21 16:09:05 +01:00
Simon Pilgrim
c24ea426d7 Update update_analyze_test_checks.py to support API changes from D83004 2020-09-21 16:09:05 +01:00
Alexey Bataev
9d0d65e027 [SLP] Allow reordering of vectorization trees with reused instructions.
If some leaves have the same instructions to be vectorized, we may
incorrectly evaluate the best order for the root node (it is built for the
vector of instructions without repeated instructions and, thus, has less
elements than the root node). In this case we just can not try to reorder
the tree + we may calculate the wrong number of nodes that requre the
same reordering.
For example, if the root node is \<a+b, a+c, a+d, f+e\>, then the leaves
are \<a, a, a, f\> and \<b, c, d, e\>. When we try to vectorize the first
leaf, it will be shrink to \<a, b\>. If instructions in this leaf should
be reordered, the best order will be \<1, 0\>. We need to extend this
order for the root node. For the root node this order should look like
\<3, 0, 1, 2\>. This patch allows extension of the orders of the nodes
with the reused instructions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D45263
2020-09-21 10:51:03 -04:00
Simon Pilgrim
9143c682a5 DWARFEmitter.cpp - use auto const& iterators in for-range loops to avoid copies. NFCI. 2020-09-21 15:33:09 +01:00
Paul C. Anagnostopoulos
0f7c7ec819 Change comments about order of classes in superclass list. 2020-09-21 10:25:44 -04:00
Georgii Rymar
9a3425f583 [llvm-readobj/libObject] - Get rid of FirstSym argument. NFCI.
We use `FirstSym` argument in `getExtendedSymbolTableIndex` to calculate
a symbol index:

```
&Sym - &FirstSym
```

Instead, we could pass the symbol index directly.
This is what this patch does, it allows to simplify another llvm-readobj API.

Differential revision: https://reviews.llvm.org/D88016
2020-09-21 16:07:50 +03:00
Simon Pilgrim
163f47116d DWARFYAML::emitDebugSections - remove unnecessary cantFail(success) call. NFCI.
As mentioned on rG6bb912336804.
2020-09-21 14:07:11 +01:00
LLVM GN Syncbot
3f2961bc88 [gn build] Port 4fc0214a101 2020-09-21 12:47:54 +00:00
Denis Antrushin
20a567ec78 [Statepoints][ISEL] gc.relocate uniquification should be based on SDValue, not IR Value.
When exporting statepoint results to virtual registers we try to avoid
generating exports for duplicated inputs. But we erroneously use
IR Value* to check if inputs are duplicated. Instead, we should use
SDValue, because even different IR values can get lowered to the same
SDValue.
I'm adding a (degenerate) test case which emphasizes importance of this
feature for invoke statepoints.
If we fail to export only unique values we will end up with something
like that:

  %0 = STATEPOINT
  %1 = COPY %0

landing_pad:
  <use of %1>

And when exceptional path is taken, %1 is left uninitialized (COPY is never
execute).

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D87695
2020-09-21 19:44:46 +07:00
Paul Walker
37b56bbc5e [SVE] Change definition of reduction ISD nodes to have an SVE vector result type.
The current nodes, AArch64::SMAXV_PRED for example, are defined to
return a NEON vector result.  This is incorrect because they modify
the complete SVE register and are thus changed to represent such.

This patch also adds nodes for UADDV_PRED and SADDV_PRED, which
unifies the handling of all SVE reductions.

NOTE: Floating-point reductions are already implemented correctly,
so this patch is essentially making everything consistent with those.

Differential Revision: https://reviews.llvm.org/D87843
2020-09-21 13:16:28 +01:00
Paul Walker
6eee9eb46a [SVE] Use NEON for extract_vector_elt when the index is in range.
Patch also adds missing patterns for unpacked vector types and
extracts of element zero.

Differential Revision: https://reviews.llvm.org/D87842
2020-09-21 13:12:28 +01:00
Alexander Belyaev
da4afc0c02 Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
This reverts commit 0345d88de654259ae90494bf9b015416e2cccacb.

Google internal backend uses EntrySU, we are looking into removing
dependency on it.

Differential Revision: https://reviews.llvm.org/D88018
2020-09-21 13:33:05 +02:00
Florian Hahn
77b449d743 Recommit "[SCEV] Look through single value PHIs."
This commit was originally because it was suspected to cause a crash,
but a reproducer did not surface.

A crash that was exposed by this change was fixed in 1d8f2e52925b.

This reverts the revert commit 0581c0b0eeba03da590d1176a4580cf9b9e8d1e3.
2020-09-21 11:59:50 +01:00
David Green
c8c6d59c71 [ARM] Select f32 constants with vmov.f16
This adds lowering for f32 values using the vmov.f16, which zeroes the
top bits whilst setting the lower bits to a pattern. This range of
values does not often come up, except where a f16 constant value has
been converted to a f32.

Differential Revision: https://reviews.llvm.org/D87790
2020-09-21 11:10:47 +01:00
Georgii Rymar
3caa549f90 [llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols.
We have an issue with `ELFDumper<ELFT>::getSymbolSectionName`:
1) It is used deeply for both LLVM/GNU styles and might return LLVM-style only
   values to describe symbols: "Undefined", "Processor Specific", "Absolute", etc.

2) `getSymbolSectionName` is used by `getFullSymbolName` and these special values
   might appear instead of symbol names in many places.
   This occurs for unnamed section symbols currently.

This patch extracts the LLVM specific logic to `LLVMStyle<ELFT>::printSymbolSection`,
which seems to be the only place where we want to print the special values mentioned.
It also adds a meaningful new warning that is reported when we are unable to get
a section index for a section symbol.

Differential revision: https://reviews.llvm.org/D87764
2020-09-21 13:05:46 +03:00
Sam Parker
a9b02cf295 [NFC][ARM] More tail predication tests.
Add mir tests for use/def of P0.
2020-09-21 10:58:05 +01:00
Sjoerd Meijer
622615c7ad [AArch64] Cortex-A55 scheduler model
This is an initial commit adding the A55 model, but it isn't used/enabled yet.
We will follow up on this to improve the model, then flip the switch.

The optimisation guide describing Cortex-A55 micro-architecture in more detail
can be found here:

https://static.docs.arm.com/epm128372/20/arm_cortex_a55_software_optimization_guide_v2.pdf

Original patch by Javed Absar.

Differential Revision: https://reviews.llvm.org/D46884
2020-09-21 10:54:32 +01:00
Alex Richardson
01addf8046 [RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
This does not result in changes for any of the current tests, but it might
improve debug information in some cases.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D86522
2020-09-21 10:21:11 +01:00
Max Kazantsev
562da2bbfa [Test] Test auto-update 2020-09-21 16:06:18 +07:00
Lucas Prates
438b0e34bd [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder
SelectionDAGBuilder was inconsistently mangling values based on ABI
Calling Conventions when getting them through copyFromRegs in
SelectionDAGBuilder, causing duplicate value type convertions for
function arguments. The checking for the mangling requirement was based
on the value's originating instruction and was performed outside of, and
inspite of, the regular Calling Convention Lowering.

The issue could be observed in a scenario such as:

```
%arg1 = load half, half* %const, align 2
%arg2 = call fastcc half @someFunc()
call fastcc void @otherFunc(half %arg1, half %arg2)
; Here, %arg2 was incorrectly mangled twice, as the CallConv data from
; the call to @someFunc() was taken into consideration for the check
; when getting the value for processing the call to @otherFunc(...),
; after the proper convertion had taken place when lowering the return
; value of the first call.
```

This patch fixes the issue by disregarding the Calling Convention
information for such copyFromRegs, making sure the ABI mangling is
properly contanined in the Calling Convention Lowering.

This fixes Bugzilla #47454.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87844
2020-09-21 10:05:34 +01:00
Florian Hahn
fe09f259f9 [LSR] Preserve MSSA when using SplitCriticalEdge.
LSR claims to MemorySSA, but we also have to make sure it is preserved
when splitting critical edges. This can be done by passing MSSAU to
SplitCriticalEdge.

Fixes PR47557.
2020-09-21 09:51:26 +01:00
Fangrui Song
e6e7c80f0e [EHStreamer] Fix a "Continue to action" -fverbose-asm comment when multi-byte LEB128 encoding is needed
This only happens with more than 64 action records and it is difficult to construct a test.
2020-09-20 21:41:48 -07:00
Qiu Chaofan
d6e49b7d70 [PowerPC] Pass nofpexcept flag to custom lowered constrained ops
This is a follow-up of D86605. For strict DAG FP node, if its FP
exception behavior metadata is ignore, it should have nofpexcept flag.
But during custom lowering, this flag isn't passed down.

This is also seen on X86 target.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D87390
2020-09-21 10:44:25 +08:00
Fangrui Song
4dabbec93d [XRay] Change mips to use version 2 sled (PC-relative address)
Follow-up to D78590. All targets use PC-relative addresses now.

Reviewed By: atanasyan, dberris

Differential Revision: https://reviews.llvm.org/D87977
2020-09-20 17:59:57 -07:00
wlei
e56a524153 [llvm-profdata]Fix llvm-profdata crash on compact binary profile
llvm-profdata `show` and `overlap` will crash in `getFuncName` on compact binary profile. This change fixed this by switching to use `getName`.

 `getFuncName` is misused in llvm-profdata. As showed below, `GUIDToFuncNameMap` is only supported in compilation mode, there is no initialization in llvm-profdata. Compact profile whose MD5 is true would try to query `GUIDToFuncNameMap` then caused the crash. So fix this by switching to `getName`

Reviewed By: MaskRay, wmi, wenlei, weihe, hoy

Differential Revision: https://reviews.llvm.org/D87740
2020-09-20 16:58:34 -07:00
Craig Topper
634488ce52 [X86] Make reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore work for avx512 after type legalization.
The scalar elements of the vXi1 build_vector will have been type legalized to i8 by padding with 0s. So we can't check for all ones. Instead we should just look at bit 0 of the constant.

Differential Revision: https://reviews.llvm.org/D87863
2020-09-20 13:54:20 -07:00
Craig Topper
5cf94a6388 [X86] Pre-commit test cases for D87863. NFC 2020-09-20 13:53:05 -07:00
Craig Topper
aa3ccaf198 [X86] Stop reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore from creating scalar i64 load/stores in 32-bit mode
If we emit a scalar i64 load/store it will get type legalized to two i32 load/stores.

Differential Revision: https://reviews.llvm.org/D87862
2020-09-20 13:46:59 -07:00
Craig Topper
b826feba37 [X86] Add 32-bit command lines to masked_store.ll and masked_load.ll 2020-09-20 13:46:59 -07:00
David Green
aa89df6c4c [ARM] Constant fold VMOVrh
This adds simple constant folding for VMOVrh, to constant fold fp16
constants to integer values. It can help especially with soft calling
conventions, but some of the results are not optimal as we end up
loading using a vldr. This will be improved in a follow up patch.

Differential Revision: https://reviews.llvm.org/D87789
2020-09-20 21:32:51 +01:00
Nikita Popov
f5e86efea8 [CVP] Additional tests for comparison with offset (NFC)
Both icmps have an additional offset here. We would fold this if
the second one didn't.
2020-09-20 22:10:34 +02:00
Nikita Popov
766062255a [LVI] Get value range from mask comparison
InstCombine likes to canonicalize comparisons of the form
X == C || X == C+1 into (X & -2) == C'. Make sure LVI can still
recover the value range from this. Can of course also be useful
for proper mask comparisons.

For the sake of clarity, the implementation goes through KnownBits
to compute the range.
2020-09-20 21:13:57 +02:00