Owen Anderson
4106b9fb31
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
Jim Grosbach
14720bed32
Thumb2 parsing and encoding for ISB.
...
llvm-svn: 139200
2011-09-06 22:53:27 +00:00
Jim Grosbach
521a061450
Thumb2 parsing and encoding for EOR.
...
llvm-svn: 139199
2011-09-06 22:44:50 +00:00
Jim Grosbach
463bf279d6
Thumb2 parsing and encoding for DSB.
...
llvm-svn: 139194
2011-09-06 22:19:40 +00:00
Jim Grosbach
276e51888c
Thumb2 parsing and encoding for DMB.
...
llvm-svn: 139193
2011-09-06 22:14:58 +00:00
Jim Grosbach
c0aaa747a1
Thumb2 parsing and encoding for DBG.
...
llvm-svn: 139191
2011-09-06 22:06:40 +00:00
Jim Grosbach
4258d5ffba
Thumb2 parsing and encoding for CMN and CMP.
...
llvm-svn: 139188
2011-09-06 21:44:58 +00:00
Jim Grosbach
45bc30cc7e
Thumb2 parsing and encoding for CLZ.
...
llvm-svn: 139177
2011-09-06 20:44:17 +00:00
Jim Grosbach
b5dcc965a7
Thumb2 parsing and encoding for CLREX.
...
llvm-svn: 139172
2011-09-06 20:27:04 +00:00
Owen Anderson
23820ebb17
Port more encoding tests over to Thumb2 decoding tests.
...
llvm-svn: 139171
2011-09-06 20:26:34 +00:00
Jim Grosbach
3399db069a
Thumb2 parsing and encoding for CDP/CDP2.
...
llvm-svn: 139168
2011-09-06 20:12:23 +00:00
Jim Grosbach
68afe301fc
Thumb2 parsing and encoding for CBZ/CBNZ.
...
llvm-svn: 139054
2011-09-02 23:46:10 +00:00
Jim Grosbach
fb5e64e731
Thumb2 parsing and encoding for BXJ.
...
llvm-svn: 139053
2011-09-02 23:43:09 +00:00
Jim Grosbach
2ea035b027
Thumb2 parsing and encoding for BIC.
...
llvm-svn: 139052
2011-09-02 23:37:54 +00:00
Jim Grosbach
588f94c09b
Thumb2 parsing and encoding for BFI.
...
llvm-svn: 139051
2011-09-02 23:28:46 +00:00
Jim Grosbach
7a45cb2b33
Thumb2 parsing and encoding for BFC.
...
llvm-svn: 139050
2011-09-02 23:25:46 +00:00
Jim Grosbach
44483a9ba5
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
Jim Grosbach
ba4ceeaae6
Thumb2 parsing and encoding for ASR.
...
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
Kevin Enderby
90a1526592
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
Jim Grosbach
cbf37eebff
Thumb2 parsing and encoding for AND (register).
...
llvm-svn: 139021
2011-09-02 18:41:35 +00:00
Jim Grosbach
dd0421034a
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
Kevin Enderby
edfcba2f3c
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
...
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
Jim Grosbach
32cf633f1c
Tests for Thumb2 AND (immediate) instruction.
...
llvm-svn: 139013
2011-09-02 17:44:27 +00:00
Jim Grosbach
5b43c7fe81
Add FIXME. Thumb2 ADR encoding choice is non-trivial.
...
llvm-svn: 139008
2011-09-02 17:21:59 +00:00
Craig Topper
316c7bfe37
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
...
llvm-svn: 138997
2011-09-02 04:17:54 +00:00
Jim Grosbach
36ea6726dd
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
Owen Anderson
d8157fabfb
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
Jim Grosbach
2b04342a91
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
Owen Anderson
4024b91dbe
Fix encoding for tBcc with immediate offset operand.
...
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
Jim Grosbach
506f8078a8
Run the Thumb1 parser tests in Thumb2 mode, as well.
...
Thumb2 is a superset of Thumb1, so all of the encodings should still work.
llvm-svn: 138883
2011-08-31 19:50:28 +00:00
Jim Grosbach
98ba1f40ee
Thumb NOP encoding varies depending on ARCH revision.
...
llvm-svn: 138876
2011-08-31 18:35:46 +00:00
Owen Anderson
f30633abbf
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
...
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
Jim Grosbach
a2f9012605
Thumb2 parsing and encoding for ADC(register).
...
Also add instruction aliases for non-.w versions of SBC since they're the
same.
llvm-svn: 138871
2011-08-31 18:23:08 +00:00
Jim Grosbach
a4c1e9d88a
Tweak Thumb1 ADD encoding selection a bit.
...
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
llvm-svn: 138862
2011-08-31 17:07:33 +00:00
Owen Anderson
adac5b2109
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
Owen Anderson
a59d489162
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
...
llvm-svn: 138837
2011-08-30 22:15:17 +00:00
Owen Anderson
9465c7fee0
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
...
llvm-svn: 138835
2011-08-30 22:10:03 +00:00
Owen Anderson
309c4b7ef6
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
...
llvm-svn: 138834
2011-08-30 22:03:20 +00:00
Owen Anderson
9d3407e7c2
Port Thumb2 assembler tests over to disassembler tests.
...
llvm-svn: 138822
2011-08-30 20:03:11 +00:00
Craig Topper
5556444bf7
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
...
llvm-svn: 138795
2011-08-30 07:09:35 +00:00
Owen Anderson
4bd28c69c4
Add missing encoding information for some of the GPR<->FP register moves.
...
llvm-svn: 138780
2011-08-29 23:15:25 +00:00
Jim Grosbach
d71237315a
Remove redundant tests from XFAIL'ed test file.
...
llvm-svn: 138779
2011-08-29 23:04:04 +00:00
Jim Grosbach
00dc3313fc
Thumb2 assembly parsing and encoding support for ADC(immediate).
...
llvm-svn: 138778
2011-08-29 23:01:38 +00:00
Jim Grosbach
3bd8967df7
Remove test file. Superceded by other more exhaustive tests.
...
llvm-svn: 138777
2011-08-29 23:00:19 +00:00
Jim Grosbach
a1aa6a2e8b
Thumb2 parsing and encoding for IT blocks.
...
llvm-svn: 138773
2011-08-29 22:24:09 +00:00
Kevin Enderby
f1aef98ad2
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
...
llvm-svn: 138771
2011-08-29 22:06:28 +00:00
Owen Anderson
e14d6edccc
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
...
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
Owen Anderson
8719e2c1c3
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
Owen Anderson
fd21da3506
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
Owen Anderson
9b85a034c9
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
Owen Anderson
af51fd9868
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
Owen Anderson
86b11d01eb
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
Owen Anderson
485eda7687
Add a testcase for r138625.
...
llvm-svn: 138626
2011-08-26 06:45:08 +00:00
Craig Topper
b20cee1e19
Fix disassembling of VCVTSD2SI
...
llvm-svn: 138623
2011-08-26 04:49:29 +00:00
Owen Anderson
d387b48b0b
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
Craig Topper
5af7ba783d
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
...
llvm-svn: 138552
2011-08-25 07:42:00 +00:00
Craig Topper
06ed6cb856
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
...
llvm-svn: 138551
2011-08-25 06:57:46 +00:00
Evan Cheng
7bfc442b2d
Some autoconf tests use module level inline asm to test compiler's handling of
...
.cfi_startproc. e.g. libffi:
$ cat confopt.c
asm (".cfi_startproc\n\t.cfi_endproc");
int main () { return 0; }
Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.
rdar://10017184
llvm-svn: 138504
2011-08-24 22:31:37 +00:00
Jim Grosbach
aae1749f65
Update tests for 138501.
...
llvm-svn: 138502
2011-08-24 22:30:18 +00:00
Jim Grosbach
effaf1e15d
Thumb parsing and encoding for SUB (SP minu immediate).
...
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
Jim Grosbach
b2b155a93f
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
Owen Anderson
6325690c08
Port over more encoding tests to decoding tests.
...
llvm-svn: 138441
2011-08-24 17:08:34 +00:00
Jim Grosbach
f5d628146a
Thumb parsing and encoding for WFE, WFI and YIELD.
...
llvm-svn: 138364
2011-08-23 20:02:30 +00:00
Jim Grosbach
9f0be95d20
Thumb parsing and encoding for UXTB and UXTH.
...
llvm-svn: 138363
2011-08-23 19:59:32 +00:00
Jim Grosbach
87c7a2b16b
Thumb parsing and encoding for TST.
...
llvm-svn: 138362
2011-08-23 19:53:17 +00:00
Jim Grosbach
7ceb45dd61
Thumb parsing and encoding for SXTB and SXTH.
...
llvm-svn: 138361
2011-08-23 19:51:42 +00:00
Jim Grosbach
1f5b8e9044
Thumb parsing and encoding for SVC.
...
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
Jim Grosbach
d343e1a13f
Thumb parsing and encoding for SUB.
...
llvm-svn: 138359
2011-08-23 19:45:45 +00:00
Jim Grosbach
9795206370
Thumb parsing and encoding for STRH.
...
llvm-svn: 138352
2011-08-23 18:56:20 +00:00
Jim Grosbach
d507a9c6b9
Thumb parsing and encoding for STRB.
...
llvm-svn: 138349
2011-08-23 18:43:06 +00:00
Jim Grosbach
f9bc99b518
Thumb parsing and encoding for tSTRspi.
...
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
Jim Grosbach
7ece5d431c
Thumb parsing and encoding for STR.
...
Not including tSTRspi.
llvm-svn: 138347
2011-08-23 18:33:38 +00:00
Jim Grosbach
3b20e779cd
Thumb parsing and encoding for STM.
...
llvm-svn: 138345
2011-08-23 18:15:37 +00:00
Owen Anderson
3de2d7656d
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
Owen Anderson
9d5074746f
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
...
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
Owen Anderson
b97912374e
Port more assemble tests over to disassembly tests.
...
llvm-svn: 138336
2011-08-23 17:26:35 +00:00
Jim Grosbach
455795fb04
Thumb parsing and encoding for SETEND.
...
llvm-svn: 138312
2011-08-22 23:58:02 +00:00
Jim Grosbach
d299db0857
Thumb parsing and encoding for SBC.
...
llvm-svn: 138311
2011-08-22 23:55:58 +00:00
Jim Grosbach
5ae40d73a6
Thumb parsing and encoding for RSB.
...
llvm-svn: 138308
2011-08-22 23:47:13 +00:00
Jim Grosbach
9aa40e0f7c
Thumb parsing and encoding for ROR.
...
llvm-svn: 138304
2011-08-22 23:40:51 +00:00
Jim Grosbach
c4109eef36
Thumb parsing and encoding for REV/REV16/REVSH.
...
llvm-svn: 138303
2011-08-22 23:39:25 +00:00
Owen Anderson
d5b7d73696
t2SMLAD is a four-register instruction, not a three-register one.
...
llvm-svn: 138301
2011-08-22 23:31:45 +00:00
Owen Anderson
c395a07c42
Correct operand naming of t2USAT16 to allow proper decoding.
...
llvm-svn: 138300
2011-08-22 23:27:47 +00:00
Owen Anderson
9e750147fb
Match operand naming to allow correct decoding of t2LDRSH_POST.
...
llvm-svn: 138298
2011-08-22 23:22:05 +00:00
Jim Grosbach
54234257fa
Improve error checking for tPUSH and tPOP register lists.
...
llvm-svn: 138295
2011-08-22 23:17:34 +00:00
Jim Grosbach
3ebeefcb5a
Tidy up. Trailing whitespace.
...
llvm-svn: 138293
2011-08-22 23:13:54 +00:00
Owen Anderson
b400952853
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
...
llvm-svn: 138292
2011-08-22 23:10:16 +00:00
Jim Grosbach
1f5445e9d3
Thumb parsing and encoding for PUSH.
...
llvm-svn: 138290
2011-08-22 23:05:11 +00:00
Jim Grosbach
04e6944000
Fix think-o.
...
llvm-svn: 138288
2011-08-22 23:04:26 +00:00
Jim Grosbach
ec3958e68e
Thumb assemmbly parsing diagnostic improvements for LDM.
...
llvm-svn: 138287
2011-08-22 23:01:07 +00:00
Jim Grosbach
059b0d9a14
Thumb assembly parsing and encoding for POP.
...
llvm-svn: 138286
2011-08-22 23:00:19 +00:00
Owen Anderson
a2231fad2e
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
...
llvm-svn: 138273
2011-08-22 21:34:00 +00:00
Owen Anderson
39d3f234f7
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
...
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
Owen Anderson
926f360e53
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
...
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
Owen Anderson
816f5524f8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
...
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
Owen Anderson
e70aed2df9
Port another swathe of Thumb1 encoding tests over to decoding tests.
...
llvm-svn: 138250
2011-08-22 18:05:49 +00:00
Owen Anderson
59178665b5
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
Jim Grosbach
3a232fc83e
Thumb assembly parsing and encoding for ORR.
...
llvm-svn: 138245
2011-08-22 17:41:44 +00:00
Jim Grosbach
a6e1ed8f2b
Fix AsmParser binary precedence for shift operators.
...
rdar://9976729
llvm-svn: 138208
2011-08-20 16:24:13 +00:00
Jim Grosbach
eb5b09fa5a
Tidy up. Whitespace.
...
llvm-svn: 138207
2011-08-20 16:10:09 +00:00
Jim Grosbach
be94868d66
Thumb parsing and encoding support for NOP.
...
The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
Jim Grosbach
326e78be7a
Thumb assembly parsing and encoding for NEG.
...
llvm-svn: 138131
2011-08-19 22:51:03 +00:00
Jim Grosbach
a97661cac4
Be more lenient on tied operand matching for MUL.
...
llvm-svn: 138124
2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes
9979e44f1b
Re-write part of VEX encoding logic, to be more easy to read! Also fix
...
a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
Jim Grosbach
c1186a4afb
Thumb assembly parsing and encoding for MVN.
...
llvm-svn: 138109
2011-08-19 22:09:23 +00:00
Jim Grosbach
8e2d4a63dc
Thumb assembly parsing and encoding for MUL.
...
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
Jim Grosbach
71ef1b39b1
Add FIXME.
...
llvm-svn: 138077
2011-08-19 20:48:54 +00:00
Jim Grosbach
cf35d78b16
Thumb assembly parsing and encoding for MOV.
...
llvm-svn: 138076
2011-08-19 20:46:54 +00:00
Jim Grosbach
a32aa55506
Thumb assembly parsing and encoding for LSR.
...
llvm-svn: 138065
2011-08-19 19:34:22 +00:00
Jim Grosbach
ea8b606660
Thumb assembly parsing and encoding for LSL(register).
...
llvm-svn: 138064
2011-08-19 19:30:58 +00:00
Jim Grosbach
7d707b4fb1
Thumb assembly parsing and encoding for LSL(immediate).
...
llvm-svn: 138063
2011-08-19 19:29:25 +00:00
Jim Grosbach
9174714826
Thumb assembly parsing and encoding for LDRSB and LDRSH.
...
llvm-svn: 138061
2011-08-19 19:17:58 +00:00
Jim Grosbach
27001ee5fd
Thumb assembly parsing and encoding for LDRH.
...
llvm-svn: 138060
2011-08-19 18:55:51 +00:00
Jim Grosbach
36fb75a109
Thumb assembly parsing and encoding for LDRB.
...
llvm-svn: 138059
2011-08-19 18:49:59 +00:00
Jim Grosbach
5a05787b9a
Thumb assembly parsing and encoding for LDR(register).
...
llvm-svn: 138056
2011-08-19 18:35:06 +00:00
Jim Grosbach
6d9a3e68bb
Thumb assembly parsing and encoding for LDR(literal).
...
llvm-svn: 138052
2011-08-19 18:20:48 +00:00
Jim Grosbach
d429ab26cb
Thumb assembly parsing and encoding for LDR(immediate) form T2.
...
llvm-svn: 138050
2011-08-19 18:13:48 +00:00
Jim Grosbach
35b968afdc
Thumb assembly parsing and encoding for LDR(immediate) form T1.
...
llvm-svn: 138047
2011-08-19 17:55:24 +00:00
Craig Topper
f68d77215d
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
...
llvm-svn: 138034
2011-08-19 05:28:50 +00:00
Bruno Cardoso Lopes
306110c29a
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
...
implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
Owen Anderson
421e30086e
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
...
Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
Owen Anderson
d113a59074
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
Owen Anderson
d121f0e77c
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
...
Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
Jim Grosbach
7ecefeb594
Thumb assembly parsing and encoding for LDM instruction.
...
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
Owen Anderson
b4bc7704ec
More Thumb1 decoding tests.
...
llvm-svn: 137974
2011-08-18 20:05:06 +00:00
Jim Grosbach
e5d4c35c23
Thumb assembly parsing and encoding for EOR.
...
llvm-svn: 137964
2011-08-18 18:10:38 +00:00
Jim Grosbach
d14d4c0aa8
Thumb assembly parsing and encoding for CMP.
...
llvm-svn: 137963
2011-08-18 18:08:29 +00:00
James Molloy
5d9ba3b5aa
Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.
...
llvm-svn: 137960
2011-08-18 18:03:02 +00:00
Jim Grosbach
a76d04e29e
Thumb assembly parsing and encoding test for CMN.
...
llvm-svn: 137957
2011-08-18 17:55:03 +00:00
Owen Anderson
366ac95879
Port over BL/BLX to disassembly tests.
...
llvm-svn: 137954
2011-08-18 17:43:52 +00:00
Jim Grosbach
54d054dba4
ARM assembly parsing and encoding test for BX/BLX (register).
...
llvm-svn: 137949
2011-08-18 17:02:28 +00:00
Jim Grosbach
1a63bca66c
ARM assembly parsing and encoding test for BL/BLX (immediate).
...
llvm-svn: 137948
2011-08-18 17:00:09 +00:00
Owen Anderson
eb5c093d8d
Port new Thumb1 encoding tests over to decoding tests.
...
llvm-svn: 137902
2011-08-17 23:37:33 +00:00
Jim Grosbach
d4e9b9844d
ARM assembly parsing and encoding test for BKPT.
...
llvm-svn: 137898
2011-08-17 23:11:13 +00:00
Jim Grosbach
fefc732dd9
ARM assembly parsing and encoding test for BIC.
...
llvm-svn: 137895
2011-08-17 23:00:53 +00:00
Jim Grosbach
b0e8cd2bfa
Thumb assembly parsing and encoding for B.
...
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
Jim Grosbach
1b761bd2d5
Thumb assembly parsing and encoding for ASR.
...
llvm-svn: 137889
2011-08-17 22:49:09 +00:00
Jim Grosbach
0115c6f75b
Thumb assembly parsing and encoding for ADR.
...
llvm-svn: 137864
2011-08-17 20:37:40 +00:00
Jim Grosbach
20329b9f8e
Add a couple of FIXMEs.
...
llvm-svn: 137861
2011-08-17 20:35:57 +00:00
Owen Anderson
4c26beae4c
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.
...
llvm-svn: 137840
2011-08-17 18:21:36 +00:00
Jim Grosbach
39af673350
Thumb assembly parsing and encoding for ADC(register) instruction.
...
llvm-svn: 137833
2011-08-17 17:55:28 +00:00
Jim Grosbach
c93201cb25
Add missing '@' delimiter.
...
llvm-svn: 137832
2011-08-17 17:46:01 +00:00
Owen Anderson
3146968039
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
...
Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
Jim Grosbach
ae9f7f938f
Thumb ADD(immediate) parsing support.
...
llvm-svn: 137788
2011-08-16 23:57:34 +00:00
Jim Grosbach
7a5c6948ca
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
...
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
Jim Grosbach
850f937ecc
Thumb assembly parsing and encoding for ADD(register) instruction.
...
llvm-svn: 137759
2011-08-16 21:34:08 +00:00
Jim Grosbach
192f298228
Add testcase for r137746.
...
llvm-svn: 137754
2011-08-16 21:11:21 +00:00
Jim Grosbach
06f3a3b427
Tidy up formatting.
...
llvm-svn: 137747
2011-08-16 20:55:41 +00:00
Jim Grosbach
8d67a0e07c
ARM thumb assembly parsing for arithmetic flag setting instructions.
...
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
Jim Grosbach
90387c44f4
ARM .align NOP padding uses different encoding pre-ARMv6.
...
Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
Owen Anderson
6549866051
Add a test file for Thumb2 NEON.
...
llvm-svn: 137687
2011-08-15 23:42:20 +00:00
Bruno Cardoso Lopes
1e817d1451
Reorder declarations of vmovmskp* and also put the necessary AVX
...
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
llvm-svn: 137684
2011-08-15 23:36:45 +00:00
Owen Anderson
54ded8463c
Add some more comprehensive VFP decoding tests.
...
llvm-svn: 137657
2011-08-15 21:29:01 +00:00
Owen Anderson
42946000dd
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
...
Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
Owen Anderson
43b6d1c14e
Add a test for Thumb1 LDRSH decoding.
...
llvm-svn: 137645
2011-08-15 20:15:43 +00:00
Owen Anderson
aed8eff14b
Add testcase for STRH. Patch by James Molloy.
...
llvm-svn: 137644
2011-08-15 20:12:03 +00:00
Owen Anderson
4854258d9c
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
Owen Anderson
cd94fca93d
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
...
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
Owen Anderson
894585de33
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
Owen Anderson
2ea55a0881
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
Owen Anderson
9d85cab3d5
Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions.
...
llvm-svn: 137495
2011-08-12 19:42:45 +00:00
Jim Grosbach
d154fc4c8f
Tidy up formatting.
...
llvm-svn: 137471
2011-08-12 17:43:31 +00:00
Jim Grosbach
1cfe8c24d5
Tidy up formatting.
...
llvm-svn: 137464
2011-08-12 17:01:02 +00:00
Benjamin Kramer
e404b3e2d1
MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does.
...
llvm-svn: 137414
2011-08-12 01:51:29 +00:00
Jim Grosbach
ade39d38e1
Clean up formatting a bit.
...
llvm-svn: 137393
2011-08-11 23:57:17 +00:00
Jim Grosbach
d17df06881
ARM vector compare to zero instruction assembly parsing support.
...
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
Jim Grosbach
41ef68eb17
Fix tests per now-correct encoding as of r137371.
...
llvm-svn: 137376
2011-08-11 22:31:48 +00:00
Jim Grosbach
edefbb31c3
ARM STRT assembly parsing and encoding.
...
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Jim Grosbach
ed8a320007
ARM load shifted register pre-index fix shift value asm parser encoding.
...
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
Jim Grosbach
609316e481
ARM STRHT assembly parsing and encoding.
...
llvm-svn: 137358
2011-08-11 21:39:41 +00:00
Jim Grosbach
5c12d41c95
ARM STRH assembly parsing and encoding.
...
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
Owen Anderson
4618d77bcd
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
Owen Anderson
1ec4fcb5d3
Improve operand validation for Thumb2 addressing modes.
...
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
Jim Grosbach
81b2835f83
ARM STRD assembly parsing and encoding.
...
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
Owen Anderson
73e7d34732
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach
bfc85134c2
ARM STRBT assembly parsing and encoding.
...
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Jim Grosbach
87f0f921b5
Add FIXME.
...
llvm-svn: 137336
2011-08-11 19:43:42 +00:00
Jim Grosbach
a6572a1201
ARM STRB assembly parsing and encoding tests.
...
llvm-svn: 137335
2011-08-11 19:42:58 +00:00
Jim Grosbach
9673dc9e01
Fix a copy/paste error so that LDRB(register) actually gets tested.
...
llvm-svn: 137333
2011-08-11 19:34:23 +00:00
Jim Grosbach
986a3eb0b2
ARM STR(register) assembly parsing and encoding tests.
...
llvm-svn: 137332
2011-08-11 19:26:17 +00:00
Jim Grosbach
e6bd3a1ab8
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Owen Anderson
63ccfdccd1
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Owen Anderson
decc5fcced
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson
707fcaca0e
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
...
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Owen Anderson
8d6b9f063f
Improve error checking in the new ARM disassembler. Patch by James Molloy.
...
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach
9717a9c0d3
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Jim Grosbach
abaaf4513f
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Jim Grosbach
eb96dd6c99
ARM tests for LDRSHT assembly parsing and encoding.
...
llvm-svn: 137274
2011-08-10 23:18:30 +00:00
Jim Grosbach
e2cc6866d1
ARM tests for LDRSH assembly parsing and encoding.
...
llvm-svn: 137272
2011-08-10 23:12:25 +00:00
Jim Grosbach
f65a625648
ARM tests for LDRSBT assembly parsing and encoding.
...
llvm-svn: 137271
2011-08-10 23:08:56 +00:00
Jim Grosbach
e22ad37645
ARM tests for LDRSB assembly parsing and encoding.
...
llvm-svn: 137270
2011-08-10 23:06:44 +00:00
Jim Grosbach
f291232aa1
Add FIXME.
...
llvm-svn: 137265
2011-08-10 22:56:43 +00:00
Jim Grosbach
5c5f1c8305
ARM tests for LDRHT assembly parsing and encoding.
...
llvm-svn: 137263
2011-08-10 22:55:38 +00:00
Jim Grosbach
7c1596bf26
ARM tests for LDRH(register) assembly parsing and encoding.
...
llvm-svn: 137261
2011-08-10 22:45:42 +00:00
Jim Grosbach
e0ccd6b34e
ARM LDRH(immediate) assembly parsing and encoding support.
...
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach
e0c10a6d0c
Add FIXME
...
llvm-svn: 137258
2011-08-10 22:20:38 +00:00
Jim Grosbach
4ad2dc8bb2
ARM LDRD(register) assembly parsing and encoding.
...
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Jim Grosbach
bbef0044c8
ARM LDRD(immediate) assembly parsing and encoding support.
...
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Owen Anderson
0fde7a84ee
Add initial support for decoding NEON instructions in Thumb2 mode.
...
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson
87b5ce880a
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
...
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Owen Anderson
b717d71aa1
Tighten operand checking of register-shifted-register operands.
...
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson
62faf296dd
Tighten operand checking on memory barrier instructions.
...
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson
869ce85500
Tighten operand checking on CPS instructions.
...
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson
8ad37f68a2
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
...
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Benjamin Kramer
ca48bdfd5b
ARM Disassembler: sign extend branch immediates.
...
Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
Owen Anderson
2aa4c7e391
Tighten Thumb1 branch predicate decoding.
...
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
Owen Anderson
ffe1c55752
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
...
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Jim Grosbach
d6da18cf19
ARM parsing and encoding for LDRBT instruction.
...
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
llvm-svn: 137074
2011-08-08 23:28:47 +00:00
Jim Grosbach
dce26073db
ARM parsing and encoding for LDRB instruction.
...
llvm-svn: 137071
2011-08-08 22:37:06 +00:00
Jim Grosbach
1dbe50798e
Add FIXME.
...
llvm-svn: 137070
2011-08-08 22:11:33 +00:00
Jim Grosbach
00c4316907
ARM load instruction shifted register index operands.
...
Parsing and encoding for shifted index operands for load instructions.
llvm-svn: 136986
2011-08-05 22:03:36 +00:00
Jim Grosbach
40a7e379c4
ARM indexed load assembly parsing and encoding.
...
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
llvm-svn: 136982
2011-08-05 21:28:30 +00:00
Jim Grosbach
861430e0bb
Add ARM LDR parsing tests.
...
llvm-svn: 136977
2011-08-05 20:33:39 +00:00
Rafael Espindola
b16f4e78a4
Fix the bitwidth of the remaining fields.
...
llvm-svn: 136884
2011-08-04 17:00:11 +00:00
Rafael Espindola
2da6e6a1d8
print st_shndx with the correct number of bits.
...
llvm-svn: 136880
2011-08-04 15:50:13 +00:00
Rafael Espindola
c1a076eeb1
print st_other with the correct number of bits.
...
llvm-svn: 136877
2011-08-04 15:38:19 +00:00
Rafael Espindola
368850841d
print st_type with the correct number of bits.
...
llvm-svn: 136875
2011-08-04 15:24:00 +00:00
Rafael Espindola
e08bb3d50f
Print st_bind with the correct number of bits.
...
llvm-svn: 136874
2011-08-04 15:10:35 +00:00
Rafael Espindola
865ab6cb05
Print r_sym with the correct number of bits.
...
llvm-svn: 136873
2011-08-04 14:48:27 +00:00
Rafael Espindola
f65dd30907
Print r_type with the correct number of bits.
...
llvm-svn: 136872
2011-08-04 14:39:30 +00:00
Rafael Espindola
c5a30ed713
Another counter goes decimal.
...
llvm-svn: 136871
2011-08-04 14:27:46 +00:00
Rafael Espindola
edfafcbfb0
Change anther counter to decimal.
...
llvm-svn: 136870
2011-08-04 14:01:03 +00:00
Rafael Espindola
3e8393e6f7
Don't print a counter in hex.
...
llvm-svn: 136869
2011-08-04 13:39:15 +00:00
Rafael Espindola
a910136fe2
Print all the bits in the addend.
...
llvm-svn: 136867
2011-08-04 13:00:24 +00:00
Jason W Kim
18ca6290c9
Fix http://llvm.org/bugs/show_bug.cgi?id=10568
...
Move the reloc size assert into AsmBackend - where it is more apropos.
llvm-svn: 136855
2011-08-04 00:38:45 +00:00
Jim Grosbach
767e9d16e6
ARM refactoring assembly parsing of memory address operands.
...
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Jim Grosbach
9f0533c5d2
ARM SRS instruction parsing, diassembly and encoding support.
...
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach
1b69dbc796
ARM assembly parsing and encoding for RFE instruction.
...
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Jim Grosbach
43e281bec4
ARM update tests for CPS instruction.
...
llvm-svn: 136472
2011-07-29 17:39:27 +00:00
Jim Grosbach
666e97a0ce
CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
...
llvm-svn: 136408
2011-07-28 21:59:38 +00:00
Jim Grosbach
01d878a4ea
ARM assembly parsing and encoding for BLX (immediate).
...
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
llvm-svn: 136406
2011-07-28 21:57:55 +00:00
Jim Grosbach
adeee03ea2
Remove obsolete FIXME reference in comment.
...
llvm-svn: 136400
2011-07-28 21:37:05 +00:00
Jim Grosbach
3bbf68ce6e
ARM assembly parsing and encoding for BFC and BFI.
...
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
llvm-svn: 136399
2011-07-28 21:34:26 +00:00
Jim Grosbach
2378f8a15e
ARM parsing and encoding for ADR.
...
The label does not have a '#' prefix. Add parsing and encoding tests.
llvm-svn: 136360
2011-07-28 16:33:54 +00:00
Jim Grosbach
68241cddd8
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
...
llvm-svn: 136358
2011-07-28 16:00:41 +00:00
Jim Grosbach
992112a797
ARM parsing and encoding tests.
...
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.
llvm-svn: 136312
2011-07-28 00:37:03 +00:00
Evan Cheng
04762a3cf5
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
...
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Jim Grosbach
37586957ee
ARM assembly parsing and encoding for USUB16 and USUB8.
...
llvm-svn: 136289
2011-07-27 23:10:05 +00:00
Jim Grosbach
3e48c1f676
ARM assembly parsing and encoding for USAX.
...
llvm-svn: 136288
2011-07-27 23:07:00 +00:00
Kevin Enderby
9adbbfffd0
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
...
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
llvm-svn: 136287
2011-07-27 23:01:50 +00:00
Jim Grosbach
b0bde240c1
Clean up tabs.
...
llvm-svn: 136286
2011-07-27 22:35:06 +00:00
Jim Grosbach
094803b4d0
ARM assembly parsing and encoding support for USAT and USAT16.
...
Use range checked immediate operands for instructions. Add tests.
llvm-svn: 136285
2011-07-27 22:34:17 +00:00
Jim Grosbach
e8619cb279
ARM assembly parsing and encoding tests for USAD8 and USADA8.
...
llvm-svn: 136284
2011-07-27 22:23:02 +00:00
Jim Grosbach
04ab1fa0bc
ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
...
llvm-svn: 136282
2011-07-27 22:13:08 +00:00
Jim Grosbach
2c4ea41358
Fix comment copy/paste-o.
...
llvm-svn: 136281
2011-07-27 22:11:41 +00:00
Jim Grosbach
a91fcf98c9
ARM assembly parsing and encoding tests for UQASX and UQSAX.
...
llvm-svn: 136280
2011-07-27 22:09:30 +00:00
Jim Grosbach
a85f517680
ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
...
llvm-svn: 136279
2011-07-27 22:08:14 +00:00
Jim Grosbach
df8040c528
ARM assembly parsing and encoding for UMULL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136277
2011-07-27 22:01:42 +00:00
Jim Grosbach
dd55e1de02
ARM assembly parsing and encoding for UMLAL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136274
2011-07-27 21:58:11 +00:00
Jim Grosbach
f48e465aa5
ARM assembly parsing and encoding tests for UMAAL.
...
llvm-svn: 136272
2011-07-27 21:53:42 +00:00
Jim Grosbach
91f7d83f9c
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
...
llvm-svn: 136267
2011-07-27 21:21:59 +00:00
Jim Grosbach
6f34be1f69
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
...
llvm-svn: 136266
2011-07-27 21:20:45 +00:00
Jim Grosbach
c5cd3228c4
ARM parsing and encoding of SBFX and UBFX.
...
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Jim Grosbach
8393f12ec5
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
...
llvm-svn: 136261
2011-07-27 20:43:44 +00:00
Jim Grosbach
1f818d0f25
ARM assembly parsing and encoding tests for TST instruction.
...
llvm-svn: 136260
2011-07-27 20:38:58 +00:00
Jim Grosbach
e74be6ad39
ARM assembly parsing and encoding tests for TEQ instruction.
...
llvm-svn: 136259
2011-07-27 20:37:36 +00:00
Owen Anderson
d2cd33b911
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
...
llvm-svn: 136255
2011-07-27 20:29:48 +00:00
Jim Grosbach
624acaffd7
ARM assembly parsing and encoding for extend instructions.
...
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
llvm-svn: 136252
2011-07-27 20:15:40 +00:00
Jim Grosbach
8e642b2b18
ARM diagnostics for ldrexd/stredx out of order paired register operands.
...
llvm-svn: 136110
2011-07-26 18:25:39 +00:00
Jim Grosbach
7b56b1cf0e
ARM parsing and encoding tests for load/store exclusive instructions.
...
llvm-svn: 136105
2011-07-26 18:07:21 +00:00
Jim Grosbach
6fbee17fef
ARM assembly parsing and encoding for SWP[B] instructions.
...
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
Jim Grosbach
d3152480f2
ARM parsing and encoding for SVC instruction.
...
llvm-svn: 136090
2011-07-26 16:24:27 +00:00
Jim Grosbach
422ac2fc64
ARM assembly parsing and encoding tests for SUB instruction.
...
llvm-svn: 136089
2011-07-26 15:44:05 +00:00
Jim Grosbach
3efad526c2
Update ARM STM tests. Fix check: prefix for diagnostic tests.
...
llvm-svn: 136088
2011-07-26 15:41:22 +00:00
Jim Grosbach
41a5cd3fa2
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
...
llvm-svn: 136013
2011-07-25 23:32:14 +00:00
Jim Grosbach
ef3d573e31
ARM assembly parsing and encoding for SSAT16 instruction.
...
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
Jim Grosbach
c1fe042da0
ARM assembly parsing and encoding for SSAT instruction.
...
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0 ').
Add tests for diagnostics and proper encoding.
llvm-svn: 135990
2011-07-25 22:20:28 +00:00
Jim Grosbach
2f728674cf
Move some ELF directives into ELF asm parser.
...
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.
rdar://9827089
llvm-svn: 135921
2011-07-25 17:55:35 +00:00
Jim Grosbach
0bfa6a6db7
Add FIXME
...
llvm-svn: 135819
2011-07-22 22:15:38 +00:00
Jim Grosbach
daf04c88c2
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
...
llvm-svn: 135818
2011-07-22 22:13:00 +00:00
Jim Grosbach
a7a6658647
ARM assembly parsing and encoding updates.
...
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
llvm-svn: 135817
2011-07-22 22:06:05 +00:00
Jim Grosbach
1e724e3217
ARM assembly parsing and encoding tests.
...
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
llvm-svn: 135810
2011-07-22 21:34:56 +00:00
Jim Grosbach
f7780d14ce
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
...
llvm-svn: 135800
2011-07-22 20:51:24 +00:00
Jim Grosbach
7ee1e3dc6c
ARM assembly parsing and encoding tests.
...
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
llvm-svn: 135798
2011-07-22 20:30:40 +00:00
Jim Grosbach
9ffa43becc
ARM assembly parsing and encoding of SMLAL instruction.
...
Fix parsing of carry-setting variant SMLALS and add tests.
llvm-svn: 135797
2011-07-22 20:18:21 +00:00
Jim Grosbach
4f1031662f
ARM encoding and assembly parsing of SMLAD{X} instructions.
...
Fix encoding of destination register. Add tests.
llvm-svn: 135796
2011-07-22 20:11:20 +00:00
Jim Grosbach
5b69318e51
ARM testcases for assembly parsing and encoding SMLA* instructions.
...
llvm-svn: 135795
2011-07-22 20:01:34 +00:00
Jim Grosbach
ebd66f344c
ARM assembly parsing and encoding for SMC instruction.
...
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
Jim Grosbach
c3612faf56
ARM encoding and assembly parsing tests.
...
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
llvm-svn: 135780
2011-07-22 18:04:48 +00:00
Jim Grosbach
0fe45ec0ed
ARM assembly parsing and encoding for SETEND instruction.
...
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
llvm-svn: 135776
2011-07-22 17:44:50 +00:00
Jim Grosbach
2bb9f8ae56
ARM assembly parsing and encoding tests for SEL instruction.
...
llvm-svn: 135772
2011-07-22 16:59:33 +00:00
Jim Grosbach
54b0cbc6ae
ARM parsing and encoding tests for SBC instruction.
...
llvm-svn: 135718
2011-07-21 23:03:59 +00:00
Jim Grosbach
901aeb1ffa
ARM testcases for SADD/SASX parsing and encoding.
...
llvm-svn: 135715
2011-07-21 23:00:49 +00:00
Jim Grosbach
8d031eeb23
ARM assembly parsing support for RSC instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135713
2011-07-21 22:56:30 +00:00
Jim Grosbach
e96857fd4f
ARM assembly parsing support for RSB instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135712
2011-07-21 22:37:43 +00:00
Jim Grosbach
6947bcc2b0
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
...
llvm-svn: 135710
2011-07-21 22:29:23 +00:00
Jim Grosbach
95ce5e9b8e
ARM parsing and encodings tests for saturating arithmetic insns.
...
llvm-svn: 135709
2011-07-21 22:18:28 +00:00
Jim Grosbach
a860ba338f
ARM assembly parsing POP/PUSH mnemonics.
...
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
llvm-svn: 135702
2011-07-21 19:57:11 +00:00
Jim Grosbach
ef5c63cafe
Add tests for ARM PKH assembly parsing.
...
llvm-svn: 135696
2011-07-21 19:02:03 +00:00
Eli Friedman
7776a468cf
Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.
...
llvm-svn: 135607
2011-07-20 19:36:11 +00:00
Jim Grosbach
9c558ee8ce
Add parsing/encoding tests for ARM ORR instruction.
...
llvm-svn: 135602
2011-07-20 18:48:53 +00:00
Jim Grosbach
173559ac44
Consolidate ARM NOP encoding test.
...
llvm-svn: 135600
2011-07-20 18:39:38 +00:00
Jim Grosbach
a2e8523f81
ARM parsing and encoding tests for MVN
...
llvm-svn: 135599
2011-07-20 18:37:08 +00:00
Jim Grosbach
1514063b5f
ARM assembly parsing of MUL instruction.
...
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
llvm-svn: 135596
2011-07-20 18:20:31 +00:00
Jim Grosbach
e70c8eb49a
Tweak ARM assembly parsing and printing of MSR instruction.
...
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
llvm-svn: 135532
2011-07-19 22:45:10 +00:00
Jim Grosbach
720b8c6578
ARM assembly parsing of MRS instruction.
...
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
llvm-svn: 135527
2011-07-19 21:59:29 +00:00
Jim Grosbach
66af8b4a40
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
...
Add range checking to the immediate operands. Update tests accordingly.
llvm-svn: 135521
2011-07-19 20:35:35 +00:00
Jim Grosbach
40cce44255
Move mr[r]c[2] ARM tests and tidy up a bit.
...
llvm-svn: 135517
2011-07-19 20:28:56 +00:00
Jim Grosbach
69686aec2b
ARM testcases for MOVT.
...
llvm-svn: 135516
2011-07-19 20:23:25 +00:00
Jim Grosbach
9debba28ed
ARM assembly parsing for MOV (register).
...
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
llvm-svn: 135513
2011-07-19 20:10:31 +00:00
Jim Grosbach
294b83e3e2
ARM assembly parsing for MOV (immediate).
...
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
llvm-svn: 135500
2011-07-19 19:13:28 +00:00
Jim Grosbach
0789ef018d
Whitespace.
...
llvm-svn: 135499
2011-07-19 19:02:39 +00:00
Eli Friedman
f6cac8a620
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
...
llvm-svn: 135337
2011-07-16 02:41:28 +00:00
Eli Friedman
6bd9cfed88
PR10370: Make sure we know how to relax push correctly on x86-64.
...
llvm-svn: 135303
2011-07-15 21:28:39 +00:00
Owen Anderson
7a380bac06
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
...
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
Jim Grosbach
6122eb0fff
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
...
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
llvm-svn: 135203
2011-07-14 22:04:21 +00:00
Jim Grosbach
7656c6f97e
Add some testcases for ARM MLA/MLS instructions.
...
llvm-svn: 135196
2011-07-14 21:43:05 +00:00
Jim Grosbach
2ab898973a
ARM MCRR/MCRR2 immediate operand range checking.
...
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
Jim Grosbach
27ebbba831
ARM MCR/MCR2 assembly parsing operand constraints.
...
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
llvm-svn: 135189
2011-07-14 21:19:17 +00:00
Jim Grosbach
09b5985799
Enable some tests we now handle correctly.
...
llvm-svn: 135185
2011-07-14 21:02:23 +00:00
Jim Grosbach
aebb9cdf68
Update ARM Assembly of LDM/STM.
...
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
llvm-svn: 135168
2011-07-14 18:35:38 +00:00
Jim Grosbach
ebbd82a248
ARM ISB assembly parsing tests.
...
llvm-svn: 135158
2011-07-14 18:02:25 +00:00
Jim Grosbach
9bbc2007df
ARM ISB instruction assembly parsing.
...
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
llvm-svn: 135156
2011-07-14 18:00:31 +00:00
Jim Grosbach
76bd4e6f75
ARM tests for EOR instruction parsing and encoding.
...
llvm-svn: 135119
2011-07-14 00:22:21 +00:00
Jim Grosbach
fe9c954c0f
Remove duplicate tests.
...
llvm-svn: 135117
2011-07-14 00:19:19 +00:00
Jim Grosbach
4b63d59acb
ARM Assembler support for DSB instruction.
...
Add instalias for default 'sy' option. Add tests.
llvm-svn: 135116
2011-07-14 00:18:13 +00:00
Jim Grosbach
5a96cebd81
ARM Assembler support for DMB instruction.
...
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
llvm-svn: 135109
2011-07-13 23:40:38 +00:00
Jim Grosbach
c0ec4205e2
ARM Assembler support for DBG instruction.
...
Add range checking and testing for parsing and encoding of DBG instruction.
llvm-svn: 135102
2011-07-13 22:59:38 +00:00
Jim Grosbach
25a4b8922d
ARM parsing and encoding tests for CMN/CMP.
...
llvm-svn: 135098
2011-07-13 22:26:58 +00:00
Jim Grosbach
d5e74991f0
Shuffle ARM assembly tests a bit.
...
llvm-svn: 135095
2011-07-13 22:19:10 +00:00
Jim Grosbach
fd2ebb4552
Range checking for CDP[2] immediates.
...
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Jim Grosbach
d3b15141b8
Fix predicates for Thumb co-processor instructions.
...
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Jim Grosbach
c7e0941dac
Testcases for ARM assembly BX/BXJ instructions.
...
llvm-svn: 135078
2011-07-13 20:25:46 +00:00
Jim Grosbach
0313701671
Testcases for ARM assembly BLX/BL instructions.
...
llvm-svn: 135072
2011-07-13 20:11:04 +00:00
Jim Grosbach
0caa098513
Range checking for 16-bit immediates in ARM assembly.
...
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Jim Grosbach
9e021b5281
Add tests for ARM parsing of 'BKPT' instruction.
...
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach
ce9b6636b3
Fix copy-pasto.
...
llvm-svn: 135062
2011-07-13 19:16:30 +00:00
Jim Grosbach
9d1a4de9e6
Add tests for ARM parsing of 'BIC' instruction.
...
llvm-svn: 135061
2011-07-13 19:12:32 +00:00
Jim Grosbach
7aea4b177f
Add some FIXMEs.
...
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.
llvm-svn: 135060
2011-07-13 19:10:23 +00:00
Jim Grosbach
9b9604762e
Add tests for ARM parsing of 'AND' instruction.
...
llvm-svn: 135056
2011-07-13 18:55:14 +00:00
Jim Grosbach
5c366bfb36
Improve ARM assembly parsing diagnostics a bit.
...
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.
Add some tests for the diagnostics we do want.
llvm-svn: 135055
2011-07-13 18:49:30 +00:00
Jim Grosbach
a0a947a8ca
Add tests for ARM parsing of 'ADD' instruction
...
llvm-svn: 135053
2011-07-13 18:12:46 +00:00
Jim Grosbach
7dbb39dffa
Destination register operand is optional for ADC and SBC ARM.
...
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach
5db1296fcd
Flesh out ARM Parser support for shifted-register operands.
...
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach
295e53b228
Add check for predicate w/o S bit.
...
llvm-svn: 134987
2011-07-12 16:25:04 +00:00
Jim Grosbach
fae61bb435
Fix recognition of ARM 'adcs' mnemonic.
...
The 'CS' is not a predication suffix in this case.
llvm-svn: 134903
2011-07-11 17:09:57 +00:00
Jim Grosbach
93f2ebb5e7
Simplify printing of ARM shifted immediates.
...
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
llvm-svn: 134902
2011-07-11 16:48:36 +00:00
Evan Cheng
1346a63a0f
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
...
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Evan Cheng
71dc177796
Add support for ARM / Thumb mode switching with .code 16 and .code 32.
...
llvm-svn: 134760
2011-07-08 22:36:29 +00:00
Evan Cheng
952943f744
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
...
llvm-svn: 134590
2011-07-07 03:55:05 +00:00
Kevin Enderby
43cb64711d
Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501.
...
llvm-svn: 134511
2011-07-06 17:55:20 +00:00
Kevin Enderby
59ba10f2ac
Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
...
push with a small constant produces a 2-byte push.
llvm-svn: 134501
2011-07-06 17:23:46 +00:00
Eli Friedman
9765ae0015
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
...
llvm-svn: 134424
2011-07-05 18:21:20 +00:00
Joerg Sonnenberger
708b6e085d
Recognize the xstorerng alias for VIA PadLock's xstore instruction.
...
llvm-svn: 134126
2011-06-30 01:38:03 +00:00
Jim Grosbach
88387d64d6
Asm parser range checking on .<size> <value> directives.
...
For example, ".byte 256" would previously assert() when emitting an object
file. Now it generates a diagnostic that the literal value is out of range.
rdar://9686950
llvm-svn: 134069
2011-06-29 16:05:14 +00:00
Jim Grosbach
33470a73f0
ARM Thumb2 asm syntax optional destination operand for binary operators.
...
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff
rdar://9672867
llvm-svn: 133973
2011-06-28 00:19:13 +00:00
Jim Grosbach
190b9d7ec0
ARM Assembly support for Thumb mov-immediate.
...
Correctly parse the forms of the Thumb mov-immediate instruction:
1. 8-bit immediate 0-255.
2. 12-bit shifted-immediate.
The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.
llvm-svn: 133966
2011-06-27 23:54:06 +00:00
Jim Grosbach
7c950cf36c
ARM assembler support for ldmfd/stmfd mnemonics.
...
llvm-svn: 133936
2011-06-27 20:32:18 +00:00
Jim Grosbach
7157b0228f
ARM assembler support for vpush/vpop.
...
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.
rdar://9683231
llvm-svn: 133932
2011-06-27 20:00:07 +00:00
Jim Grosbach
210c7054ac
ARM Assembly syntax support for arithmetic implied dest operand.
...
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
sub r2, r2, #6
sub r2, #6
rdar://9682597
llvm-svn: 133925
2011-06-27 19:09:15 +00:00
Jim Grosbach
f8b05a7bbb
Move ARM-specific test to ARM directory.
...
Hopefully make the x86-target-only Windows bots happy.
llvm-svn: 133856
2011-06-25 01:53:17 +00:00
Jim Grosbach
c10ef9d30c
Testcase for r133818
...
llvm-svn: 133823
2011-06-24 20:59:01 +00:00
Eli Friedman
802029c494
Add support for movntil/movntiq mnemonics. Reported on llvmdev.
...
llvm-svn: 133759
2011-06-23 21:07:47 +00:00
Nick Lewycky
8e5c09b7dc
Add support for assembling "movq" when it's correct to do so, while continuing
...
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.
llvm-svn: 133565
2011-06-21 22:45:41 +00:00
Bob Wilson
5b04895bb8
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
...
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
llvm-svn: 133524
2011-06-21 17:35:13 +00:00
Nick Lewycky
831fb8200d
Emit movq for 64-bit register to XMM register moves, but continue to accept
...
movd when assembling.
llvm-svn: 133452
2011-06-20 18:33:26 +00:00
Hans Wennborg
6229bbd9c0
MC: Allow .common as alias for .comm assembler directive. PR10116.
...
llvm-svn: 133349
2011-06-18 13:51:54 +00:00
Bill Wendling
5ae6b0c972
Improve the heuristic to emit the alias if the number of hard-coded registers
...
are also greater than the alias.
llvm-svn: 133038
2011-06-15 04:31:19 +00:00
Bill Wendling
77d4d62693
Heuristic: If the number of operands in the alias are more than the number of
...
operands in the aliasee, don't print the alias.
llvm-svn: 132963
2011-06-14 03:17:20 +00:00
Roman Divacky
478976c99b
Test that ".byte 1, 2, 3, 4" does the right thing.
...
Requested by nbjoerg!
llvm-svn: 132716
2011-06-07 17:32:17 +00:00
Rafael Espindola
f500121fcf
Basic support for macros with explicit arguments.
...
We still don't handle
* default values
* :req
* :vararg
* \()
llvm-svn: 132656
2011-06-05 02:43:45 +00:00
Nick Lewycky
36e7570fb3
Add support for @GOTPTOFF in i386 mode.
...
llvm-svn: 132643
2011-06-04 17:38:07 +00:00
Bruno Cardoso Lopes
0bdb365634
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
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must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
llvm-svn: 132324
2011-05-31 03:33:27 +00:00
Rafael Espindola
9550e237a8
Use %rbp on a 64 bit test.
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llvm-svn: 132279
2011-05-29 04:04:50 +00:00
Benjamin Kramer
ad67c34014
Move ARM specific test into the ARM subdir.
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llvm-svn: 132255
2011-05-28 11:01:30 +00:00
Bruno Cardoso Lopes
93eae0fd19
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
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mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
llvm-svn: 132233
2011-05-27 23:46:09 +00:00
Charles Davis
cb20ea9935
Add the suffix to the Win64 EH data sections' names if given. Add a test for
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this. XFAIL'd, because the COFF AsmParser can't handle .section yet.
llvm-svn: 132220
2011-05-27 21:38:47 +00:00
Charles Davis
01cde4d080
Assorted fixes for Win64 EH unwind info emission:
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- Flip order of bitfields. This gets our output matching GAS.
- Handle case where the end of the prolog wasn't specified.
- If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes.
Add a test for the latter two.
llvm-svn: 132188
2011-05-27 15:10:25 +00:00
Charles Davis
028e424cf3
Add a test for Win64 EH unwind information emission.
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llvm-svn: 132180
2011-05-27 03:54:43 +00:00
Charles Davis
cf332d9ff7
Add a test for the chained directives that I forgot last time.
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llvm-svn: 132110
2011-05-26 05:17:43 +00:00
Charles Davis
0021487a8e
Test .seh_startchained and .seh_endchained parsing.
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Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.
The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.
llvm-svn: 132106
2011-05-26 02:45:47 +00:00
Charles Davis
ede0f07dae
Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with
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them.
I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.
llvm-svn: 132084
2011-05-25 21:43:45 +00:00
Charles Davis
6b67ee5130
Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the
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buggy methods that parse these directives.
llvm-svn: 132045
2011-05-25 04:51:25 +00:00
Charles Davis
14a32a9608
Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another
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one I found by inspection).
llvm-svn: 132037
2011-05-25 04:08:15 +00:00
Charles Davis
967ee6a30b
Add a test for the .seh_handler directive. Fix problems with the parsing
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method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.
llvm-svn: 132028
2011-05-25 01:33:42 +00:00
Bruno Cardoso Lopes
3a4aae57f4
Fix PR9762
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Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
llvm-svn: 132026
2011-05-25 00:35:03 +00:00
Charles Davis
d943eb05ed
Test basic SEH directive-parsing functionality. Fix a latent bug exposed by
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this test.
llvm-svn: 132004
2011-05-24 21:22:53 +00:00
Chris Lattner
859ce35115
add test from PR9164
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llvm-svn: 131876
2011-05-22 22:35:34 +00:00
Chris Lattner
009caa6b41
testcase for PR9378
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llvm-svn: 131875
2011-05-22 22:32:53 +00:00
Johnny Chen
6e8aeaa2f4
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
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Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
llvm-svn: 131859
2011-05-22 17:51:04 +00:00
Rafael Espindola
f114810ec8
adds some attributes to attribute section when cpu is "xscale"
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(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
llvm-svn: 131751
2011-05-20 20:10:34 +00:00
Rafael Espindola
27dbdbdf4c
fixes target address tBL and tBLX and sets relocation type
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of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
llvm-svn: 131748
2011-05-20 20:01:01 +00:00
Jason W Kim
93cb3f967d
This fixes one divergence between LLVM and binutils for ARM in the
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text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
llvm-svn: 131674
2011-05-19 20:55:25 +00:00
Rafael Espindola
826d41a144
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
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Fixes PR9934.
We really need to start tblgening the relocation info :-(
llvm-svn: 131669
2011-05-19 20:32:34 +00:00
Johnny Chen
3d6c5f4876
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
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llvm-svn: 131565
2011-05-18 20:32:41 +00:00
Rafael Espindola
e0b15205c1
sets bit 0 of the function address of thumb function in .symtab
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("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
llvm-svn: 131406
2011-05-16 16:17:21 +00:00
Owen Anderson
50766bc2f2
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
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llvm-svn: 131189
2011-05-11 17:00:48 +00:00
Rafael Espindola
e8890f4b16
On MachO, unlike ELF, there should be no relocation to produce the CIE pointer.
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llvm-svn: 131149
2011-05-10 20:59:42 +00:00
Rafael Espindola
ff4443c82c
In a debug_frame the cfi offset is to the start of the debug_frame section!
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llvm-svn: 131129
2011-05-10 15:20:23 +00:00
Rafael Espindola
b7c942431f
Add support for producing .deubg_frame sections.
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llvm-svn: 131121
2011-05-10 03:54:12 +00:00
Jakob Stoklund Olesen
8a075ce7ea
Explicitly request -join-physregs for some tests that depend on it.
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llvm-svn: 130855
2011-05-04 19:01:59 +00:00
Eric Christopher
4f90f378ee
Remove some random comments that snuck in from somewhere.
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llvm-svn: 130812
2011-05-04 00:48:02 +00:00
Eric Christopher
1de0dfaab0
xmm0 is an implicit parameter in this and so shouldn't be in the
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string template.
Fixes rdar://8493866
llvm-svn: 130747
2011-05-03 01:28:32 +00:00
Daniel Dunbar
9a87852114
MCAsmLayout: Add support for computing the symbol offset of variables. Not
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currently used, because variables don't get reported as being "defined".
llvm-svn: 130524
2011-04-29 18:20:20 +00:00
Daniel Dunbar
1488659798
MC: Change variable symbols to be recognized as defined, by assigning their sections based on FindAssociatedSection().
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llvm-svn: 130523
2011-04-29 18:20:17 +00:00
Johnny Chen
ac8aeb22e4
Add tests for A8.6.110 NOP.
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llvm-svn: 130345
2011-04-27 23:29:21 +00:00
Chandler Carruth
74094b8d4a
Remove some hard coded CR-LFs. Some of these were the entire files, one of
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these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.
llvm-svn: 130125
2011-04-25 07:11:23 +00:00
Johnny Chen
dfac31bc1b
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
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print out ldr, not ldr.n.
rdar://problem/9267772
llvm-svn: 130008
2011-04-22 19:12:43 +00:00
Rafael Espindola
e206800036
Fix relative relocations. This is sufficient for running the rust testsuite with
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MC :-)
llvm-svn: 129923
2011-04-21 18:36:50 +00:00
Rafael Espindola
032ab8c114
Behave like gnu as when a relocation crosses sections.
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llvm-svn: 129850
2011-04-20 14:01:45 +00:00