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3210 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
6a2bfde3c8 TwoAddressInstructionPass doesn't really know how to merge live intervals when 
lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

llvm-svn: 104146
 2010-05-19 20:08:00 +00:00
Bob Wilson
e5f623ac22 Testcase to go with 104141. 
llvm-svn: 104142
 2010-05-19 18:58:37 +00:00
Evan Cheng
6f52107b12 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. 
llvm-svn: 104115
 2010-05-19 07:28:01 +00:00
Evan Cheng
632cb17357 Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. 
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094
 2010-05-19 01:08:17 +00:00
Jakob Stoklund Olesen
f3114dbb3a Remember to update VirtRegLastUse when spilling without killing before a call. 
llvm-svn: 104074
 2010-05-18 22:20:09 +00:00
Dan Gohman
eaa3ee65bd When converting a test to a cmp to fold a load, use the cmp that has an 
8-bit immediate field rather than one with a wider immediate field.

llvm-svn: 104064
 2010-05-18 21:42:03 +00:00
Evan Cheng
e2980af336 Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
llvm-svn: 104060
 2010-05-18 21:31:17 +00:00
Evan Cheng
9fc34e676d Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE. 
llvm-svn: 104050
 2010-05-18 20:03:28 +00:00
Daniel Dunbar
8c20c162fe MC/X86: Implement custom lowering to make sure we match things like 
X86::ADC32ri $0, %eax
to
  X86::ADC32i32 $0

llvm-svn: 104030
 2010-05-18 17:22:24 +00:00
Evan Cheng
39b5115e93 FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). 
llvm-svn: 104004
 2010-05-18 00:03:40 +00:00
Evan Cheng
8aa900cf16 Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions. 
llvm-svn: 103994
 2010-05-17 23:24:12 +00:00
Evan Cheng
378d6c5d76 Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. 
llvm-svn: 103984
 2010-05-17 22:09:49 +00:00
Evan Cheng
bb0a4fbe13 Careful with reg_sequence coalescing to not to overwrite sub-register indices. 
llvm-svn: 103971
 2010-05-17 20:57:12 +00:00
Evan Cheng
3bce87c79f Turn on -neon-reg-sequence by default. 
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!

llvm-svn: 103960
 2010-05-17 19:51:20 +00:00
Jakob Stoklund Olesen
c07fd51d56 Avoid allocating the same physreg to multiple virtregs in one instruction. 
While that approach works wonders for register pressure, it tends to break
everything.

This should unbreak the arm-linux builder and fix a number of miscompilations.

llvm-svn: 103946
 2010-05-17 17:18:59 +00:00
Jakob Stoklund Olesen
40545bf117 Only use clairvoyance when defining a register, and then only if it has one use. 
This makes allocation independent on the ordering of use-def chains.

llvm-svn: 103935
 2010-05-17 04:50:57 +00:00
Dale Johannesen
b71d6a4150 Removing as part of previous reversion. 
llvm-svn: 103915
 2010-05-16 20:19:40 +00:00
Dale Johannesen
cf2d4b9f91 Revert 103911; it broke a test that expects bitconvert 
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine).  The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.

llvm-svn: 103914
 2010-05-16 20:19:04 +00:00
Dale Johannesen
15dce10b5a Make x86-64 64-bit bitconvert work when SSE is not available. 
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)

llvm-svn: 103911
 2010-05-16 18:22:38 +00:00
Anton Korobeynikov
925a32ae37 Add support for thiscall calling convention. 
Patch by Charles Davis and Steven Watanabe!

llvm-svn: 103902
 2010-05-16 09:08:45 +00:00
Anton Korobeynikov
314ccc5501 Some cheap DAG combine goodness for multiplication with a particular constant. 
This can be extended later on to handle more "complex" constants.

llvm-svn: 103881
 2010-05-15 18:16:59 +00:00
Evan Cheng
85497bd415 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
 2010-05-15 02:18:07 +00:00
Bill Wendling
5fde821884 SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and 
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)

llvm-svn: 103829
 2010-05-14 22:17:42 +00:00
Jakob Stoklund Olesen
3eac02b22f Simplify the handling of physreg defs and uses in RegAllocFast. 
This adds extra security against using clobbered physregs, and it adds kill
markers to physreg uses.

llvm-svn: 103784
 2010-05-14 18:03:25 +00:00
Jakob Stoklund Olesen
d99818256c Take allocation hints from copy instructions to/from physregs. 
This causes way more identity copies to be generated, ripe for coalescing.

llvm-svn: 103686
 2010-05-13 00:19:43 +00:00
Jakob Stoklund Olesen
7d1323d9a5 Make sure to add kill flags to the last use of a virtreg when it is redefined. 
The X86 floating point stack pass and others depend on good kill flags.

llvm-svn: 103635
 2010-05-12 18:46:03 +00:00
Jakob Stoklund Olesen
6976c543cd Enable a bunch more -regalloc=fast tests 
llvm-svn: 103531
 2010-05-12 00:11:24 +00:00
Jakob Stoklund Olesen
063844f706 Keep track of the last place a live virtreg was used. 
This allows us to add accurate kill markers, something the scavenger likes.
Add some more tests from ARM that needed this.

llvm-svn: 103521
 2010-05-11 23:24:45 +00:00
Jakob Stoklund Olesen
99d5d74fb0 One more -regalloc=fast test 
llvm-svn: 103509
 2010-05-11 20:51:07 +00:00
Jakob Stoklund Olesen
e27902ac68 Simplify the tracking of used physregs to a bulk bitor followed by a transitive 
closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

llvm-svn: 103500
 2010-05-11 20:30:28 +00:00
Jakob Stoklund Olesen
442e38c4de Mostly rewrite RegAllocFast. 
Sorry for the big change. The path leading up to this patch had some TableGen
changes that I didn't want to commit before I knew they were useful. They
weren't, and this version does not need them.

The fast register allocator now does no liveness calculations. Instead it relies
on kill flags provided by isel. (Currently those kill flags are also ignored due
to isel bugs). The allocation algorithm is supposed to work with any subset of
valid kill flags. More kill flags simply means fewer spills inserted.

Registers are allocated from a working set that contains no aliases. That means
most allocations can be done directly without expensive alias checks. When the
working set runs out of registers we do the full alias check to find new free
registers.

llvm-svn: 103488
 2010-05-11 18:54:45 +00:00
Kalle Raiskila
e302300b51 Make SPU backend not assert on jump tables. 
llvm-svn: 103466
 2010-05-11 11:00:02 +00:00
Evan Cheng
11130a0a22 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
llvm-svn: 103459
 2010-05-11 07:26:32 +00:00
Evan Cheng
df350445c6 Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869. 
llvm-svn: 103419
 2010-05-10 19:03:57 +00:00
Kalle Raiskila
61289abcda Fix encoding of 'sf' and 'sfh' instructions. 
llvm-svn: 103399
 2010-05-10 08:13:49 +00:00
Bill Wendling
787de8fe38 Readd testcase. 
llvm-svn: 103335
 2010-05-08 04:47:54 +00:00
Dan Gohman
4ca74b9c6c When pruning candidate formulae out of an LSRUse, update the 
LSRUse's Regs set after all pruning is done, rather than trying
to do it on the fly, which can produce an incomplete result.

This fixes a case where heuristic pruning was stripping all
formulae from a use, which led the solver to enter an infinite
loop.

Also, add a few asserts to diagnose this kind of situation.

llvm-svn: 103328
 2010-05-07 23:36:59 +00:00
Bill Wendling
4241941b52 Remove. Don't XFAIL. 
llvm-svn: 103321
 2010-05-07 23:09:17 +00:00
Bill Wendling
3846ec7889 Temorarily revert r101984. 
llvm-svn: 103314
 2010-05-07 22:45:36 +00:00
Dan Gohman
95040c18f4 SDDbgValues are apparently not being legalized. Fix a symptom of the problem, 
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.

llvm-svn: 103310
 2010-05-07 22:19:08 +00:00
Dale Johannesen
1ee37ac5d4 Fix PR 7087, and probably other things, by extending 
getConstantFP to accept the two supported long double
target types.  This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.

llvm-svn: 103299
 2010-05-07 21:35:53 +00:00
Jim Grosbach
2db1618b44 Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
 2010-05-07 18:34:55 +00:00
Duncan Sands
ed2ef5a987 Correct some bogus target triples. 
llvm-svn: 103265
 2010-05-07 17:03:48 +00:00
Nick Lewycky
3e5720a898 Revert r103133 and add testcase from PR7066. 
llvm-svn: 103233
 2010-05-07 01:45:38 +00:00
Dan Gohman
f863ad3dc5 Disable the new unknown-location code for now. It causes a major 
increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226
 2010-05-07 01:08:53 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.

llvm-svn: 103194
 2010-05-06 20:33:48 +00:00
Dan Gohman
3190e5c292 Add a testcase for r103135, explicitly representing unknown 
locations in debug line info.

llvm-svn: 103189
 2010-05-06 17:49:17 +00:00
Chris Lattner
014a954e3d Fix PR7054 - Assertion `Symbol->isUndefined() && "Cannot define a symbol twice!"' failed. 
Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.

llvm-svn: 103140
 2010-05-06 00:05:37 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jakob Stoklund Olesen
2e5d12acfa Fix PR6520. An earlyclobber physreg must not be allocated to anything else. 
llvm-svn: 103133
 2010-05-05 23:07:41 +00:00