llvm-mirror

mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 00:12:50 +01:00

Author	SHA1	Message	Date
Jim Grosbach	9b9604762e	Add tests for ARM parsing of 'AND' instruction. llvm-svn: 135056	2011-07-13 18:55:14 +00:00
Jim Grosbach	5c366bfb36	Improve ARM assembly parsing diagnostics a bit. Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. llvm-svn: 135055	2011-07-13 18:49:30 +00:00
Jim Grosbach	a0a947a8ca	Add tests for ARM parsing of 'ADD' instruction llvm-svn: 135053	2011-07-13 18:12:46 +00:00
Jim Grosbach	7dbb39dffa	Destination register operand is optional for ADC and SBC ARM. llvm-svn: 135052	2011-07-13 17:57:17 +00:00
Jim Grosbach	5db1296fcd	Flesh out ARM Parser support for shifted-register operands. Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. llvm-svn: 135049	2011-07-13 17:50:29 +00:00
Jim Grosbach	295e53b228	Add check for predicate w/o S bit. llvm-svn: 134987	2011-07-12 16:25:04 +00:00
Jim Grosbach	fae61bb435	Fix recognition of ARM 'adcs' mnemonic. The 'CS' is not a predication suffix in this case. llvm-svn: 134903	2011-07-11 17:09:57 +00:00
Jim Grosbach	93f2ebb5e7	Simplify printing of ARM shifted immediates. Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902	2011-07-11 16:48:36 +00:00
Evan Cheng	1346a63a0f	- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884	2011-07-11 03:57:24 +00:00
Evan Cheng	71dc177796	Add support for ARM / Thumb mode switching with .code 16 and .code 32. llvm-svn: 134760	2011-07-08 22:36:29 +00:00
Evan Cheng	952943f744	Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590	2011-07-07 03:55:05 +00:00
Kevin Enderby	43cb64711d	Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501. llvm-svn: 134511	2011-07-06 17:55:20 +00:00
Kevin Enderby	59ba10f2ac	Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a push with a small constant produces a 2-byte push. llvm-svn: 134501	2011-07-06 17:23:46 +00:00
Eli Friedman	9765ae0015	Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269. llvm-svn: 134424	2011-07-05 18:21:20 +00:00
Joerg Sonnenberger	708b6e085d	Recognize the xstorerng alias for VIA PadLock's xstore instruction. llvm-svn: 134126	2011-06-30 01:38:03 +00:00
Jim Grosbach	88387d64d6	Asm parser range checking on .<size> <value> directives. For example, ".byte 256" would previously assert() when emitting an object file. Now it generates a diagnostic that the literal value is out of range. rdar://9686950 llvm-svn: 134069	2011-06-29 16:05:14 +00:00
Jim Grosbach	33470a73f0	ARM Thumb2 asm syntax optional destination operand for binary operators. When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: and r1, #ff and r1, r1, #ff rdar://9672867 llvm-svn: 133973	2011-06-28 00:19:13 +00:00
Jim Grosbach	190b9d7ec0	ARM Assembly support for Thumb mov-immediate. Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. llvm-svn: 133966	2011-06-27 23:54:06 +00:00
Jim Grosbach	7c950cf36c	ARM assembler support for ldmfd/stmfd mnemonics. llvm-svn: 133936	2011-06-27 20:32:18 +00:00
Jim Grosbach	7157b0228f	ARM assembler support for vpush/vpop. Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple writeback instructions w/ SP as the base pointer. rdar://9683231 llvm-svn: 133932	2011-06-27 20:00:07 +00:00
Jim Grosbach	210c7054ac	ARM Assembly syntax support for arithmetic implied dest operand. When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: sub r2, r2, #6 sub r2, #6 rdar://9682597 llvm-svn: 133925	2011-06-27 19:09:15 +00:00
Jim Grosbach	f8b05a7bbb	Move ARM-specific test to ARM directory. Hopefully make the x86-target-only Windows bots happy. llvm-svn: 133856	2011-06-25 01:53:17 +00:00
Jim Grosbach	c10ef9d30c	Testcase for r133818 llvm-svn: 133823	2011-06-24 20:59:01 +00:00
Eli Friedman	802029c494	Add support for movntil/movntiq mnemonics. Reported on llvmdev. llvm-svn: 133759	2011-06-23 21:07:47 +00:00
Nick Lewycky	8e5c09b7dc	Add support for assembling "movq" when it's correct to do so, while continuing to emit "movd" across the board to continue supporting a Darwin assembler bug. This is the reincarnation of r133452. llvm-svn: 133565	2011-06-21 22:45:41 +00:00
Bob Wilson	5b04895bb8	Revert r133452: "Emit movq for 64-bit register to XMM register moves..." This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using the integrated assembler. llvm-svn: 133524	2011-06-21 17:35:13 +00:00
Nick Lewycky	831fb8200d	Emit movq for 64-bit register to XMM register moves, but continue to accept movd when assembling. llvm-svn: 133452	2011-06-20 18:33:26 +00:00
Hans Wennborg	6229bbd9c0	MC: Allow .common as alias for .comm assembler directive. PR10116. llvm-svn: 133349	2011-06-18 13:51:54 +00:00
Bill Wendling	5ae6b0c972	Improve the heuristic to emit the alias if the number of hard-coded registers are also greater than the alias. llvm-svn: 133038	2011-06-15 04:31:19 +00:00
Bill Wendling	77d4d62693	Heuristic: If the number of operands in the alias are more than the number of operands in the aliasee, don't print the alias. llvm-svn: 132963	2011-06-14 03:17:20 +00:00
Roman Divacky	478976c99b	Test that ".byte 1, 2, 3, 4" does the right thing. Requested by nbjoerg! llvm-svn: 132716	2011-06-07 17:32:17 +00:00
Rafael Espindola	f500121fcf	Basic support for macros with explicit arguments. We still don't handle * default values * :req * :vararg * \() llvm-svn: 132656	2011-06-05 02:43:45 +00:00
Nick Lewycky	36e7570fb3	Add support for @GOTPTOFF in i386 mode. llvm-svn: 132643	2011-06-04 17:38:07 +00:00
Bruno Cardoso Lopes	0bdb365634	Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. llvm-svn: 132324	2011-05-31 03:33:27 +00:00
Rafael Espindola	9550e237a8	Use %rbp on a 64 bit test. llvm-svn: 132279	2011-05-29 04:04:50 +00:00
Benjamin Kramer	ad67c34014	Move ARM specific test into the ARM subdir. llvm-svn: 132255	2011-05-28 11:01:30 +00:00
Bruno Cardoso Lopes	93eae0fd19	ARM asm parser wasn't able to parse a "mov" instruction while in Thumb mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode, default to the Thumb 1 versions/encodings. llvm-svn: 132233	2011-05-27 23:46:09 +00:00
Charles Davis	cb20ea9935	Add the suffix to the Win64 EH data sections' names if given. Add a test for this. XFAIL'd, because the COFF AsmParser can't handle .section yet. llvm-svn: 132220	2011-05-27 21:38:47 +00:00
Charles Davis	01cde4d080	Assorted fixes for Win64 EH unwind info emission: - Flip order of bitfields. This gets our output matching GAS. - Handle case where the end of the prolog wasn't specified. - If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes. Add a test for the latter two. llvm-svn: 132188	2011-05-27 15:10:25 +00:00
Charles Davis	028e424cf3	Add a test for Win64 EH unwind information emission. llvm-svn: 132180	2011-05-27 03:54:43 +00:00
Charles Davis	cf332d9ff7	Add a test for the chained directives that I forgot last time. llvm-svn: 132110	2011-05-26 05:17:43 +00:00
Charles Davis	0021487a8e	Test .seh_startchained and .seh_endchained parsing. Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with chained unwind areas exposed by the test that were related to this. The ChainedParent field had the wrong address, because when the chained unwind info was added, the addresses shifted around. Now we store the pointers to the structures, which are now allocated from the MC heap. llvm-svn: 132106	2011-05-26 02:45:47 +00:00
Charles Davis	ede0f07dae	Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with them. I had to add a special SwitchSectionNoChange method to MCStreamer just for .seh_handlerdata. If this isn't OK, please let me know, and I'll find some other way to fix .seh_handlerdata streaming. llvm-svn: 132084	2011-05-25 21:43:45 +00:00
Charles Davis	6b67ee5130	Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the buggy methods that parse these directives. llvm-svn: 132045	2011-05-25 04:51:25 +00:00
Charles Davis	14a32a9608	Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another one I found by inspection). llvm-svn: 132037	2011-05-25 04:08:15 +00:00
Charles Davis	967ee6a30b	Add a test for the .seh_handler directive. Fix problems with the parsing method exposed by the test. While we're at it, simplify the .seh_proc parsing method. llvm-svn: 132028	2011-05-25 01:33:42 +00:00
Bruno Cardoso Lopes	3a4aae57f4	Fix PR9762 Enable the parsing of the operand "cpsr_all" for the ARM msr instruction llvm-svn: 132026	2011-05-25 00:35:03 +00:00
Charles Davis	d943eb05ed	Test basic SEH directive-parsing functionality. Fix a latent bug exposed by this test. llvm-svn: 132004	2011-05-24 21:22:53 +00:00
Chris Lattner	859ce35115	add test from PR9164 llvm-svn: 131876	2011-05-22 22:35:34 +00:00
Chris Lattner	009caa6b41	testcase for PR9378 llvm-svn: 131875	2011-05-22 22:32:53 +00:00
Johnny Chen	6e8aeaa2f4	Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. llvm-svn: 131859	2011-05-22 17:51:04 +00:00
Rafael Espindola	f114810ec8	adds some attributes to attribute section when cpu is "xscale" (this is what used in Android NDK, when architecture is ARMv5) patch by Koan-Sin Tan llvm-svn: 131751	2011-05-20 20:10:34 +00:00
Rafael Espindola	27dbdbdf4c	fixes target address tBL and tBLX and sets relocation type of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6) Patch by koan-sin tan. llvm-svn: 131748	2011-05-20 20:01:01 +00:00
Jason W Kim	93cb3f967d	This fixes one divergence between LLVM and binutils for ARM in the text section. Assume the following bit of annotated assembly: .section .data.rel.ro,"aw",%progbits .align 2 .LAlpha: .long startval(GOTOFF) .text .align 2 .type main,%function .align 4 main: ;;; assume "main" starts at offset 0x20 0x0 push {r11, lr} 0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-4) + 8) = -20 0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-8) + 8) = -16 0xc ... blah .LBeta: 0x10 add r0, pc, r0 0x14 ... blah .LGamma: 0x18 add r1, pc, r1 Above snippet results in the following relocs in the .o file for the first pair of movw/movt instructions 00000024 R_ARM_MOVW_PREL_NC .LAlpha 00000028 R_ARM_MOVT_PREL .LAlpha And the encoded instructions in the .o file for main: must be 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20 28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16 However, llc (prior to this commit) generates the following sequence 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20 28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1 What has to happen in the ArmAsmBackend is that if the relocation is PC relative, the 16 bits encoded as part of movw and movt must be both addends, not addresses. It makes sense to encode addresses by right shifting the value by 16, but the result is incorrect for PIC. i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case. This change agrees with what GNU as does, and makes the PIC code run. MC/ARM/elf-movt.s covers this case. llvm-svn: 131674	2011-05-19 20:55:25 +00:00
Rafael Espindola	826d41a144	ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S. Fixes PR9934. We really need to start tblgening the relocation info :-( llvm-svn: 131669	2011-05-19 20:32:34 +00:00
Johnny Chen	3d6c5f4876	Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. llvm-svn: 131565	2011-05-18 20:32:41 +00:00
Rafael Espindola	e0b15205c1	sets bit 0 of the function address of thumb function in .symtab ("T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction ;it is 0 otherwise." from "ELF for the ARM Architecture" 4.7.1.2) Patch by Koan-Sin Tan! llvm-svn: 131406	2011-05-16 16:17:21 +00:00
Owen Anderson	50766bc2f2	Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. llvm-svn: 131189	2011-05-11 17:00:48 +00:00
Rafael Espindola	e8890f4b16	On MachO, unlike ELF, there should be no relocation to produce the CIE pointer. llvm-svn: 131149	2011-05-10 20:59:42 +00:00
Rafael Espindola	ff4443c82c	In a debug_frame the cfi offset is to the start of the debug_frame section! llvm-svn: 131129	2011-05-10 15:20:23 +00:00
Rafael Espindola	b7c942431f	Add support for producing .deubg_frame sections. llvm-svn: 131121	2011-05-10 03:54:12 +00:00
Jakob Stoklund Olesen	8a075ce7ea	Explicitly request -join-physregs for some tests that depend on it. llvm-svn: 130855	2011-05-04 19:01:59 +00:00
Eric Christopher	4f90f378ee	Remove some random comments that snuck in from somewhere. llvm-svn: 130812	2011-05-04 00:48:02 +00:00
Eric Christopher	1de0dfaab0	xmm0 is an implicit parameter in this and so shouldn't be in the string template. Fixes rdar://8493866 llvm-svn: 130747	2011-05-03 01:28:32 +00:00
Daniel Dunbar	9a87852114	MCAsmLayout: Add support for computing the symbol offset of variables. Not currently used, because variables don't get reported as being "defined". llvm-svn: 130524	2011-04-29 18:20:20 +00:00
Daniel Dunbar	1488659798	MC: Change variable symbols to be recognized as defined, by assigning their sections based on FindAssociatedSection(). llvm-svn: 130523	2011-04-29 18:20:17 +00:00
Johnny Chen	ac8aeb22e4	Add tests for A8.6.110 NOP. llvm-svn: 130345	2011-04-27 23:29:21 +00:00
Chandler Carruth	74094b8d4a	Remove some hard coded CR-LFs. Some of these were the entire files, one of these was just one line of a file. Explicitly set the eol-style property on the files to try and ensure this fix stays. llvm-svn: 130125	2011-04-25 07:11:23 +00:00
Johnny Chen	dfac31bc1b	Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008	2011-04-22 19:12:43 +00:00
Rafael Espindola	e206800036	Fix relative relocations. This is sufficient for running the rust testsuite with MC :-) llvm-svn: 129923	2011-04-21 18:36:50 +00:00
Rafael Espindola	032ab8c114	Behave like gnu as when a relocation crosses sections. llvm-svn: 129850	2011-04-20 14:01:45 +00:00
Johnny Chen	d7a6b974bc	Thumb2 BFC was insufficiently encoded. rdar://problem/9292717 llvm-svn: 129619	2011-04-15 22:52:15 +00:00
Johnny Chen	2a183b813d	A8.6.315 VLD3 (single 3-element structure to all lanes) The a bit must be encoded as 0. rdar://problem/9292625 llvm-svn: 129618	2011-04-15 22:49:08 +00:00
Joerg Sonnenberger	42c3063de0	Add encoding tests for flds/filds llvm-svn: 129589	2011-04-15 19:25:31 +00:00
Chris Lattner	0304b82f80	Fix a ton of comment typos found by codespell. Patch by Luis Felipe Strano Moraes! llvm-svn: 129558	2011-04-15 05:18:47 +00:00
Johnny Chen	197d67a987	The ARM disassembler did not handle the alignment correctly for VLDDUP instructions (single element or n-element structure to all lanes). llvm-svn: 129550	2011-04-15 00:10:45 +00:00
Johnny Chen	d58c6d4730	Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. llvm-svn: 129531	2011-04-14 19:13:28 +00:00
Bill Wendling	0b9c16295a	As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498	2011-04-14 01:46:37 +00:00
Bill Wendling	d49591cf21	Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497	2011-04-14 01:11:51 +00:00
Johnny Chen	1362fdf7a6	Thumb disassembler did not handle tBRIND (indirect branch) properly. rdar://problem/9280370 llvm-svn: 129480	2011-04-13 21:59:01 +00:00
Johnny Chen	d4a0b55be5	Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471	2011-04-13 21:35:49 +00:00
Johnny Chen	dd6fc153b1	The LDRT/STRT (unpriviledged load/store) operations don't take SP or PC as Rt. rdar://problem/9279440 llvm-svn: 129469	2011-04-13 21:04:32 +00:00
Johnny Chen	b293311a34	Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. rdar://problem/9276651 llvm-svn: 129462	2011-04-13 19:46:05 +00:00
Johnny Chen	e94b35dc41	Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. rdar://problem/9276427 llvm-svn: 129456	2011-04-13 17:51:02 +00:00
Johnny Chen	5ae9980472	Add sanity check for Ld/St Dual forms of Thumb2 instructions. rdar://problem/9273947 llvm-svn: 129411	2011-04-12 23:31:00 +00:00
Johnny Chen	e3c070e904	The Thumb2 RFE instructions need to have their second halfword fully specified. In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391	2011-04-12 21:41:51 +00:00
Johnny Chen	4450794a69	Add bad register checks for Thumb2 Ld/St instructions. rdar://problem/9269047 llvm-svn: 129387	2011-04-12 21:17:51 +00:00
Johnny Chen	4435fc93c9	The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377	2011-04-12 18:48:00 +00:00
Johnny Chen	aaaa46cee2	Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. llvm-svn: 129365	2011-04-12 17:09:04 +00:00
Rafael Espindola	5c5bb3e9a6	Fix the case of a .cfi_rel_offset before any .cfi_def_cfa_offset. llvm-svn: 129362	2011-04-12 16:12:03 +00:00
Rafael Espindola	7c4de15c7b	Implement .cfi_same_value. llvm-svn: 129361	2011-04-12 15:31:05 +00:00
Johnny Chen	156517d4d2	Add one test case (svc). llvm-svn: 129327	2011-04-12 00:21:48 +00:00
Eric Christopher	b01713088d	Match case for invalid constant error messages and add a new test for invalid hexadecimals. llvm-svn: 129326	2011-04-12 00:18:03 +00:00
Johnny Chen	58713f0ec2	A8.6.16 B Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 llvm-svn: 129325	2011-04-12 00:14:49 +00:00
Eric Christopher	2dc03456d0	Test for invalid constant expr addition - bad octal constant. llvm-svn: 129323	2011-04-12 00:03:38 +00:00
Johnny Chen	443a6902bf	Thumb disassembler was erroneously rejecting "blx sp" instruction. rdar://problem/9267838 llvm-svn: 129320	2011-04-11 23:33:30 +00:00
Rafael Espindola	a1fb8a36f9	Implement cfi_rel_offset llvm-svn: 129306	2011-04-11 21:49:50 +00:00
Rafael Espindola	873ddd983f	Add test for previous commit. llvm-svn: 129304	2011-04-11 21:41:34 +00:00
Johnny Chen	77f484c5df	Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. rdar://problem/9266265 llvm-svn: 129298	2011-04-11 21:14:35 +00:00
Johnny Chen	b07cb8fee1	Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. llvm-svn: 129286	2011-04-11 18:34:12 +00:00
Chris Lattner	b9b420d588	fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately, InstAlias doesn't allow matching immediate operands, so we have to write C++ code to do this. llvm-svn: 129223	2011-04-09 19:41:05 +00:00
Benjamin Kramer	6f39531981	Don't store Twine temporaries, it's not safe. And don't append the name over and over again in the loop. llvm-svn: 129210	2011-04-09 11:26:27 +00:00
Johnny Chen	e2464aa24a	Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. PR9650 rdar://problem/9257565 llvm-svn: 129147	2011-04-08 19:41:22 +00:00
Johnny Chen	5b7854afa5	Sanity check the option operand for DMB/DSB. PR9648 rdar://problem/9257634 llvm-svn: 129146	2011-04-08 19:18:07 +00:00
Johnny Chen	2bb229ed27	MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it. Add tests for that. llvm-svn: 129137	2011-04-08 17:29:58 +00:00
Johnny Chen	16ed2c18a0	Add sanity checking for bad register specifier(s) for the DPFrm instructions. Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117	2011-04-08 00:29:09 +00:00
Rafael Espindola	c2955605da	Update tests llvm-svn: 129116	2011-04-07 23:51:25 +00:00
Johnny Chen	0b8e3b20f7	Add a VEXT test. llvm-svn: 129111	2011-04-07 22:04:01 +00:00
Rafael Espindola	a27969f537	Add support for .skip. Patch by Roman Divacky. Fixes PR9361. llvm-svn: 129106	2011-04-07 20:26:23 +00:00
Johnny Chen	5d23dd2116	Add sanity checking for invalid register encodings for signed/unsigned extend instructions. Add some test cases. llvm-svn: 129098	2011-04-07 19:28:58 +00:00
Johnny Chen	7198a60b9a	Add sanity checking for invalid register encodings for saturating instructions. llvm-svn: 129096	2011-04-07 19:02:08 +00:00
Johnny Chen	ecc113f223	Add some more comments about checkings of invalid register numbers. And two test cases. llvm-svn: 129090	2011-04-07 18:33:19 +00:00
Johnny Chen	4c81015af7	Sanity check MSRi for invalid mask values and reject it as invalid. rdar://problem/9246844 llvm-svn: 129050	2011-04-07 01:37:34 +00:00
Johnny Chen	1f028bb23e	The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047	2011-04-07 01:05:52 +00:00
Johnny Chen	523f8f38f7	Should also check SMLAD for invalid register values. rdar://problem/9246650 llvm-svn: 129042	2011-04-07 00:50:25 +00:00
Johnny Chen	81aa7d84be	A8.6.393 The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- \| 1: 1: 1: 1\| 0: 1: 0: 0\| 0: 0: 0: 0\| 0: 0: 1: 1\| 0: 0: 0: 0\| 1: 0: 0: 1\| 1: 0: 1: 1\| 0: 0: 1: 1\| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- \| 1: 1: 1: 1\| 0: 1: 0: 0\| 0: 0: 0: 0\| 0: 0: 1: 1\| 0: 0: 0: 0\| 1: 0: 0: 1\| 1: 0: 1: 1\| 0: 0: 1: 1\| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033	2011-04-06 22:14:48 +00:00
Johnny Chen	96fd9620c8	A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027	2011-04-06 20:49:02 +00:00
Johnny Chen	b3130a03a7	Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 llvm-svn: 129015	2011-04-06 18:27:46 +00:00
Johnny Chen	765dec3867	Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977	2011-04-06 01:18:32 +00:00
Johnny Chen	48b39632aa	Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 llvm-svn: 128958	2011-04-05 23:28:00 +00:00
Johnny Chen	359b9a2331	A7.3 register encoding Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 llvm-svn: 128949	2011-04-05 22:57:07 +00:00
Johnny Chen	cf11408b65	ARM disassembler was erroneously accepting an invalid RSC instruction. Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945	2011-04-05 22:18:07 +00:00
Johnny Chen	6e1367d5dd	ARM disassembler was erroneously accepting an invalid LSL instruction. For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941	2011-04-05 21:49:44 +00:00
Johnny Chen	b50ab34083	The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922	2011-04-05 20:32:23 +00:00
Johnny Chen	4a15bdc1aa	ARM disassembler should flag (rGPRRegClassID, r13\|r15) as an error. llvm-svn: 128913	2011-04-05 19:42:11 +00:00
Johnny Chen	f2d8c2ea3d	LDRD now prints out two dst registers. llvm-svn: 128909	2011-04-05 18:53:14 +00:00
Johnny Chen	d37098ae32	Constants with multiple encodings (ARM): An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. llvm-svn: 128897	2011-04-05 18:02:46 +00:00
Johnny Chen	626c0a35f6	Check for invalid register encodings for UMAAL and friends where: if dLo == 15 \|\| dHi == 15 \|\| n == 15 \|\| m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; rdar://problem/9230202 llvm-svn: 128895	2011-04-05 17:43:10 +00:00
Johnny Chen	785ab1531b	Fix SRS/SRSW encoding bits. rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. llvm-svn: 128864	2011-04-05 00:16:18 +00:00
Johnny Chen	7fb247299a	Fix incorrect alignment for NEON VST2b32_UPD. rdar://problem/9225433 llvm-svn: 128841	2011-04-04 20:35:31 +00:00
Bruno Cardoso Lopes	74363376e4	- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832	2011-04-04 17:18:19 +00:00
Joerg Sonnenberger	1cbd300346	Add support for the VIA PadLock instructions. llvm-svn: 128826	2011-04-04 16:58:13 +00:00
Johnny Chen	dcd29e054c	Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757	2011-04-02 02:24:54 +00:00
Johnny Chen	6f10cfdf01	Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. rdar://problem/9224276 llvm-svn: 128749	2011-04-01 23:30:25 +00:00
Johnny Chen	b308662930	MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. rdar://problem/9224120 llvm-svn: 128748	2011-04-01 23:15:50 +00:00
Johnny Chen	845caa871c	Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- \| 1: 0: 0: 0\| 0: 0: 0: 0\| 1: 0: 1: 1\| 1: 0: 0: 0\| 1: 1: 1: 1\| 0: 0: 1: 1\| 0: 1: 0: 0\| 0: 0: 0: 0\| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- \| 1: 0: 0: 0\| 0: 0: 0: 0\| 1: 0: 1: 1\| 1: 0: 0: 0\| 1: 1: 1: 1\| 0: 0: 1: 1\| 0: 1: 0: 0\| 0: 0: 0: 0\| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 llvm-svn: 128746	2011-04-01 22:32:51 +00:00
Johnny Chen	65fe34ae00	Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction as invalid. llvm-svn: 128734	2011-04-01 20:21:38 +00:00
Johnny Chen	17f1f7c322	Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722	2011-04-01 18:26:38 +00:00
Bruno Cardoso Lopes	d285a7f27e	Apply again changes to support ARM memory asm parsing. I removed all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689	2011-03-31 23:26:08 +00:00
Johnny Chen	a7312b9622	Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which amounts to an UNDEFINED instruction. llvm-svn: 128668	2011-03-31 20:54:30 +00:00
Johnny Chen	2c5149791a	Fix single word and unsigned byte data transfer instruction encodings so that Inst{4} = 0. rdar://problem/9213022 llvm-svn: 128662	2011-03-31 19:28:35 +00:00
Johnny Chen	0bb797b2f3	Add BLXi to the instruction table for disassembly purpose. A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644	2011-03-31 17:53:50 +00:00
Daniel Dunbar	5827f55cc7	Remove stray empty test file. llvm-svn: 128640	2011-03-31 17:01:56 +00:00
Bruno Cardoso Lopes	392dbfd384	Revert r128632 again, until I figure out what break the tests llvm-svn: 128635	2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes	3b2f5421ac	Reapply r128585 without generating a lib depedency cycle. An updated log: - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632	2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay	325e16f668	Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597	2011-03-31 00:39:16 +00:00
Bruno Cardoso Lopes	cebbf7fe68	- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585	2011-03-30 23:32:32 +00:00
Johnny Chen	326082e0b2	Add a test case for thumb stc2 instruction. llvm-svn: 128517	2011-03-30 01:02:06 +00:00
Kevin Enderby	976435fa83	Adding a test for "-inf" as well. llvm-svn: 128495	2011-03-29 21:54:10 +00:00
Johnny Chen	28a32ef2d7	Add a test case for MSRi. llvm-svn: 128494	2011-03-29 21:52:02 +00:00
Kevin Enderby	1ece39d99c	Added support symbolic floating point constants in the MC assembler for Infinity and Nans with the same strings as GAS supports. rdar://8673024 llvm-svn: 128488	2011-03-29 21:11:52 +00:00
Johnny Chen	3c4cb78640	Add a thumb test file for printf (iOS 4.3). llvm-svn: 128487	2011-03-29 21:09:30 +00:00
Johnny Chen	ab342ac374	A8.6.188 STC, STC2 The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 llvm-svn: 128478	2011-03-29 19:49:38 +00:00
Johnny Chen	9a61664869	Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt. llvm-svn: 128477	2011-03-29 19:10:06 +00:00
Johnny Chen	1cd323de0a	Add and modify some tests. llvm-svn: 128476	2011-03-29 19:08:52 +00:00
Owen Anderson	d73041e884	Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. llvm-svn: 128461	2011-03-29 16:45:53 +00:00
Daniel Dunbar	5d8c7d0d36	MC: Add support for disabling "temporary label" behavior. Useful for debugging on Darwin. llvm-svn: 128430	2011-03-28 22:49:15 +00:00
Johnny Chen	8b921cebc6	Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. llvm-svn: 128417	2011-03-28 18:41:58 +00:00
Johnny Chen	61713b9c16	Fixed the t2PLD and friends disassembly and add two test cases. llvm-svn: 128322	2011-03-26 01:32:48 +00:00
Johnny Chen	7238c61ff7	Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt. llvm-svn: 128306	2011-03-25 23:02:58 +00:00
Johnny Chen	4c59e0a556	Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul(). llvm-svn: 128305	2011-03-25 22:43:28 +00:00
Johnny Chen	75c4627aea	Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. Also add some test cases. rdar://problem/9189829 llvm-svn: 128304	2011-03-25 22:19:07 +00:00
Johnny Chen	5b840e19ef	DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. rdar://problem/9182892 llvm-svn: 128299	2011-03-25 19:35:37 +00:00
Johnny Chen	f16635a8f0	A8.6.226 TBB, TBH: Add two test cases. llvm-svn: 128295	2011-03-25 18:40:21 +00:00
Johnny Chen	c69c7b19ae	Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to t2LDREX/t2STREX instructions. Add two test cases. llvm-svn: 128293	2011-03-25 18:29:49 +00:00
Daniel Dunbar	1cbd2c6c88	MC: Improve some diagnostics on uses of '.' pseudo-symbol. llvm-svn: 128289	2011-03-25 17:47:17 +00:00
Johnny Chen	f19366e37b	Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that. rdar://problem/9184053 llvm-svn: 128285	2011-03-25 17:31:16 +00:00
Johnny Chen	583b7cb25e	Also need to handle invalid imod values for CPS2p. rdar://problem/9186136 llvm-svn: 128283	2011-03-25 17:03:12 +00:00
Johnny Chen	1f29c2775d	Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. llvm-svn: 128252	2011-03-25 01:09:48 +00:00
Johnny Chen	a4f73530a5	delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. llvm-svn: 128249	2011-03-25 00:17:42 +00:00
Johnny Chen	4a55a733b8	The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. llvm-svn: 128247	2011-03-24 23:42:31 +00:00
Johnny Chen	6345e6a882	The ARM disassembler was confused with the 16-bit tSTMIA instruction. According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. llvm-svn: 128246	2011-03-24 23:21:14 +00:00
Johnny Chen	9672fe0126	Handle the added VBICivi NEON instructions, too. llvm-svn: 128243	2011-03-24 22:04:39 +00:00
Johnny Chen	1fc160fa19	T2 Load/Store Multiple: These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. llvm-svn: 128240	2011-03-24 21:36:56 +00:00
Benjamin Kramer	a9c4afdeec	Plug a leak in the arm disassembler and put the tests back. llvm-svn: 128238	2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes	a5de5df6d8	Add asm parsing support w/ testcases for strex/ldrex family of instructions llvm-svn: 128236	2011-03-24 21:04:58 +00:00
Johnny Chen	ef99d9b9eb	Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'. These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble. llvm-svn: 128235	2011-03-24 20:56:23 +00:00
Johnny Chen	ae5d27987a	ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234	2011-03-24 20:42:48 +00:00
Johnny Chen	f6655e82b3	The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the VORRivi instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. llvm-svn: 128226	2011-03-24 18:40:38 +00:00
Johnny Chen	154393018f	Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range. llvm-svn: 128220	2011-03-24 17:04:22 +00:00
Johnny Chen	404fb6c07f	Load/Store Multiple: These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add two test cases. llvm-svn: 128191	2011-03-24 01:40:42 +00:00
Johnny Chen	0d55ce3734	STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). We now tag them as IndexModePost. llvm-svn: 128189	2011-03-24 01:07:26 +00:00
Johnny Chen	f8507c96f1	The r128103 fix to cope with the removal of addressing modes from the MC instructions were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. llvm-svn: 128186	2011-03-24 00:28:38 +00:00
Johnny Chen	b9309ecef1	Add disassembly test cases for: A8.6.292 VCMPE llvm-svn: 128120	2011-03-22 23:08:56 +00:00
Johnny Chen	beb7e880a2	LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). We now tag them as IndexModePost. This fixed http://llvm.org/bugs/show_bug.cgi?id=9530. llvm-svn: 128113	2011-03-22 22:28:49 +00:00
Johnny Chen	a31ae5ca74	Add one more test case for VFP Load/Store Multiple (vpop). llvm-svn: 128106	2011-03-22 20:21:08 +00:00
Johnny Chen	90908a8eeb	A8.6.399 VSTM: VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm() to reflect the change. Also add a test case. llvm-svn: 128103	2011-03-22 20:00:10 +00:00
Rafael Espindola	b5c6ae67ac	Write the section table and the section data in the same order that gun as does. This makes it a lot easier to compare the output of both as the addresses are now a lot closer. llvm-svn: 127972	2011-03-20 18:44:20 +00:00
Johnny Chen	3520263009	Fixed an assert by the ARM disassembler for LDRD_PRE/POST. The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. llvm-svn: 127935	2011-03-19 01:16:20 +00:00
Owen Anderson	16fce7d4af	Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. llvm-svn: 127917	2011-03-18 22:50:18 +00:00
Joerg Sonnenberger	aa8ac259e9	Support explicit argument forms for the X86 string instructions. For now, only the default segments are supported. llvm-svn: 127875	2011-03-18 11:59:40 +00:00
Johnny Chen	14f091b6ab	The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset. Remove the offending logic and update the test cases. llvm-svn: 127843	2011-03-18 00:38:03 +00:00
Johnny Chen	41abb5b0f7	It used to be that t_addrmode_s4 was used for both: o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. llvm-svn: 127833	2011-03-17 22:04:05 +00:00
Daniel Dunbar	0e9d7aeb1f	MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have been removed. llvm-svn: 127812	2011-03-17 16:25:24 +00:00
Joerg Sonnenberger	e37bdf4386	Fix handling of @IDNTPOFF relocations, they need to get STT_TLS. While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too. llvm-svn: 127780	2011-03-17 00:35:10 +00:00
Johnny Chen	e88573849d	There were two issues fixed: 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. llvm-svn: 127707	2011-03-15 22:27:33 +00:00
Sean Callanan	e78b505311	Basic sanity checks to ensure that 2- and 3-byte VEX prefixes are working for triadic AVX instructions. This concludes the patch set to enable AVX support for the X86 disassebler. llvm-svn: 127647	2011-03-15 01:32:46 +00:00
Johnny Chen	a86399b8e6	Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 llvm-svn: 127642	2011-03-15 01:13:17 +00:00
Cameron Zwarich	bf5c9cd119	Roll r127459 back in: Optimize trivial branches in CodeGenPrepare, which often get created from the lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. llvm-svn: 127498	2011-03-11 21:52:04 +00:00
Daniel Dunbar	a02706c889	Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get created from the", it broke some GCC test suite tests. llvm-svn: 127477	2011-03-11 19:30:30 +00:00
Cameron Zwarich	9ed726c151	Optimize trivial branches in CodeGenPrepare, which often get created from the lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. llvm-svn: 127459	2011-03-11 04:54:27 +00:00
Johnny Chen	6bf5d7a170	LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. The insufficient encoding information of the combined instruction confuses the decoder wrt UQADD16. Add extra logic to recover from that. Fixed an assert reported by Sean Callanan llvm-svn: 127354	2011-03-09 20:01:14 +00:00
Bill Wendling	68934338ab	* Correct encoding for VSRI. * Add tests for VSRI and VSLI. llvm-svn: 127297	2011-03-09 00:33:17 +00:00
Bill Wendling	b790c462c0	Correct the encoding for VRSRA and VSRA instructions. llvm-svn: 127294	2011-03-09 00:00:35 +00:00
Bill Wendling	ab9f04b6d8	* Fix VRSHR and VSHR to have the correct encoding for the immediate. * Update the NEON shift instruction test to expect what 'as' produces. llvm-svn: 127293	2011-03-08 23:48:09 +00:00
Bill Wendling	0e4923ebe5	A few more tests for instruction encodings. llvm-svn: 127209	2011-03-08 02:51:48 +00:00
Bill Wendling	958e854f40	Rename the narrow shift right immediate operands to "shr_imm*" operands. Also expand the testing of the narrowing shift right instructions. No functionality change. llvm-svn: 127193	2011-03-07 23:38:41 +00:00
Joerg Sonnenberger	5f2f5fa638	Be nice to Xcore and the XMOS assembler and avoid quoting section names that contain only letters, digits and the characters "_" and ".". llvm-svn: 127028	2011-03-04 20:03:14 +00:00
Eli Friedman	7243ca7572	Followup to r126970: add 64-bit encoding tests for str with reg operand. llvm-svn: 126987	2011-03-04 04:06:47 +00:00
Eli Friedman	be07c34368	PR9377: Handle x86 str with register operand in a way consistent with gas. llvm-svn: 126970	2011-03-04 00:10:17 +00:00
Joerg Sonnenberger	bb93506f95	Bug#9033: For the ELF assembler output, always quote the section name. llvm-svn: 126963	2011-03-03 22:31:08 +00:00
Eli Friedman	f7eb4cce13	PR9352: Always emit a relocation for weak symbols. Not emitting relocations for calls to weak symbols with a definition has the appearance of working with LLVM-generated code because weak symbol definitions are put in their own sections. llvm-svn: 126933	2011-03-03 07:24:36 +00:00
Bob Wilson	e24bee9ce8	TableGen should not ignore BX instructions for the ARM disassembler. pr9368. llvm-svn: 126931	2011-03-03 07:19:52 +00:00
Bob Wilson	42f80596ca	pr9367: Add missing predicated BLX instructions. Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915	2011-03-03 01:41:01 +00:00
Kevin Enderby	58cc960338	Fixes an assertion failure while disassembling ARM rsbs reg/reg form. Patch by Ted Kremenek! llvm-svn: 126895	2011-03-02 23:08:33 +00:00
Bill Wendling	304dda7810	Narrow right shifts need to encode their immediates differently from a normal shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> llvm-svn: 126723	2011-03-01 01:00:59 +00:00
Kevin Enderby	a1c2ea4ba0	Fix the arm's disassembler for blx that was building an MCInst without the needed two predicate operands before the imm operand. llvm-svn: 126662	2011-02-28 18:46:31 +00:00
Chris Lattner	90c8cff37e	split this test into arch specific pieces, so the ARM test isn't run when the arm backend isn't built. This fixes PR9327 llvm-svn: 126500	2011-02-25 19:06:35 +00:00
Joerg Sonnenberger	9c30c492df	Restore r125595 (reverted in r126336) with modifications: Introduce a variable in the AsmParserExtension whether [] is valid in an expression. If it is true, parse them like (). Enable this for ELF only. llvm-svn: 126443	2011-02-24 21:59:22 +00:00
Devang Patel	bac565c8a3	Move arch specific tests in arch specific directories. llvm-svn: 126401	2011-02-24 19:06:27 +00:00
Jim Grosbach	d8032abf70	Remove file. Previous commit deleted content, but left the file around. llvm-svn: 126337	2011-02-23 21:43:31 +00:00
Jim Grosbach	e7be1f2990	Revert r125595, which is an X86-only undocumented assembly syntax extension enabled for all targets. Non-X86 targets should not have this behavior enabled by default. Joerg, if you would like to resubmit with the behavior conditionalized to be X86-ELF only, that's fine. llvm-svn: 126336	2011-02-23 21:26:51 +00:00
Rafael Espindola	993a4ef35c	Put in the symbol table symbols only used in a .globl statement. Fixes PR9292. llvm-svn: 126330	2011-02-23 20:22:07 +00:00
Sean Callanan	e1308394f1	Fixed a bug in the enhanced disassembler that caused it to ignore valid uses of FS and GS as additional base registers in address computations. Added a test case for this. llvm-svn: 126302	2011-02-23 03:31:28 +00:00
Joerg Sonnenberger	67e0eb235d	Use the same (%dx) hack for in[bwl] as for out[bwl]. llvm-svn: 126244	2011-02-22 20:40:09 +00:00
Sean Callanan	419a1b871e	Added a testcase for the enhanced disassembly bug fixed in r126147, where a field in the X86 decode structure was being read as bits, not bytes. llvm-svn: 126182	2011-02-22 02:19:18 +00:00
Joerg Sonnenberger	9dceff5417	Recognize loopz and loopnz as aliases for loope and loopne. From Dimitry Andric. llvm-svn: 126168	2011-02-22 00:43:07 +00:00
Rafael Espindola	e4a04cce2b	Implement xgetbv and xsetbv. Patch by Jai Menon. llvm-svn: 126165	2011-02-22 00:35:18 +00:00
Joerg Sonnenberger	dfe33572b5	Handle FK_PCRel_1 and add a test case for this and FK_PCRel_4. llvm-svn: 126157	2011-02-21 23:25:41 +00:00
Rafael Espindola	5fd4a261e7	Add some limited support for labels in org directives. Hopefully enough to fix PR9245. llvm-svn: 126091	2011-02-20 20:20:07 +00:00
Chris Lattner	7cd801727d	implement PR9264: disambiguating 'bt mem, imm' as a btl. This is reasonable to do since all bt-mem forms do the same thing. llvm-svn: 126047	2011-02-19 21:06:36 +00:00
Bruno Cardoso Lopes	ad05904e0b	Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948	2011-02-18 19:45:59 +00:00
Joerg Sonnenberger	efa8090e2a	Recognize monitor/mwait with explicit register arguments llvm-svn: 125805	2011-02-18 00:48:11 +00:00
Joerg Sonnenberger	9f8f3a2c59	Recognize leavel and leaveq aliases for leave. Validate encoding of leave in 64bit mode. llvm-svn: 125795	2011-02-17 23:36:39 +00:00
Rafael Espindola	4ef1268b39	Gas is very inconsistent about when a relaxation/relocation is needed. Do the right thing and stop trying to copy it. Fixes PR8944. llvm-svn: 125648	2011-02-16 03:25:55 +00:00
Rafael Espindola	b59fdeb3de	Add support for pushsection and popsection. Patch by Joerg Sonnenberger. llvm-svn: 125629	2011-02-16 01:08:29 +00:00
Roman Divacky	3277e18a42	Add support for parsing [expr]. This is submitted by Joerg Sonnenberger and fixes his PR8685. llvm-svn: 125595	2011-02-15 20:43:39 +00:00
Bruno Cardoso Lopes	e65a98b127	Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489	2011-02-14 13:09:44 +00:00
Reid Kleckner	0e68b2ed88	Add encodings and mnemonics for FXSAVE64 and FXRSTOR64. These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use 64-bit pointer values instead of 32-bit pointer values in the memory map they dump and restore. llvm-svn: 125446	2011-02-12 23:24:13 +00:00
Jim Grosbach	48e8554772	Do AsmMatcher operand classification per-opcode. When matching operands for a candidate opcode match in the auto-generated AsmMatcher, check each operand against the expected operand match class. Previously, operands were classified independently of the opcode being handled, which led to difficulties when operand match classes were more complicated than simple subclass relationships. llvm-svn: 125245	2011-02-10 00:08:28 +00:00
Owen Anderson	899a6d74bf	Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127	2011-02-08 22:39:40 +00:00
Benjamin Kramer	8ff71a1384	Support for .ifdef / .ifndef in the assembler parser. Patch by Joerg Sonnenberger. llvm-svn: 125120	2011-02-08 22:29:56 +00:00
Bruno Cardoso Lopes	0ce5b0f4a8	Add support for parsing dmb/dsb instructions llvm-svn: 125055	2011-02-07 22:09:15 +00:00
Jason W Kim	7342155b4c	Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage failures with relocations. The code committed is a first cut at compatibility for emitted relocations in ELF .o. Why do this? because existing ARM tools like emitting relocs symbols as explicit relocations, not as section-offset relocs. Result is that with these changes, 1) relocs are now substantially identical what to gcc outputs. 2) larger apps (including many spec2k tests) compile, cross-link, and pass Added reminder fixme to tests for future conversion to .s form. llvm-svn: 124996	2011-02-07 01:11:15 +00:00
Jason W Kim	056e5aacb7	Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to 5 to match the current doc. Added FIXME reminder Make it really configurable later. llvm-svn: 124899	2011-02-04 21:41:11 +00:00
Jason W Kim	10c1a81736	Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895	2011-02-04 19:47:15 +00:00
Evan Cheng	dc27913f2d	Fix test for non-darwin targets. llvm-svn: 124640	2011-02-01 01:16:18 +00:00
Bob Wilson	e7ac2389b2	PR9030: Fix disassembly of ARM "mov pc, lr" instruction. Patch by Jyun-Yan You. llvm-svn: 124492	2011-01-28 17:50:30 +00:00
Roman Divacky	c6a20d1728	Add support for parsing .float llvm-svn: 124485	2011-01-28 14:20:32 +00:00
Nico Weber	66fd0e8119	PR8951: Support for .equiv in integrated assembler, patch by Jörg Sonnenberger! llvm-svn: 124467	2011-01-28 03:04:41 +00:00
Evan Cheng	2042be8132	Fix PLD encoding. llvm-svn: 124458	2011-01-27 23:48:34 +00:00
Roman Divacky	f817c82cf3	Add support for specifying register name in cfi-register/offset/def as well as register number. llvm-svn: 124379	2011-01-27 17:16:37 +00:00
Bruno Cardoso Lopes	228d126d6f	Add encoding testcases for ARM vcvtr variations llvm-svn: 124289	2011-01-26 13:53:38 +00:00
Bruno Cardoso Lopes	2d6bd03b18	fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions llvm-svn: 124288	2011-01-26 13:28:14 +00:00
Rafael Espindola	f290466899	Jörg Sonnenberger noticed that we were missing this test. llvm-svn: 124139	2011-01-24 19:40:38 +00:00
Rafael Espindola	ead58a5259	Handle strings in section names the same way as gas: * If the name is a single string, we remove the quotes * If the name starts without a quote, we include any quotes in the name llvm-svn: 124127	2011-01-24 18:02:54 +00:00
Rafael Espindola	547873da60	Add support for the --noexecstack option. llvm-svn: 124077	2011-01-23 17:55:27 +00:00
Rafael Espindola	14333be1af	Add support for lowercase variants. llvm-svn: 124071	2011-01-23 16:11:25 +00:00
Rafael Espindola	aefd549139	Delay the creation of eh_frame so that the user can change the defaults. Add support for SHT_X86_64_UNWIND. llvm-svn: 124059	2011-01-23 05:43:40 +00:00
Bruno Cardoso Lopes	2f96371a7a	Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. llvm-svn: 123975	2011-01-21 14:07:40 +00:00
Bruno Cardoso Lopes	dc3853d7b5	Add testcases for clz encoding llvm-svn: 123937	2011-01-20 19:27:16 +00:00
Bruno Cardoso Lopes	6aeb2e320f	Fix the encoding and parsing of clrex instruction llvm-svn: 123936	2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes	5f06c0aa3b	Add cdp/cdp2 instructions for thumb/thumb2 llvm-svn: 123929	2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes	3584c02d83	- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927	2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes	75712e8a7a	Add mcr2 and mrc2 support to thumb2 targets llvm-svn: 123919	2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes	f377d1721e	Add mcr* and mr*c support to thumb targets llvm-svn: 123917	2011-01-20 16:35:57 +00:00
Bruno Cardoso Lopes	0f7a30b1cb	Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc llvm-svn: 123837	2011-01-19 16:56:52 +00:00
Owen Anderson	ed4acd59cb	When matching asm operands, always try to match the most restricted type first. Unfortunately, while this is the "right" thing to do, it breaks some ARM asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous. This is tricky to resolve since neither is a subset of the other. XFAIL the test for now. The old way was broken in other ways, just ways we didn't happen to be testing, and our ARM asm parsing is going to require significant revisiting at a later point anyways. llvm-svn: 123786	2011-01-18 23:01:21 +00:00
Bruno Cardoso Lopes	e0f8fee637	Create two new generic classes to represent the following VMRS/VMSR variations: vmrs reg, fpexc vmrs reg, fpsid vmsr fpexc, reg vmsr fpsid, reg llvm-svn: 123783	2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes	82c6fe3dfe	Fix MRS encoding for arm and thumb. llvm-svn: 123778	2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes	6e4c5af01e	Fix the encoding of t2ISB by using the right class and also parse it correctly llvm-svn: 123776	2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes	c1e21b06b9	Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. llvm-svn: 123772	2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes	94247155c4	Add support for parsing and encoding ARM's official syntax for the BFI instruction llvm-svn: 123770	2011-01-18 20:45:56 +00:00
Daniel Dunbar	ba39b2fdc1	McARM: Start marking T2 address operands as such, for the benefit of the parser. llvm-svn: 123722	2011-01-18 03:06:03 +00:00
Rafael Espindola	9afb7af08a	Update tests. llvm-svn: 123591	2011-01-16 18:02:57 +00:00
Evan Cheng	0cdd5547f1	Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. - Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first. - Added support for Thumb2 :lower16: and :upper16: fix up. - Added :upper16: and :lower16: relocation support to mach-o object writer. llvm-svn: 123424	2011-01-14 02:38:49 +00:00
Owen Anderson	4f5dac3541	As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends. llvm-svn: 123407	2011-01-13 22:38:16 +00:00
Evan Cheng	cc474b4864	Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369	2011-01-13 07:58:56 +00:00
Bill Wendling	e82361731d	Sort the register list based on the actual register numbers rather than the enum values we give to them. <rdar://problem/8823730> llvm-svn: 123321	2011-01-12 21:20:59 +00:00
Jason W Kim	ae183f9862	1. Support ELF pcrel relocations for movw/movt: R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. 3. Add support for 3 new elf section types (no-ops) llvm-svn: 123294	2011-01-12 00:19:25 +00:00
Jason W Kim	db6eddeea3	Workaround for bug 8721. .s Test added. llvm-svn: 123292	2011-01-11 23:53:41 +00:00
Chris Lattner	586e7af07d	Fix PR8946, a missing reg/reg form of movdqu. llvm-svn: 123242	2011-01-11 17:04:55 +00:00
Daniel Dunbar	fbc0b96c34	McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the carry setting flag from the mnemonic. Note that this currently involves me disabling a number of working cases in arm_instructions.s, this is a hopefully short term evil which will be rapidly fixed (and greatly surpassed), assuming my current approach flies. llvm-svn: 123238	2011-01-11 15:59:50 +00:00
Daniel Dunbar	0e9ece99bb	McARM: Flush out hard coded known non-predicated mnemonic list. llvm-svn: 123189	2011-01-10 21:01:03 +00:00
Rafael Espindola	64814fff0b	Correctly disassemble truncated asm. Patch by Richard Simth. llvm-svn: 122962	2011-01-06 16:48:42 +00:00
Evan Cheng	5f20fa7fed	Convert MC tests to .s so codegen changes won't break them. llvm-svn: 122786	2011-01-03 23:47:14 +00:00
Rafael Espindola	e223c0aa14	Fix PR8878. llvm-svn: 122658	2011-01-01 19:05:35 +00:00
Nick Lewycky	5cb84ee2cf	Add another non-commutable instruction that gas accepts commuted forms for. Fixes PR8861. llvm-svn: 122641	2010-12-30 22:10:49 +00:00
Daniel Dunbar	9ee74282a6	MC/Mach-O/Thumb: Set the thumb bit in the symbol table. llvm-svn: 122630	2010-12-29 14:14:06 +00:00
Rafael Espindola	7b1b3f5d82	Correctly encode pcrel\|indirect. llvm-svn: 122624	2010-12-29 04:31:26 +00:00
Rafael Espindola	0408a378e9	Fix bug when trying to output uint16_t or uint32_t. llvm-svn: 122615	2010-12-29 02:30:49 +00:00
Rafael Espindola	d51ed1fc6a	Implement cfi_def_cfa. Also don't convert to dwarf reg numbers twice. Looks like 6 is a fixed point of that and so the previous tests were OK :-) llvm-svn: 122614	2010-12-29 01:42:56 +00:00
Rafael Espindola	257de5c4a2	Implement cfi_def_cfa_register. llvm-svn: 122612	2010-12-29 00:26:06 +00:00
Rafael Espindola	061209eaf3	Initial .cfi_offset implementation. llvm-svn: 122611	2010-12-29 00:09:59 +00:00
Rafael Espindola	d93ec3572d	Don't produce a "DW_CFA_advance_loc 0". llvm-svn: 122609	2010-12-28 23:38:03 +00:00
Rafael Espindola	3fdd045643	Implement .cfi_remember_state and .cfi_restore_state. llvm-svn: 122602	2010-12-28 18:36:23 +00:00
Rafael Espindola	c97d642bf7	Relax address updates in the eh_frame section. llvm-svn: 122591	2010-12-28 05:39:27 +00:00
Rafael Espindola	0552cb0638	Start adding basic support for emitting the call frame instructions. llvm-svn: 122590	2010-12-28 04:15:37 +00:00
Rafael Espindola	12c30aed07	Add support for .cfi_lsda. llvm-svn: 122584	2010-12-27 15:56:22 +00:00
Daniel Dunbar	2d0cf8e149	MC/Mach-O/Thumb: Select appropriate relocation types for Thumb. llvm-svn: 122583	2010-12-27 14:49:49 +00:00
Rafael Espindola	7f947794d7	Handle reloc_riprel_4byte_movq_load. Should make the bots happy. llvm-svn: 122579	2010-12-27 02:03:24 +00:00
Rafael Espindola	e7e67fce10	Add support for the same encodings of the personality function that gnu as supports. llvm-svn: 122577	2010-12-27 00:36:05 +00:00
Rafael Espindola	2ebe553431	Add support for @note. Patch by Jörg Sonnenberger. llvm-svn: 122568	2010-12-26 21:30:59 +00:00
Rafael Espindola	99f1527316	Add basic support for .cfi_personality. llvm-svn: 122566	2010-12-26 20:20:31 +00:00
Chris Lattner	2129ce0891	Generalize a previous change, fixing PR8855 - an valid large immediate rejected by the mc assembler. llvm-svn: 122557	2010-12-25 21:36:35 +00:00
Daniel Dunbar	592854a10a	MC/Mach-O/ARM: Start handling some Thumb branches. llvm-svn: 122547	2010-12-24 16:41:46 +00:00
Kevin Enderby	ff7e68c5e7	In llvm-mc parse a Hash token as a full line comment. Allows handling of preprocessed .s files and matches darwin gas. rdar://8798690 Also fix a comment on the next line of AsmParser.cpp after this new code. llvm-svn: 122531	2010-12-24 00:12:02 +00:00
Daniel Dunbar	e6ec0e7149	MC/Mach-O/ARM: Don't try to use scattered relocs for BR24 fixups. llvm-svn: 122441	2010-12-22 21:26:43 +00:00
Rafael Espindola	5004de4d8b	Add reduced test from 8845. llvm-svn: 122438	2010-12-22 21:15:13 +00:00
Daniel Dunbar	cb8ac619a2	MC/Mach-O/ARM: We always use the SECTDIFF reloc type on ARM, which is esp. important given that the LOCAL_SECTDIFF enumeration got redefined. llvm-svn: 122412	2010-12-22 16:52:19 +00:00
Daniel Dunbar	e44a2c1166	MC/Mach-O/ARM: Add enough relocation logic to get BR24 relocations. llvm-svn: 122407	2010-12-22 16:19:24 +00:00
Rafael Espindola	7c995a90fc	Simplify the handling of .size expressions. llvm-svn: 122404	2010-12-22 16:03:00 +00:00
Wesley Peck	e8ec7a4d1f	Teach the MBlaze disassembler to disassemble special purpose registers. llvm-svn: 122269	2010-12-20 21:18:04 +00:00
Roman Divacky	42b3eee794	Set the value of absolute symbols. llvm-svn: 122268	2010-12-20 21:14:39 +00:00
Roman Divacky	13b5260f62	Print all 64bits for st_value and st_size. Adjust tests accordingly. llvm-svn: 122263	2010-12-20 20:49:43 +00:00
Wesley Peck	af2890a051	Teach the MBlaze asm parser how to parse special purpose register names. llvm-svn: 122261	2010-12-20 20:43:24 +00:00
Roman Divacky	ed5bb14415	Add support for lexing single quotes like 'c'. This fixed 8615. llvm-svn: 122150	2010-12-18 08:56:37 +00:00
Rafael Espindola	4c1b83e53f	Add a test that shows that we produce no fixups when computing the difference of two symbols in the same fragment. llvm-svn: 122145	2010-12-18 05:07:45 +00:00
Rafael Espindola	dff6c18a5e	Test for push being relaxed. llvm-svn: 122124	2010-12-18 01:16:59 +00:00
Daniel Dunbar	1f9fd0b79b	MC/Expr: Implemnt more aggressive folding during symbol evaluation using IsSymbolRefDifferenceFullyResolved(). For example, we will now fold away something like: -- _a: ... L0: ... L1: ... .long (L1 - L0) / 2 -- llvm-svn: 122043	2010-12-17 05:50:33 +00:00
Rafael Espindola	bd13ceed72	"Fix" FDE alignment to match what gas does. llvm-svn: 122006	2010-12-17 00:28:02 +00:00
Rafael Espindola	3ee4530406	Make pushq produce signed relocations. llvm-svn: 122005	2010-12-16 22:50:01 +00:00
Bob Wilson	438a9a1367	Add Neon VCVT instructions for f32 <-> f16 conversions. Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. llvm-svn: 121902	2010-12-15 22:14:12 +00:00
Bob Wilson	1082705e72	Fix misspelled target triples in MC/ARM test commands. llvm-svn: 121901	2010-12-15 22:14:01 +00:00
Rafael Espindola	94d026d157	Relax alignment fragments. With this we don't need the EffectiveSize field anymore. Without that field LayoutFragment only updates offsets and we don't need to invalidate the current fragment when it is relaxed (only the ones following it). This is also a very small improvement in the accuracy of the layout info as we now use the after relaxation size immediately. llvm-svn: 121857	2010-12-15 08:45:53 +00:00
Rafael Espindola	f55f520a7a	Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments. Since we now don't update addresses so early, we might relax a bit more than we need to. This is simillar to the issue in PR8467. llvm-svn: 121856	2010-12-15 07:39:29 +00:00
Kevin Enderby	6b3ae489f8	Add some more MC tests for ARM arithmetic instructions that update or don't update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830	2010-12-15 01:24:36 +00:00
Daniel Dunbar	3f9b9dc852	MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. llvm-svn: 121772	2010-12-14 17:37:16 +00:00
Rafael Espindola	0e665e502d	Fixed version of 121434 with no new memory leaks. llvm-svn: 121471	2010-12-10 07:39:47 +00:00
Rafael Espindola	011e168728	Revert my previous patch to make the valgrind bots happy. llvm-svn: 121461	2010-12-10 04:01:09 +00:00
Rafael Espindola	03ad1e8f1f	Initial support for the cfi directives. This is just enough to get f: .cfi_startproc nop .cfi_endproc assembled (on ELF). llvm-svn: 121434	2010-12-09 23:48:29 +00:00
Kevin Enderby	55cb19813e	Add support for parsing ARM arithmetic instructions that update or don't update the condition codes. Where the ones that do have an 's' suffix and the ones that don't don't have the suffix. The trick is if MatchInstructionImpl() fails we try again after adding a CCOut operand with the correct value and removing the 's' if present. Four simple test cases added for now, lots more to come. llvm-svn: 121401	2010-12-09 19:19:43 +00:00
Kevin Enderby	988dab6b5c	Allow a slash, '/', as a prefix separator for X86. rdar://8741045 llvm-svn: 121320	2010-12-08 23:57:59 +00:00
Rafael Espindola	866531d633	Fix absolute recording of differences of symbols in two sections. Reduced from ctor_dtor_count-2.cpp. llvm-svn: 121152	2010-12-07 17:12:32 +00:00
Rafael Espindola	da64b6aa50	Fix relocations with weak definitions. llvm-svn: 121114	2010-12-07 05:57:28 +00:00
Rafael Espindola	9ede5ef045	Fix pcrel relocations that cross sections. llvm-svn: 121107	2010-12-07 03:50:14 +00:00
Rafael Espindola	c98cc0b286	Fix a crash reduced from gcc produced assembly. llvm-svn: 121085	2010-12-07 01:09:54 +00:00
Owen Anderson	81f8b084e6	Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. llvm-svn: 121082	2010-12-07 00:45:21 +00:00
Rafael Espindola	3e954d16f4	Second try at making direct object emission produce the same results as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc bootstrap on darwin10 using darwin9's assembler and linker. llvm-svn: 121006	2010-12-06 17:27:56 +00:00
Rafael Espindola	f56c11276e	Don't use PadSectionToAlignment on windows. llvm-svn: 120978	2010-12-06 03:03:44 +00:00
Rafael Espindola	9215947c83	There are two reasons why we might want to use foo = a - b .long foo instead of just .long a - b First, on darwin9 64 bits the assembler produces the wrong result. Second, if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not consider a - b to be a constant but will if the dummy foo is created. Split how we handle these cases. The first one is something MC should take care of. The second one has to be handled by the caller. llvm-svn: 120889	2010-12-04 03:21:47 +00:00
Rafael Espindola	50b6170457	Next step: Only pad debug_line when the target is darwin. Add a FIXME to avoid doing that if the target is darwin10 or newer. This fixes ) Direct object emission was producing objects without the workaround on darwin9. ) Assembly printing was producing objects with the workaround on linux. llvm-svn: 120866	2010-12-04 00:31:13 +00:00
Jim Grosbach	8cef570ed9	Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order halfword being emitted to the stream first. rdar://8728174 llvm-svn: 120848	2010-12-03 22:31:40 +00:00
Jim Grosbach	c69ad2176a	When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 32-bit wide version by adding the .w suffix. llvm-svn: 120838	2010-12-03 20:33:01 +00:00
Rafael Espindola	16b64c646a	Rename temporary symbols if they conflict with artificial symbols created by the assembler. This was blocking parsing any large .s produced by clang for example. Fixes PR8596. llvm-svn: 120603	2010-12-01 20:46:11 +00:00
Owen Anderson	8802c68592	Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. llvm-svn: 120589	2010-12-01 19:18:46 +00:00
Owen Anderson	e2a8781847	Add tests for more forms of Thumb2 loads and stores. llvm-svn: 120436	2010-11-30 18:15:21 +00:00
Bill Wendling	ae920bcc50	Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. llvm-svn: 120408	2010-11-30 07:44:32 +00:00
Owen Anderson	b6e1c56c79	Correct Thumb2 encodings for a much wider range of loads and stores. llvm-svn: 120364	2010-11-30 00:14:31 +00:00
Owen Anderson	14abbb1a2e	Provide Thumb2 encodings for basic loads and stores. llvm-svn: 120340	2010-11-29 22:44:32 +00:00
Benjamin Kramer	84bf47f2d8	Fix some broken CHECK lines. llvm-svn: 120332	2010-11-29 22:34:55 +00:00
Bill Wendling	c0055893db	Add more Thumb encodings. llvm-svn: 120279	2010-11-29 01:07:48 +00:00
Bill Wendling	b54752da15	More Thumb encodings. llvm-svn: 120278	2010-11-29 01:00:43 +00:00
Bill Wendling	8f0b624061	Add Thumb encodings for REV instructions. llvm-svn: 120277	2010-11-29 00:42:50 +00:00
Bill Wendling	d233cab1eb	Add more Thumb encodings. llvm-svn: 120272	2010-11-29 00:18:15 +00:00
Chris Lattner	a11c5c5c32	fix PR8686, accepting a 'b' suffix at the end of all the setcc instructions. I choose to handle this with an asmparser hack, though it could be handled by changing all the instruction definitions to allow be "setneb" instead of "setne". The asm parser hack is better in this case, because we want the disassembler to produce setne, not setneb. llvm-svn: 120260	2010-11-28 20:23:50 +00:00
Rafael Espindola	6f5680f4a0	Implement the data16 prefix. llvm-svn: 120224	2010-11-27 20:29:45 +00:00
Daniel Dunbar	6153e5cd7b	macho-dump: Fix typo. llvm-svn: 120185	2010-11-27 04:00:06 +00:00
Rafael Espindola	e3dc1c951c	Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction. llvm-svn: 120147	2010-11-25 17:14:16 +00:00
Rafael Espindola	a8488b04e1	Factor some code to parseSectionFlags and fix the default type of a section. llvm-svn: 120145	2010-11-25 15:32:56 +00:00
Rafael Espindola	1a81f03f87	Behave a bit more like gnu as and use the symbol (instead of the section) for any relocation to a symbol defined in a tls section. llvm-svn: 120121	2010-11-24 21:57:39 +00:00
Rafael Espindola	97690e2d7d	Relocate with the symbol if the relocation is of kind NTPOFF. Patch by David Meyer, I added the test. llvm-svn: 120104	2010-11-24 19:23:50 +00:00
Rafael Espindola	81ecba9559	Fix and add tests for all cases in x86 and x86_64 where gnu as implicitly sets the type of a symbol to STT_TLS. llvm-svn: 120100	2010-11-24 18:51:21 +00:00
Rafael Espindola	38daba991e	Testcase for r120017. llvm-svn: 120099	2010-11-24 18:03:57 +00:00
Rafael Espindola	dc299d2615	If a symbol is used as tls, mark it as tls even if not declare as so. Probably fixes PR8659. llvm-svn: 120076	2010-11-24 02:19:40 +00:00
Rafael Espindola	6f069fc35f	Produce a relocation for pcrel absolute values. Based on a patch by David Meyer. llvm-svn: 120006	2010-11-23 07:20:12 +00:00
Bill Wendling	a472e7be70	Add encoding for ARM "trap" instruction. llvm-svn: 119938	2010-11-21 11:05:29 +00:00
Chris Lattner	4aaa7fbb98	implement PR8524, apparently mainline gas accepts movq as an alias for movd when transfering between i64 gprs and mmx regs. llvm-svn: 119931	2010-11-21 08:18:57 +00:00
Rafael Espindola	ee6aea622f	Handle PCRel relocations with absolute values. Fixes PR8656. llvm-svn: 119917	2010-11-21 00:48:25 +00:00
Kevin Enderby	214e641d8d	Added support for the Mach-O .symbol_resolver directive. rdar://8673046 llvm-svn: 119816	2010-11-19 18:39:33 +00:00
Bill Wendling	50a1812023	Add MC encodings for some Thumb instructions. Test for a few of them. The "bx lr" instruction cannot be tested just yet. It requires matching a "condition code", but adding one of those makes things go south quickly... llvm-svn: 119774	2010-11-19 01:33:10 +00:00
Bill Wendling	ef43273c51	Add support for parsing the writeback ("!") token. llvm-svn: 119761	2010-11-18 23:43:05 +00:00
Owen Anderson	c0d5d13769	More tests. llvm-svn: 119756	2010-11-18 23:30:10 +00:00
Owen Anderson	ca14474db4	Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2. llvm-svn: 119755	2010-11-18 23:29:56 +00:00
Owen Anderson	25dc3a4fe6	More Thumb2 encodings. llvm-svn: 119737	2010-11-18 21:15:19 +00:00
Owen Anderson	eec8c82d32	Fill out the set of Thumb2 multiplication operator encodings. llvm-svn: 119733	2010-11-18 20:32:18 +00:00
Owen Anderson	b7970b2c6a	Try again at providing Thumb2 encodings for basic multiplication operators. llvm-svn: 119601	2010-11-18 01:08:42 +00:00
Owen Anderson	e8906ba112	Revert r119593 while I figure out my testing disagrees with the buildbot. llvm-svn: 119597	2010-11-18 00:42:51 +00:00
Owen Anderson	47a64ab90c	Provide correct Thumb2 encodings for basic multiplication operators. llvm-svn: 119593	2010-11-18 00:19:10 +00:00
Wesley Peck	890a8357af	Now that the MBlaze backend is in its own directory, split the test cases into multiple files for different types of instructions. llvm-svn: 119580	2010-11-17 22:54:43 +00:00
Owen Anderson	ea6ac4cdff	Second attempt at correct encodings for Thumb2 bitfield instructions. llvm-svn: 119575	2010-11-17 22:16:31 +00:00
Owen Anderson	2adebbb603	Revert r119551, which broke buildbots. llvm-svn: 119555	2010-11-17 20:48:51 +00:00
Owen Anderson	c7750780fc	Provide Thumb2 encodings for bitfield instructions. llvm-svn: 119551	2010-11-17 20:35:29 +00:00
Owen Anderson	d88cfe5453	More miscellaneous Thumb2 encodings. llvm-svn: 119546	2010-11-17 19:57:38 +00:00
Rafael Espindola	b6fcca35a2	Add support for .int. llvm-svn: 119512	2010-11-17 16:24:40 +00:00
Rafael Espindola	9186952072	Add support for .2byte, .4byte and .8byte. Fixes PR8631. llvm-svn: 119511	2010-11-17 16:15:42 +00:00
Bill Wendling	f0a1acba8c	Proper encoding for VLDM and VSTM instructions. The register lists for these instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460	2010-11-17 04:32:08 +00:00
Rafael Espindola	47e7ef8c8f	A bit more of gnu as compatibility when handling relocations with aliases. llvm-svn: 119328	2010-11-16 04:11:46 +00:00
Bill Wendling	e15bf6b98d	Test encodings for LDM and STM. llvm-svn: 119315	2010-11-16 01:38:20 +00:00
Owen Anderson	686fae59e6	Add Thumb2 encodings for mov and friends. llvm-svn: 119295	2010-11-16 00:29:56 +00:00
Rafael Espindola	53a8ae85b7	Change the 11 byte nop to be a single instruction. llvm-svn: 119286	2010-11-15 23:10:30 +00:00
Owen Anderson	db1a4541c2	Provide Thumb2 encodings for sxtb and friends. llvm-svn: 119185	2010-11-15 21:12:05 +00:00
Owen Anderson	0bb2efeb7d	Add Thumb2 encodings for comparison and shift operators. llvm-svn: 119176	2010-11-15 19:58:36 +00:00
Owen Anderson	5ae5db8931	Add correct Thumb2 encodings for mvn and friends. llvm-svn: 119170	2010-11-15 18:45:17 +00:00
Rafael Espindola	1f6440b1e2	Change MCExpr::EvaluateAsRelocatableImpl of variables to return the original variable if recursing fails to simplify it. Factor AliasedSymbol to be a method of MCSymbol. Update MCAssembler::EvaluateFixup to match the change in EvaluateAsRelocatableImpl. Remove the WeakRefExpr hack, as the object writer now sees the weakref with no extra effort needed. Nothing else is using MCTargetExpr, but keep it for now. Now that the ELF writer sees relocations with aliases, handle .weak foo2 foo2: .weak bar2 .set bar2,foo2 .quad bar2 the same way gas does and produce a relocation with bar2. llvm-svn: 119152	2010-11-15 16:33:49 +00:00
Rafael Espindola	f6c0121c93	Fix PR8565. This moves most of the isUsed logic to the MCSymbol itself. With this we get a bit more relaxed about allowing definitions after uses: uses that don't evaluate their argument immediately (jmp foo) are accepted. ddunbar, this was the smallest compromise I could think of that lets us accept gcc (and clang!) assembly. llvm-svn: 119144	2010-11-15 14:40:36 +00:00
Rafael Espindola	5572cb1aed	Move the logic to decide with which symbol we produce a relocation (if any) to a central location. This also makes us a bit more compatible with gas. llvm-svn: 119094	2010-11-14 23:53:26 +00:00
Rafael Espindola	59a93284d7	Fix another case of a .comm directive without a corresponding .type directive. llvm-svn: 119073	2010-11-14 21:11:16 +00:00
Rafael Espindola	1884e6d475	Fix the type of a symbol created with .comm and no corresponding .type. llvm-svn: 119060	2010-11-14 19:40:55 +00:00
Dale Johannesen	05a7c613fa	Segregate tests by target. llvm-svn: 119050	2010-11-14 18:14:32 +00:00
Rafael Espindola	444d9c0b02	Handle a peculiar comdat case: Creating a section with an undefined signature symbol causes a local symbol to be created unless there is some other use of the symbol. llvm-svn: 119026	2010-11-14 04:17:37 +00:00
Wesley Peck	4a2644f203	Fixed error and re-enabled MBlaze MC disassembler tests. llvm-svn: 118987	2010-11-13 05:48:21 +00:00
Rafael Espindola	9cd0fd30e0	Parse and record the gnu_unique_object type. llvm-svn: 118980	2010-11-13 04:51:02 +00:00
Dale Johannesen	7a2e75185a	This test stops after disassembling 1 instructions on darwin and, judging from the buildbots, Linux. Removing it for now, but this is not the right fix, Wesley please look at it. llvm-svn: 118977	2010-11-13 03:55:04 +00:00
Rafael Espindola	00c5605efc	Parse and remember discriminators in .loc line. I try to output them with another patch. This lets us parse a bit more of the gcc 4.5 output. llvm-svn: 118975	2010-11-13 03:18:27 +00:00
Wesley Peck	5c8b28f1fe	Add test cases that should have been committed with 118969. llvm-svn: 118974	2010-11-13 02:51:00 +00:00
Wesley Peck	c534d55751	1. Adding test cases for MBlaze MC disassembler. 2. Fixing several errors in disassembler uncovered by test cases. 3. Fixing invalid encoding of PCMPEQ and PCMPNE uncovered by test cases. llvm-svn: 118969	2010-11-13 02:37:59 +00:00
Rafael Espindola	e296fd654b	Fix the encoding of negative line deltas. llvm-svn: 118962	2010-11-13 01:06:27 +00:00
Wesley Peck	28f124b047	1. Adding missing immediate mode asm parser test cases. 2. Fixing improper immediate mode reverse subtract. llvm-svn: 118948	2010-11-13 00:03:46 +00:00
Wesley Peck	f11db049fe	Fixing improperly encoded reverse subtract instructions in MBlaze backend. llvm-svn: 118943	2010-11-12 23:41:10 +00:00
Wesley Peck	be71f5db40	1. Finishing MBlaze MC asm parser test cases 2. Parsing .word directive in MBlaze asm parser 3. Fixing hack where memory instructions reversed order of last two parameters 4. Fixing many improperly encoded instructions 5. Support parsing special instructions (MFS,MTS,etc.) 6. Removing unused functions from inst printer llvm-svn: 118941	2010-11-12 23:30:17 +00:00
Owen Anderson	f1ffc8fdc9	First stab at providing correct Thumb2 encodings, start with adc. llvm-svn: 118924	2010-11-12 21:12:40 +00:00
Chris Lattner	2a70c4e38a	accept lret as an alias for lretl, fixing the reopened part of PR8592 llvm-svn: 118916	2010-11-12 18:54:56 +00:00
Chris Lattner	612039e538	implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix. llvm-svn: 118903	2010-11-12 17:41:20 +00:00
Rafael Espindola	dc54b2b285	gnu as support both % and @ before types, do the same. llvm-svn: 118893	2010-11-12 15:47:08 +00:00
Owen Anderson	85cf1b8ff5	Fill out support for Thumb2 encodings of NEON instructions. llvm-svn: 118854	2010-11-11 23:12:55 +00:00
Wesley Peck	0e937ae80d	Fix tblgen instruction errors exposed by MC asm parser tests Fix minimum 16-bit signed value error exposed by MC asm parser tests Add initial MC asm parser tests for the MBlaze backend llvm-svn: 118844	2010-11-11 21:40:53 +00:00
Owen Anderson	0913dac245	Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. llvm-svn: 118843	2010-11-11 21:36:43 +00:00
Owen Anderson	7fda1a6efd	Flesh out tests for Thumb2 encodings of NEON instructions. llvm-svn: 118837	2010-11-11 21:15:47 +00:00
Owen Anderson	f43f09f6f6	Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. More tests to come. llvm-svn: 118819	2010-11-11 19:07:48 +00:00
Rafael Espindola	1725702868	Mark labels declared in tls sections as STT_TLS. This matches the behavior of gas. llvm-svn: 118818	2010-11-11 19:04:55 +00:00
Rafael Espindola	8555d32c9e	Initial comdat implementation. llvm-svn: 118805	2010-11-11 18:13:52 +00:00
Rafael Espindola	f7b3bb84e8	Make AliasedSymbol able to handle MCTargetExpr. They can get here if a weakref is used with a VariantKind. llvm-svn: 118798	2010-11-11 17:24:43 +00:00
Rafael Espindola	f1ee36c3a3	Fix the symbol index of weak references. Also make RecordRelocation a bit easier to read by having const references to the symbol, aliased symbol and renamed symbol. llvm-svn: 118793	2010-11-11 16:48:11 +00:00
Owen Anderson	52e3873edc	Add support for ARM's specialized vector-compare-against-zero instructions. llvm-svn: 118453	2010-11-08 23:21:22 +00:00
Rafael Espindola	1602d991d5	Set default flags for .rodata. llvm-svn: 118395	2010-11-08 02:47:59 +00:00
Rafael Espindola	877bb5ba4b	Relax dwarf line fragments. This fixes a crash in the included testcase. llvm-svn: 118365	2010-11-07 02:07:12 +00:00
Chris Lattner	24ba201941	implement aliases for div/idiv that have an explicit A register operand, implementing rdar://8431864 llvm-svn: 118364	2010-11-06 22:41:18 +00:00
Chris Lattner	25f31dcc8f	add aliases for movs between seg registers and mem. There are multiple different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 llvm-svn: 118362	2010-11-06 22:35:34 +00:00
Chris Lattner	0d6d870628	go to great lengths to work around a GAS bug my previous patch exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. llvm-svn: 118356	2010-11-06 21:37:06 +00:00
Chris Lattner	bbd318b76a	rework the rotate-by-1 instructions to be defined like the shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355	2010-11-06 21:23:40 +00:00
Chris Lattner	af1f50772a	change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354	2010-11-06 20:55:09 +00:00
Chris Lattner	1beb2b3fc5	correct suffix matching to search for s/l/t suffixes on floating point stack instructions instead of looking for b/w/l/q. This fixes issues where we'd accidentally match fistp to fistpl, when it is in fact an ambiguous instruction. This changes the behavior of llvm-mc to reject fstp, which was the correct fix for rdar://8456389: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) it also causes us to correctly reject fistp and fist, which addresses PR8528: t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks to Ismail Donmez for tracking down the issue here! llvm-svn: 118346	2010-11-06 18:28:02 +00:00
Owen Anderson	add19dd6dd	Add codegen and encoding support for the immediate form of vbic. llvm-svn: 118291	2010-11-05 19:27:46 +00:00
Bill Wendling	990c247994	Add encoding for VSTR. llvm-svn: 118220	2010-11-04 00:59:42 +00:00
Owen Anderson	d144bb1ddc	Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. This is both the conceptually correct place for it, as well as allowing it to be more aggressive. llvm-svn: 118204	2010-11-03 23:15:26 +00:00
Owen Anderson	1a89511e5d	Add support for code generation of the one register with immediate form of vorr. We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. llvm-svn: 118201	2010-11-03 22:44:51 +00:00
Owen Anderson	98f9965c89	Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with the immediate shifted left to reflect the increased element size. llvm-svn: 118183	2010-11-03 18:16:27 +00:00
Bill Wendling	34599f4aa8	The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144	2010-11-03 01:49:29 +00:00
Chris Lattner	5bf66af7ed	chase owen. llvm-svn: 118124	2010-11-02 23:55:24 +00:00
Chris Lattner	e6e3c0e4cf	tweak this to pass. llvm-svn: 118122	2010-11-02 23:50:17 +00:00
Chris Lattner	0cfbc490da	temporarily xfail this. llvm-svn: 118120	2010-11-02 23:44:50 +00:00
Bill Wendling	1546322a9c	Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094	2010-11-02 22:31:46 +00:00
Owen Anderson	cdd587157f	Provide correct encodings for the remaining vst variants that we currently generate. llvm-svn: 118087	2010-11-02 22:18:18 +00:00
Owen Anderson	46d4ab1a87	Add correct encodings for basic variants for vst3 and vst4. llvm-svn: 118082	2010-11-02 21:47:03 +00:00
Owen Anderson	36d5c04fbd	Add correct encodings for the basic variants for vst2. llvm-svn: 118068	2010-11-02 21:16:58 +00:00
Owen Anderson	c9f6909c96	Add correct encodings for the basic form of vst1. llvm-svn: 118067	2010-11-02 21:06:06 +00:00
Owen Anderson	ee1337c01f	Add correct encodings for the rest of the vld instructions that we generate. llvm-svn: 118053	2010-11-02 20:40:59 +00:00
Rafael Espindola	1db6a21aff	Add support for expressions in .sleb/.uleb directives. llvm-svn: 118023	2010-11-02 17:22:24 +00:00
Owen Anderson	9d85c89ade	Add correct NEON encodings for vld2, vld3, and vld4 basic variants. llvm-svn: 117997	2010-11-02 01:24:55 +00:00

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1570 Commits