1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Commit Graph

3196 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
c07fd51d56 Avoid allocating the same physreg to multiple virtregs in one instruction.
While that approach works wonders for register pressure, it tends to break
everything.

This should unbreak the arm-linux builder and fix a number of miscompilations.

llvm-svn: 103946
2010-05-17 17:18:59 +00:00
Jakob Stoklund Olesen
40545bf117 Only use clairvoyance when defining a register, and then only if it has one use.
This makes allocation independent on the ordering of use-def chains.

llvm-svn: 103935
2010-05-17 04:50:57 +00:00
Dale Johannesen
b71d6a4150 Removing as part of previous reversion.
llvm-svn: 103915
2010-05-16 20:19:40 +00:00
Dale Johannesen
cf2d4b9f91 Revert 103911; it broke a test that expects bitconvert
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine).  The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.

llvm-svn: 103914
2010-05-16 20:19:04 +00:00
Dale Johannesen
15dce10b5a Make x86-64 64-bit bitconvert work when SSE is not available.
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)

llvm-svn: 103911
2010-05-16 18:22:38 +00:00
Anton Korobeynikov
925a32ae37 Add support for thiscall calling convention.
Patch by Charles Davis and Steven Watanabe!

llvm-svn: 103902
2010-05-16 09:08:45 +00:00
Anton Korobeynikov
314ccc5501 Some cheap DAG combine goodness for multiplication with a particular constant.
This can be extended later on to handle more "complex" constants.

llvm-svn: 103881
2010-05-15 18:16:59 +00:00
Evan Cheng
85497bd415 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
2010-05-15 02:18:07 +00:00
Bill Wendling
5fde821884 SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)

llvm-svn: 103829
2010-05-14 22:17:42 +00:00
Jakob Stoklund Olesen
3eac02b22f Simplify the handling of physreg defs and uses in RegAllocFast.
This adds extra security against using clobbered physregs, and it adds kill
markers to physreg uses.

llvm-svn: 103784
2010-05-14 18:03:25 +00:00
Jakob Stoklund Olesen
d99818256c Take allocation hints from copy instructions to/from physregs.
This causes way more identity copies to be generated, ripe for coalescing.

llvm-svn: 103686
2010-05-13 00:19:43 +00:00
Jakob Stoklund Olesen
7d1323d9a5 Make sure to add kill flags to the last use of a virtreg when it is redefined.
The X86 floating point stack pass and others depend on good kill flags.

llvm-svn: 103635
2010-05-12 18:46:03 +00:00
Jakob Stoklund Olesen
6976c543cd Enable a bunch more -regalloc=fast tests
llvm-svn: 103531
2010-05-12 00:11:24 +00:00
Jakob Stoklund Olesen
063844f706 Keep track of the last place a live virtreg was used.
This allows us to add accurate kill markers, something the scavenger likes.
Add some more tests from ARM that needed this.

llvm-svn: 103521
2010-05-11 23:24:45 +00:00
Jakob Stoklund Olesen
99d5d74fb0 One more -regalloc=fast test
llvm-svn: 103509
2010-05-11 20:51:07 +00:00
Jakob Stoklund Olesen
e27902ac68 Simplify the tracking of used physregs to a bulk bitor followed by a transitive
closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

llvm-svn: 103500
2010-05-11 20:30:28 +00:00
Jakob Stoklund Olesen
442e38c4de Mostly rewrite RegAllocFast.
Sorry for the big change. The path leading up to this patch had some TableGen
changes that I didn't want to commit before I knew they were useful. They
weren't, and this version does not need them.

The fast register allocator now does no liveness calculations. Instead it relies
on kill flags provided by isel. (Currently those kill flags are also ignored due
to isel bugs). The allocation algorithm is supposed to work with any subset of
valid kill flags. More kill flags simply means fewer spills inserted.

Registers are allocated from a working set that contains no aliases. That means
most allocations can be done directly without expensive alias checks. When the
working set runs out of registers we do the full alias check to find new free
registers.

llvm-svn: 103488
2010-05-11 18:54:45 +00:00
Kalle Raiskila
e302300b51 Make SPU backend not assert on jump tables.
llvm-svn: 103466
2010-05-11 11:00:02 +00:00
Evan Cheng
11130a0a22 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
llvm-svn: 103459
2010-05-11 07:26:32 +00:00
Evan Cheng
df350445c6 Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869.
llvm-svn: 103419
2010-05-10 19:03:57 +00:00
Kalle Raiskila
61289abcda Fix encoding of 'sf' and 'sfh' instructions.
llvm-svn: 103399
2010-05-10 08:13:49 +00:00
Bill Wendling
787de8fe38 Readd testcase.
llvm-svn: 103335
2010-05-08 04:47:54 +00:00
Dan Gohman
4ca74b9c6c When pruning candidate formulae out of an LSRUse, update the
LSRUse's Regs set after all pruning is done, rather than trying
to do it on the fly, which can produce an incomplete result.

This fixes a case where heuristic pruning was stripping all
formulae from a use, which led the solver to enter an infinite
loop.

Also, add a few asserts to diagnose this kind of situation.

llvm-svn: 103328
2010-05-07 23:36:59 +00:00
Bill Wendling
4241941b52 Remove. Don't XFAIL.
llvm-svn: 103321
2010-05-07 23:09:17 +00:00
Bill Wendling
3846ec7889 Temorarily revert r101984.
llvm-svn: 103314
2010-05-07 22:45:36 +00:00
Dan Gohman
95040c18f4 SDDbgValues are apparently not being legalized. Fix a symptom of the problem,
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.

llvm-svn: 103310
2010-05-07 22:19:08 +00:00
Dale Johannesen
1ee37ac5d4 Fix PR 7087, and probably other things, by extending
getConstantFP to accept the two supported long double
target types.  This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.

llvm-svn: 103299
2010-05-07 21:35:53 +00:00
Jim Grosbach
2db1618b44 Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
2010-05-07 18:34:55 +00:00
Duncan Sands
ed2ef5a987 Correct some bogus target triples.
llvm-svn: 103265
2010-05-07 17:03:48 +00:00
Nick Lewycky
3e5720a898 Revert r103133 and add testcase from PR7066.
llvm-svn: 103233
2010-05-07 01:45:38 +00:00
Dan Gohman
f863ad3dc5 Disable the new unknown-location code for now. It causes a major
increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226
2010-05-07 01:08:53 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.

llvm-svn: 103194
2010-05-06 20:33:48 +00:00
Dan Gohman
3190e5c292 Add a testcase for r103135, explicitly representing unknown
locations in debug line info.

llvm-svn: 103189
2010-05-06 17:49:17 +00:00
Chris Lattner
014a954e3d Fix PR7054 - Assertion `Symbol->isUndefined() && "Cannot define a symbol twice!"' failed.
Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.

llvm-svn: 103140
2010-05-06 00:05:37 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
2010-05-05 23:44:43 +00:00
Jakob Stoklund Olesen
2e5d12acfa Fix PR6520. An earlyclobber physreg must not be allocated to anything else.
llvm-svn: 103133
2010-05-05 23:07:41 +00:00
Jim Grosbach
7eb0b4d646 fix copy/paste oops.
llvm-svn: 103122
2010-05-05 21:07:46 +00:00
Jim Grosbach
25fc725b2a Add tests for ARMV7M divide instruction use
llvm-svn: 103120
2010-05-05 20:47:15 +00:00
Jim Grosbach
9b7ae2027f remove unneeded underscores.
llvm-svn: 103114
2010-05-05 19:55:58 +00:00
Jim Grosbach
7ea67d346f Convert to filecheck
llvm-svn: 103113
2010-05-05 19:41:11 +00:00
Chris Lattner
b4696853af "on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."
Patch by Kalle Raiskila!

llvm-svn: 103021
2010-05-04 17:58:46 +00:00
Dale Johannesen
b10ca6bf4c Implement builtin_return_address(x) and builtin_frame_address(x)
on PPC for x!=0.  7624113.

llvm-svn: 102972
2010-05-03 22:59:34 +00:00
Jakob Stoklund Olesen
51ab2653d5 Check that subregisters don't have independent values in RemoveCopyByCommutingDef().
This fixes PR6941.

llvm-svn: 102970
2010-05-03 22:40:32 +00:00
Dan Gohman
c024fd43c9 Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
when the type is floating-point.

llvm-svn: 102969
2010-05-03 22:36:46 +00:00
Dan Gohman
15cb983f55 Fix a bug which prevented tail merging of return instructions in
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.

The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.

Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.

And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.

llvm-svn: 102907
2010-05-03 14:35:47 +00:00
Duncan Sands
153ad3b903 Remove the -enable-sjlj-eh option, which doesn't do anything.
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.

llvm-svn: 102865
2010-05-02 15:36:26 +00:00
Anton Korobeynikov
a3726088fa Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),
when needed. This fixes PR7001

llvm-svn: 102838
2010-05-01 12:52:34 +00:00
Anton Korobeynikov
f31181a0cc Do folding for indirect branches, where possible
llvm-svn: 102836
2010-05-01 12:28:21 +00:00
Anton Korobeynikov
9b724bd446 Implement indirect branches on MSP430
llvm-svn: 102835
2010-05-01 12:04:32 +00:00
Bill Wendling
7b6527b94b Test failing too much on too many platforms.
llvm-svn: 102812
2010-05-01 00:12:33 +00:00