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Author SHA1 Message Date
Chris Lattner
93820f4ad7 Consolidate the GPOpt stuff to all use the Subtarget, instead of still 
depending on the command line option.  Now the command line option just
sets the subtarget as appropriate.  G5 opts will now default to on on
G5-enabled nightly testers among other machines.

llvm-svn: 22688
 2005-08-05 22:05:03 +00:00
Chris Lattner
79095d3416 Enable gp optimizations by default when available, even when a target triple 
is available, since the target triple doesn't specify whether to use gpopts
or not.

llvm-svn: 22685
 2005-08-05 21:25:13 +00:00
Chris Lattner
d82395fc04 add a note 
llvm-svn: 22681
 2005-08-05 19:18:32 +00:00
Chris Lattner
852038daec don't crash when running the PPC backend on non-ppc hosts without specifying 
a subtarget.

llvm-svn: 22677
 2005-08-05 16:17:22 +00:00
Nate Begeman
c76ffa6717 Hack to naturally align doubles in the constant pool. Remove this once we 
know what The Right Thing To Do is.

llvm-svn: 22660
 2005-08-04 21:04:09 +00:00
Nate Begeman
84d0a2806a Use the new subtarget support to automatically choose the correct ABI 
and asm printer for PowerPC if one is not specified.

llvm-svn: 22659
 2005-08-04 20:49:48 +00:00
Nate Begeman
09997f1012 Add Subtarget support to PowerPC. Next up, using it. 
llvm-svn: 22644
 2005-08-04 07:12:09 +00:00
Misha Brukman
41a00bbfa6 Fix grammar: apostrophe-s ('s) is possessive, not plural; also iff vs. if. 
llvm-svn: 22619
 2005-08-03 17:29:52 +00:00
Chris Lattner
adfe9f12ef minor capitalization thing, patch by Jim Laskey 
llvm-svn: 22617
 2005-08-03 16:52:22 +00:00
Chris Lattner
75a8a64de4 This hunk accidentally got dropped. Patch by Jim Laskey 
llvm-svn: 22595
 2005-08-02 19:30:55 +00:00
Chris Lattner
cc8ae687e1 Update to use the new MathExtras.h support for log2 computation. 
Patch contributed by Jim Laskey!

llvm-svn: 22594
 2005-08-02 19:26:06 +00:00
Chris Lattner
3a81e0795b add a pass name to make debugging dumps nicer 
llvm-svn: 22588
 2005-08-02 19:07:49 +00:00
Jeff Cohen
019104459d Keep tabs and trailing spaces out. 
llvm-svn: 22565
 2005-07-30 18:33:25 +00:00
Andrew Lenharth
3a7dc9f0bd turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) 
llvm-svn: 22553
 2005-07-29 23:32:02 +00:00
Chris Lattner
5d02e3a15e Eliminate an extra copy from R1 that Nate noticed on function calls that 
have to write arguments to the stack

llvm-svn: 22536
 2005-07-28 05:23:43 +00:00
Chris Lattner
a9dac1cd7a Specify the correct number of operands 
llvm-svn: 22535
 2005-07-28 04:42:11 +00:00
Nate Begeman
b125feb99f Fold constant adds into loads and stores to frame indices. 
For the following code:
double %ext(int %A.0__, long %A.1__) {
        %A_addr = alloca %typedef.DComplex              ; <%typedef.DComplex*> [#uses=2]
        %tmp.1 = cast %typedef.DComplex* %A_addr to int*                ; <int*> [#uses=1]
        store int %A.0__, int* %tmp.1
        %tmp.2 = getelementptr %typedef.DComplex* %A_addr, int 0, uint 1                ; <double*> [#uses=2]
        %tmp.3 = cast double* %tmp.2 to long*           ; <long*> [#uses=1]
        store long %A.1__, long* %tmp.3
        %tmp.5 = load double* %tmp.2            ; <double> [#uses=1]
        ret double %tmp.5
}

We now generate:
_ext:
.LBB_ext_0:     ;
        stw r3, -12(r1)
        stw r4, -8(r1)
        stw r5, -4(r1)
        lfd f1, -8(r1)
        blr

Instead of:
_ext:
.LBB_ext_0:     ;
        stw r3, -12(r1)
        addi r2, r1, -12
        stw r4, 4(r2)
        stw r5, 8(r2)
        lfd f1, 4(r2)
        blr

This also fires hundreds of times on MultiSource.

llvm-svn: 22533
 2005-07-28 03:02:05 +00:00
Nate Begeman
d230bf7242 Fix some comments 
llvm-svn: 22530
 2005-07-27 23:11:27 +00:00
Jeff Cohen
bd51ec7461 Eliminate all remaining tabs and trailing spaces. 
llvm-svn: 22523
 2005-07-27 06:12:32 +00:00
Nate Begeman
54792213a7 Implement the optimization for the Red Zone on Darwin. This removes the 
unnecessary SP manipulation in leaf routines that don't need it.

llvm-svn: 22522
 2005-07-27 06:06:29 +00:00
Jeff Cohen
81980781a1 Eliminate tabs and trailing spaces. 
llvm-svn: 22520
 2005-07-27 05:53:44 +00:00
Chris Lattner
9c98c4366a add a note about the red zone 
llvm-svn: 22518
 2005-07-26 19:07:51 +00:00
Chris Lattner
2e2dd83e7d Wrap some long lines, fix emission of weak global variables 
llvm-svn: 22517
 2005-07-26 19:03:27 +00:00
Nate Begeman
cd48821a69 Update the PPC readme 
llvm-svn: 22516
 2005-07-26 18:59:06 +00:00
Nate Begeman
19014db53f Fix an optimization put in for accessing static globals. This obviates 
the need to build PIC.

llvm-svn: 22512
 2005-07-25 21:15:28 +00:00
Chris Lattner
dd14de5a1e PowerPC no-pic code is not quite ready for prime-time 
llvm-svn: 22507
 2005-07-22 22:58:34 +00:00
Andrew Lenharth
0e1c0e7c79 update interface 
llvm-svn: 22498
 2005-07-22 20:49:37 +00:00
Nate Begeman
7259cc60c4 Support building non-PIC 
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.

llvm-svn: 22494
 2005-07-21 20:44:43 +00:00
Chris Lattner
1766305e60 revert to using 4-byte alignment for doubles, as specified by the ABI 
llvm-svn: 22493
 2005-07-21 19:17:18 +00:00
Nate Begeman
95421ab212 Support assembling fsqrt on darwin. This will be implemented better when 
PowerPC gets subtarget support up.

llvm-svn: 22489
 2005-07-21 01:25:49 +00:00
Nate Begeman
ae843fcefe Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5. 
8-byte align doubles.

llvm-svn: 22486
 2005-07-20 22:42:00 +00:00
Nate Begeman
b83789d611 Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being 
automatically generated from a target description.

llvm-svn: 22470
 2005-07-19 16:51:05 +00:00
Nate Begeman
be4b78ff53 Remove some code that moved to the generic asm printer a long time ago. 
llvm-svn: 22407
 2005-07-12 18:34:15 +00:00
Chris Lattner
ffaf40a143 Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode. 
This is the last MVTSDNode.

This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.

Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).

llvm-svn: 22368
 2005-07-10 01:56:13 +00:00
Chris Lattner
273b81e0c0 Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode 
llvm-svn: 22366
 2005-07-10 00:29:18 +00:00
Nate Begeman
70532b9f00 Add support for assembling .s files on mac os x for intel 
Add support for running bugpoint on mac os x for intel

llvm-svn: 22351
 2005-07-08 00:23:26 +00:00
Chris Lattner
199560c668 Make several cleanups to Andrews varargs change: 
1. Pass Value*'s into lowering methods so that the proper pointers can be
   added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
   chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
4. Now that we have Value*'s available in the lowering methods, pass them
   into any load/stores from the valist that are emitted

llvm-svn: 22339
 2005-07-05 19:58:54 +00:00
Chris Lattner
23a1b681d0 Fix PowerPC varargs 
llvm-svn: 22335
 2005-07-05 17:48:31 +00:00
Chris Lattner
6a865d5a22 Varargs is apparently currently broken on PPC. This hacks it so that it 
is at least overloading the right virtual methods.  The implementations
are currently wrong though.  This fixes Ptrdist/bc, but not other programs
(e.g. siod).

llvm-svn: 22326
 2005-07-01 23:11:56 +00:00
Chris Lattner
06282f51cf Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile 
interface.

llvm-svn: 22282
 2005-06-25 02:48:37 +00:00
Andrew Lenharth
4fd2bde906 If we support structs as va_list, we must pass pointers to them to va_copy 
See last commit for LangRef, this implements it on all targets.

llvm-svn: 22273
 2005-06-22 21:04:42 +00:00
Andrew Lenharth
a9214fec08 core changes for varargs 
llvm-svn: 22254
 2005-06-18 18:34:52 +00:00
Reid Spencer
678c9a3b00 Clean up some uninitialized variables and missing return statements that 
GCC 4.0.0 compiler (sometimes incorrectly) warns about under release build.

llvm-svn: 22249
 2005-06-18 17:37:34 +00:00
Chris Lattner
70914ca850 silence incredibly braindead GCC 4 warning 
llvm-svn: 22246
 2005-06-17 13:44:07 +00:00
Nate Begeman
12cd2d8d99 Commit fix for generating conditional branch pseudo instructions that 
avoids dereferencing the end() iterator when selecting the fallthrough
block.  This requires an ilist change.

llvm-svn: 22212
 2005-06-15 18:22:43 +00:00
Nate Begeman
9bb1be2eec Commit a small improvement that is already in the x86 and ia64 backends to 
not generate unnecessary register copies.  This improves compile time by
2-5% depending on the test.

llvm-svn: 22210
 2005-06-14 03:55:23 +00:00
Nate Begeman
f516b866e5 Fix a memory smasher caught by Mac OS X's debug malloc library. We were 
incorrectly using an iterator after it was invalid.

llvm-svn: 22207
 2005-06-12 23:50:33 +00:00
Reid Spencer
a88b91d681 For PR572: 
Undefine the PPC symbol which is defined by Linux/PPC (erroneously) so it
doesn't pollute the user namespace and clash with our namespace declarations.

llvm-svn: 22202
 2005-06-08 17:44:48 +00:00
Nate Begeman
47cd13d42a Handle some more real world cases of rlwimi. These don't come up that 
regularly in "normal" code, but for things like software graphics, they
make a big difference.

For the following code:
unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha)
{
	unsigned tmpA,tmpB,mixed;
	tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F);
	tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F);
	mixed = (tmpA * alpha) + (tmpB * (32 - alpha));
	return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0);
}

We now generate:
_Trans16Bit:
.LBB_Trans16Bit_0:      ; entry
        andi. r2, r4, 31775
        rlwimi r2, r4, 15, 7, 11
        subfic r4, r5, 32
        mullw r2, r2, r4
        andi. r4, r3, 31775
        rlwimi r4, r3, 15, 7, 11
        mullw r3, r4, r5
        add r2, r2, r3
        srwi r3, r2, 5
        andi. r3, r3, 31775
        rlwimi r3, r2, 12, 22, 26
        blr

Instead of:
_Trans16Bit:
.LBB_Trans16Bit_0:      ; entry
        slwi r2, r4, 15
        rlwinm r2, r2, 0, 7, 11
        andi. r4, r4, 31775
        or r2, r2, r4
        subfic r4, r5, 32
        mullw r2, r2, r4
        slwi r4, r3, 15
        rlwinm r4, r4, 0, 7, 11
        andi. r3, r3, 31775
        or r3, r4, r3
        mullw r3, r3, r5
        add r2, r2, r3
        srwi r3, r2, 5
        andi. r3, r3, 31775
        srwi r2, r2, 20
        rlwimi r3, r2, 0, 22, 26
        blr

llvm-svn: 22201
 2005-06-08 04:14:27 +00:00
Chris Lattner
0366a913ad PPC "branch and link" instructions are branches in the PPC sense, but not 
in the LLVM code generator sense (they are calls).  Don't mark them as such,
which fixes the regressions on the ppc tester last night

llvm-svn: 22065
 2005-05-15 20:11:44 +00:00
Chris Lattner
9fc81f1162 Fix andrews changes to fit in 80 columns 
llvm-svn: 22064
 2005-05-15 19:54:37 +00:00
Chris Lattner
93007dda7d treat TAILCALL nodes identically to CALL nodes 
llvm-svn: 21977
 2005-05-13 20:29:26 +00:00
Chris Lattner
9d788e93a6 Add an isTailCall flag to LowerCallTo 
llvm-svn: 21958
 2005-05-13 18:50:42 +00:00
Chris Lattner
f8795289ff Realize that we don't support fmod directly, fixing CodeGen/Generic/print-arith-fp.ll 
llvm-svn: 21939
 2005-05-13 16:20:22 +00:00
Chris Lattner
094bbfcebb rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN. 
llvm-svn: 21915
 2005-05-12 23:24:06 +00:00
Chris Lattner
7e08dd591c Pass in Calling Convention to use into LowerCallTo 
llvm-svn: 21899
 2005-05-12 19:56:45 +00:00
Chris Lattner
6b0a45e42c These targets don't like setcc 
llvm-svn: 21884
 2005-05-12 02:06:00 +00:00
Nate Begeman
e84f776b5d Necessary changes to codegen cttz efficiently on PowerPC 
1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have
   CTPOP, but does have CTLZ
2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts
3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a
4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW

llvm-svn: 21880
 2005-05-11 23:43:56 +00:00
Chris Lattner
333ae3d837 fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible, 
include and (srl)    and the inverses (shl and) etc.

llvm-svn: 21820
 2005-05-09 17:39:48 +00:00
Andrew Lenharth
8e2beec4d1 fix typo 
llvm-svn: 21693
 2005-05-04 19:25:37 +00:00
Andrew Lenharth
8b64bd0fd5 Implement count leading zeros (ctlz), count trailing zeros (cttz), and count 
population (ctpop).  Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.

More coming soon.

llvm-svn: 21676
 2005-05-03 17:19:30 +00:00
Chris Lattner
b0af0dd919 Doesn't support these nodes 
llvm-svn: 21634
 2005-04-30 04:26:56 +00:00
Chris Lattner
ce0d8c2408 This target doesn't support the FSIN/FCOS/FSQRT nodes yet 
llvm-svn: 21633
 2005-04-30 04:26:06 +00:00
Andrew Lenharth
2a00530fa7 Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends. 
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*.  Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.

llvm-svn: 21599
 2005-04-27 20:10:01 +00:00
Misha Brukman
66d3c6e020 Convert tabs to spaces 
llvm-svn: 21452
 2005-04-22 17:54:37 +00:00
Misha Brukman
1fef885677 Remove trailing whitespace 
llvm-svn: 21425
 2005-04-21 23:30:14 +00:00
Chris Lattner
208da25af0 Match another form of eqv 
llvm-svn: 21413
 2005-04-21 21:09:11 +00:00
Chris Lattner
3d4612c54c Add completely untested support for mtcrf/mfcrf encoding 
llvm-svn: 21353
 2005-04-19 05:41:52 +00:00
Chris Lattner
e6f861f92c switch over the rest of the formats that use RC to use isDOT 
llvm-svn: 21352
 2005-04-19 05:21:30 +00:00
Chris Lattner
082ca8fcab Convert the XForm instrs and XSForm instruction over to use isDOT 
llvm-svn: 21351
 2005-04-19 05:15:18 +00:00
Chris Lattner
3fdfd4e009 Now that the ppc64 and vmx operands of I are always 0, forward substitute 
them away.

llvm-svn: 21350
 2005-04-19 05:05:22 +00:00
Chris Lattner
e6f7713f03 convert over bform and iform instructions 
llvm-svn: 21349
 2005-04-19 05:00:59 +00:00
Chris Lattner
3ae0832381 Convert over DForm and DSForm instructions 
llvm-svn: 21348
 2005-04-19 04:59:28 +00:00
Chris Lattner
4ecf523af4 Convert XLForm and XForm instructions over to use PPC64 when appropriate. 
llvm-svn: 21347
 2005-04-19 04:51:30 +00:00
Chris Lattner
6a2abe8591 Convert XO XS and XFX forms to use isPPC64 
llvm-svn: 21346
 2005-04-19 04:40:07 +00:00
Chris Lattner
3cfa7a24cb Turn PPC64 and VMX into classes that can be added to instructions instead of 
bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over

llvm-svn: 21345
 2005-04-19 04:32:54 +00:00
Nate Begeman
3b1c0df702 Next round of PPC CR optimizations. For the following code: 
int %bar(float %a, float %b, float %c, float %d) {
entry:
    %tmp.1 = setlt float %a, %d
    %tmp.2 = setlt float %b, %d
    %or = or bool %tmp.1, %tmp.2
    %tmp.3 = setgt float %c, %d
    %tmp.4 = or bool %or, %tmp.3
    %tmp.5 = and bool %tmp.4, true
    %retval = cast bool %tmp.5 to int
    ret int %retval
}

We now emit:

_bar:
.LBB_bar_0:     ; entry
        fcmpu cr0, f1, f4
        fcmpu cr1, f2, f4
        cror 0, 0, 4
        fcmpu cr1, f3, f4
        cror 28, 0, 5
        mfcr r2
        rlwinm r3, r2, 29, 31, 31
        blr

Instead of:

_bar:
.LBB_bar_0:     ; entry
        fcmpu cr7, f1, f4
        mfcr r2
        rlwinm r2, r2, 29, 31, 31
        fcmpu cr7, f2, f4
        mfcr r3
        rlwinm r3, r3, 29, 31, 31
        or r2, r2, r3
        fcmpu cr7, f3, f4
        mfcr r3
        rlwinm r3, r3, 30, 31, 31
        or r3, r2, r3
        blr

llvm-svn: 21321
 2005-04-18 07:48:09 +00:00
Nate Begeman
85cd65b389 Change codegen for setcc to read the bit directly out of the condition 
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.

llvm-svn: 21314
 2005-04-18 02:43:24 +00:00
Chris Lattner
a1fd64a073 Handle ExternalSymbol operands in the PPC JIT 
llvm-svn: 21312
 2005-04-18 00:46:10 +00:00
Nate Begeman
ecb5b5c028 Make pattern isel default for ppc 
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309
 2005-04-15 22:12:16 +00:00
Nate Begeman
604895b03c Implement multi-way branches through logical ops on condition registers. 
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.

llvm-svn: 21298
 2005-04-14 09:45:08 +00:00
Nate Begeman
b707ec16b4 Add the necessary support to codegen condition register logical ops with 
register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295
 2005-04-14 03:20:38 +00:00
Nate Begeman
99a9840b56 Start allocating condition registers. Almost all explicit uses of CR0 are 
now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.

llvm-svn: 21294
 2005-04-13 23:15:44 +00:00
Nate Begeman
ae49d52006 Implement the fold shift X, zext(Y) -> shift X, Y at the target level, 
where it is safe to do so.

llvm-svn: 21293
 2005-04-13 22:14:14 +00:00
Nate Begeman
20b3399465 Disbale the broken fold of shift + sz[ext] for now 
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

llvm-svn: 21291
 2005-04-13 21:23:31 +00:00
Chris Lattner
8489ac991d remove one more occurance of this that snuck in 
llvm-svn: 21271
 2005-04-13 02:46:17 +00:00
Chris Lattner
26c7c9150a Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit 
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.

llvm-svn: 21268
 2005-04-13 02:40:26 +00:00
Nate Begeman
a56527ea5f Fold shift by size larger than type size to undef 
Make llvm undef values generate ISD::UNDEF nodes

llvm-svn: 21261
 2005-04-12 23:12:17 +00:00
Nate Begeman
79c8b8fd1c Implement setcc op, -1 sequences 
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm

llvm-svn: 21260
 2005-04-12 21:22:28 +00:00
Nate Begeman
f96b42f1b6 Initial support for allocation condition registers 
llvm-svn: 21246
 2005-04-12 07:04:16 +00:00
Nate Begeman
a154deaaff Implement bitfield clears 
Implement divide by negative power of two

llvm-svn: 21240
 2005-04-12 00:10:02 +00:00
Nate Begeman
f31b58f145 Update PPC readme. Remove things that are done or aren't ppc specific 
llvm-svn: 21232
 2005-04-11 20:48:57 +00:00
Chris Lattner
ee715b2abc ORo sets CR0 
llvm-svn: 21227
 2005-04-11 15:03:48 +00:00
Chris Lattner
7d11f40ee2 Revert the previous patch, which I didn't mean to check in. 
llvm-svn: 21226
 2005-04-11 15:03:41 +00:00
Chris Lattner
d925c74452 Fix a minor bug (ORo didn't mark that it set CR0). 
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;

llvm-svn: 21225
 2005-04-11 15:01:39 +00:00
Nate Begeman
783fe2108e Add recording variants of ISD::AND and ISD::OR. This kills almost 1000 
(1.5%) instructions in 186.crafty

llvm-svn: 21222
 2005-04-11 06:34:10 +00:00
Nate Begeman
34aa7ec9cb Fix another fixme: factor out the constant fp generation code. 
llvm-svn: 21207
 2005-04-10 06:06:10 +00:00
Nate Begeman
b6c9b326e3 Fix 64 bit argument loading that straddles the args in regs / args on stack 
boundary.

llvm-svn: 21206
 2005-04-10 05:53:14 +00:00
Nate Begeman
0a43e95718 Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not 
have to inform the register allocator it might be stepped on.

llvm-svn: 21202
 2005-04-10 03:59:42 +00:00
Nate Begeman
f5cedbc812 Make sure that BRCOND branches can be converted into long branches too. 
llvm-svn: 21198
 2005-04-10 01:48:29 +00:00